meson: convert hw/vfio
[qemu.git] / hw / ppc / spapr.c
1 /*
2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
3 *
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 */
26
27 #include "qemu/osdep.h"
28 #include "qemu-common.h"
29 #include "qapi/error.h"
30 #include "qapi/visitor.h"
31 #include "sysemu/sysemu.h"
32 #include "sysemu/hostmem.h"
33 #include "sysemu/numa.h"
34 #include "sysemu/qtest.h"
35 #include "sysemu/reset.h"
36 #include "sysemu/runstate.h"
37 #include "qemu/log.h"
38 #include "hw/fw-path-provider.h"
39 #include "elf.h"
40 #include "net/net.h"
41 #include "sysemu/device_tree.h"
42 #include "sysemu/cpus.h"
43 #include "sysemu/hw_accel.h"
44 #include "kvm_ppc.h"
45 #include "migration/misc.h"
46 #include "migration/qemu-file-types.h"
47 #include "migration/global_state.h"
48 #include "migration/register.h"
49 #include "migration/blocker.h"
50 #include "mmu-hash64.h"
51 #include "mmu-book3s-v3.h"
52 #include "cpu-models.h"
53 #include "hw/core/cpu.h"
54
55 #include "hw/boards.h"
56 #include "hw/ppc/ppc.h"
57 #include "hw/loader.h"
58
59 #include "hw/ppc/fdt.h"
60 #include "hw/ppc/spapr.h"
61 #include "hw/ppc/spapr_vio.h"
62 #include "hw/qdev-properties.h"
63 #include "hw/pci-host/spapr.h"
64 #include "hw/pci/msi.h"
65
66 #include "hw/pci/pci.h"
67 #include "hw/scsi/scsi.h"
68 #include "hw/virtio/virtio-scsi.h"
69 #include "hw/virtio/vhost-scsi-common.h"
70
71 #include "exec/address-spaces.h"
72 #include "exec/ram_addr.h"
73 #include "hw/usb.h"
74 #include "qemu/config-file.h"
75 #include "qemu/error-report.h"
76 #include "trace.h"
77 #include "hw/nmi.h"
78 #include "hw/intc/intc.h"
79
80 #include "hw/ppc/spapr_cpu_core.h"
81 #include "hw/mem/memory-device.h"
82 #include "hw/ppc/spapr_tpm_proxy.h"
83 #include "hw/ppc/spapr_nvdimm.h"
84
85 #include "monitor/monitor.h"
86
87 #include <libfdt.h>
88
89 /* SLOF memory layout:
90 *
91 * SLOF raw image loaded at 0, copies its romfs right below the flat
92 * device-tree, then position SLOF itself 31M below that
93 *
94 * So we set FW_OVERHEAD to 40MB which should account for all of that
95 * and more
96 *
97 * We load our kernel at 4M, leaving space for SLOF initial image
98 */
99 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */
100 #define FW_MAX_SIZE 0x400000
101 #define FW_FILE_NAME "slof.bin"
102 #define FW_OVERHEAD 0x2800000
103 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
104
105 #define MIN_RMA_SLOF (128 * MiB)
106
107 #define PHANDLE_INTC 0x00001111
108
109 /* These two functions implement the VCPU id numbering: one to compute them
110 * all and one to identify thread 0 of a VCORE. Any change to the first one
111 * is likely to have an impact on the second one, so let's keep them close.
112 */
113 static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index)
114 {
115 MachineState *ms = MACHINE(spapr);
116 unsigned int smp_threads = ms->smp.threads;
117
118 assert(spapr->vsmt);
119 return
120 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads;
121 }
122 static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr,
123 PowerPCCPU *cpu)
124 {
125 assert(spapr->vsmt);
126 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0;
127 }
128
129 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque)
130 {
131 /* Dummy entries correspond to unused ICPState objects in older QEMUs,
132 * and newer QEMUs don't even have them. In both cases, we don't want
133 * to send anything on the wire.
134 */
135 return false;
136 }
137
138 static const VMStateDescription pre_2_10_vmstate_dummy_icp = {
139 .name = "icp/server",
140 .version_id = 1,
141 .minimum_version_id = 1,
142 .needed = pre_2_10_vmstate_dummy_icp_needed,
143 .fields = (VMStateField[]) {
144 VMSTATE_UNUSED(4), /* uint32_t xirr */
145 VMSTATE_UNUSED(1), /* uint8_t pending_priority */
146 VMSTATE_UNUSED(1), /* uint8_t mfrr */
147 VMSTATE_END_OF_LIST()
148 },
149 };
150
151 static void pre_2_10_vmstate_register_dummy_icp(int i)
152 {
153 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp,
154 (void *)(uintptr_t) i);
155 }
156
157 static void pre_2_10_vmstate_unregister_dummy_icp(int i)
158 {
159 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp,
160 (void *)(uintptr_t) i);
161 }
162
163 int spapr_max_server_number(SpaprMachineState *spapr)
164 {
165 MachineState *ms = MACHINE(spapr);
166
167 assert(spapr->vsmt);
168 return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads);
169 }
170
171 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
172 int smt_threads)
173 {
174 int i, ret = 0;
175 uint32_t servers_prop[smt_threads];
176 uint32_t gservers_prop[smt_threads * 2];
177 int index = spapr_get_vcpu_id(cpu);
178
179 if (cpu->compat_pvr) {
180 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr);
181 if (ret < 0) {
182 return ret;
183 }
184 }
185
186 /* Build interrupt servers and gservers properties */
187 for (i = 0; i < smt_threads; i++) {
188 servers_prop[i] = cpu_to_be32(index + i);
189 /* Hack, direct the group queues back to cpu 0 */
190 gservers_prop[i*2] = cpu_to_be32(index + i);
191 gservers_prop[i*2 + 1] = 0;
192 }
193 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
194 servers_prop, sizeof(servers_prop));
195 if (ret < 0) {
196 return ret;
197 }
198 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s",
199 gservers_prop, sizeof(gservers_prop));
200
201 return ret;
202 }
203
204 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu)
205 {
206 int index = spapr_get_vcpu_id(cpu);
207 uint32_t associativity[] = {cpu_to_be32(0x5),
208 cpu_to_be32(0x0),
209 cpu_to_be32(0x0),
210 cpu_to_be32(0x0),
211 cpu_to_be32(cpu->node_id),
212 cpu_to_be32(index)};
213
214 /* Advertise NUMA via ibm,associativity */
215 return fdt_setprop(fdt, offset, "ibm,associativity", associativity,
216 sizeof(associativity));
217 }
218
219 static void spapr_dt_pa_features(SpaprMachineState *spapr,
220 PowerPCCPU *cpu,
221 void *fdt, int offset)
222 {
223 uint8_t pa_features_206[] = { 6, 0,
224 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
225 uint8_t pa_features_207[] = { 24, 0,
226 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
227 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
228 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
229 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
230 uint8_t pa_features_300[] = { 66, 0,
231 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
232 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */
233 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */
234 /* 6: DS207 */
235 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
236 /* 16: Vector */
237 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
238 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */
239 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
240 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
241 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
242 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */
243 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
244 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */
245 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */
246 /* 42: PM, 44: PC RA, 46: SC vec'd */
247 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
248 /* 48: SIMD, 50: QP BFP, 52: String */
249 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
250 /* 54: DecFP, 56: DecI, 58: SHA */
251 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
252 /* 60: NM atomic, 62: RNG */
253 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
254 };
255 uint8_t *pa_features = NULL;
256 size_t pa_size;
257
258 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) {
259 pa_features = pa_features_206;
260 pa_size = sizeof(pa_features_206);
261 }
262 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) {
263 pa_features = pa_features_207;
264 pa_size = sizeof(pa_features_207);
265 }
266 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) {
267 pa_features = pa_features_300;
268 pa_size = sizeof(pa_features_300);
269 }
270 if (!pa_features) {
271 return;
272 }
273
274 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) {
275 /*
276 * Note: we keep CI large pages off by default because a 64K capable
277 * guest provisioned with large pages might otherwise try to map a qemu
278 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
279 * even if that qemu runs on a 4k host.
280 * We dd this bit back here if we are confident this is not an issue
281 */
282 pa_features[3] |= 0x20;
283 }
284 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) {
285 pa_features[24] |= 0x80; /* Transactional memory support */
286 }
287 if (spapr->cas_pre_isa3_guest && pa_size > 40) {
288 /* Workaround for broken kernels that attempt (guest) radix
289 * mode when they can't handle it, if they see the radix bit set
290 * in pa-features. So hide it from them. */
291 pa_features[40 + 2] &= ~0x80; /* Radix MMU */
292 }
293
294 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size)));
295 }
296
297 static hwaddr spapr_node0_size(MachineState *machine)
298 {
299 if (machine->numa_state->num_nodes) {
300 int i;
301 for (i = 0; i < machine->numa_state->num_nodes; ++i) {
302 if (machine->numa_state->nodes[i].node_mem) {
303 return MIN(pow2floor(machine->numa_state->nodes[i].node_mem),
304 machine->ram_size);
305 }
306 }
307 }
308 return machine->ram_size;
309 }
310
311 static void add_str(GString *s, const gchar *s1)
312 {
313 g_string_append_len(s, s1, strlen(s1) + 1);
314 }
315
316 static int spapr_dt_memory_node(void *fdt, int nodeid, hwaddr start,
317 hwaddr size)
318 {
319 uint32_t associativity[] = {
320 cpu_to_be32(0x4), /* length */
321 cpu_to_be32(0x0), cpu_to_be32(0x0),
322 cpu_to_be32(0x0), cpu_to_be32(nodeid)
323 };
324 char mem_name[32];
325 uint64_t mem_reg_property[2];
326 int off;
327
328 mem_reg_property[0] = cpu_to_be64(start);
329 mem_reg_property[1] = cpu_to_be64(size);
330
331 sprintf(mem_name, "memory@%" HWADDR_PRIx, start);
332 off = fdt_add_subnode(fdt, 0, mem_name);
333 _FDT(off);
334 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
335 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
336 sizeof(mem_reg_property))));
337 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
338 sizeof(associativity))));
339 return off;
340 }
341
342 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr)
343 {
344 MemoryDeviceInfoList *info;
345
346 for (info = list; info; info = info->next) {
347 MemoryDeviceInfo *value = info->value;
348
349 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) {
350 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data;
351
352 if (addr >= pcdimm_info->addr &&
353 addr < (pcdimm_info->addr + pcdimm_info->size)) {
354 return pcdimm_info->node;
355 }
356 }
357 }
358
359 return -1;
360 }
361
362 struct sPAPRDrconfCellV2 {
363 uint32_t seq_lmbs;
364 uint64_t base_addr;
365 uint32_t drc_index;
366 uint32_t aa_index;
367 uint32_t flags;
368 } QEMU_PACKED;
369
370 typedef struct DrconfCellQueue {
371 struct sPAPRDrconfCellV2 cell;
372 QSIMPLEQ_ENTRY(DrconfCellQueue) entry;
373 } DrconfCellQueue;
374
375 static DrconfCellQueue *
376 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr,
377 uint32_t drc_index, uint32_t aa_index,
378 uint32_t flags)
379 {
380 DrconfCellQueue *elem;
381
382 elem = g_malloc0(sizeof(*elem));
383 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs);
384 elem->cell.base_addr = cpu_to_be64(base_addr);
385 elem->cell.drc_index = cpu_to_be32(drc_index);
386 elem->cell.aa_index = cpu_to_be32(aa_index);
387 elem->cell.flags = cpu_to_be32(flags);
388
389 return elem;
390 }
391
392 static int spapr_dt_dynamic_memory_v2(SpaprMachineState *spapr, void *fdt,
393 int offset, MemoryDeviceInfoList *dimms)
394 {
395 MachineState *machine = MACHINE(spapr);
396 uint8_t *int_buf, *cur_index;
397 int ret;
398 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
399 uint64_t addr, cur_addr, size;
400 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size);
401 uint64_t mem_end = machine->device_memory->base +
402 memory_region_size(&machine->device_memory->mr);
403 uint32_t node, buf_len, nr_entries = 0;
404 SpaprDrc *drc;
405 DrconfCellQueue *elem, *next;
406 MemoryDeviceInfoList *info;
407 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue
408 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue);
409
410 /* Entry to cover RAM and the gap area */
411 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1,
412 SPAPR_LMB_FLAGS_RESERVED |
413 SPAPR_LMB_FLAGS_DRC_INVALID);
414 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
415 nr_entries++;
416
417 cur_addr = machine->device_memory->base;
418 for (info = dimms; info; info = info->next) {
419 PCDIMMDeviceInfo *di = info->value->u.dimm.data;
420
421 addr = di->addr;
422 size = di->size;
423 node = di->node;
424
425 /*
426 * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The
427 * area is marked hotpluggable in the next iteration for the bigger
428 * chunk including the NVDIMM occupied area.
429 */
430 if (info->value->type == MEMORY_DEVICE_INFO_KIND_NVDIMM)
431 continue;
432
433 /* Entry for hot-pluggable area */
434 if (cur_addr < addr) {
435 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size);
436 g_assert(drc);
437 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size,
438 cur_addr, spapr_drc_index(drc), -1, 0);
439 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
440 nr_entries++;
441 }
442
443 /* Entry for DIMM */
444 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size);
445 g_assert(drc);
446 elem = spapr_get_drconf_cell(size / lmb_size, addr,
447 spapr_drc_index(drc), node,
448 (SPAPR_LMB_FLAGS_ASSIGNED |
449 SPAPR_LMB_FLAGS_HOTREMOVABLE));
450 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
451 nr_entries++;
452 cur_addr = addr + size;
453 }
454
455 /* Entry for remaining hotpluggable area */
456 if (cur_addr < mem_end) {
457 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size);
458 g_assert(drc);
459 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size,
460 cur_addr, spapr_drc_index(drc), -1, 0);
461 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
462 nr_entries++;
463 }
464
465 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t);
466 int_buf = cur_index = g_malloc0(buf_len);
467 *(uint32_t *)int_buf = cpu_to_be32(nr_entries);
468 cur_index += sizeof(nr_entries);
469
470 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) {
471 memcpy(cur_index, &elem->cell, sizeof(elem->cell));
472 cur_index += sizeof(elem->cell);
473 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry);
474 g_free(elem);
475 }
476
477 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len);
478 g_free(int_buf);
479 if (ret < 0) {
480 return -1;
481 }
482 return 0;
483 }
484
485 static int spapr_dt_dynamic_memory(SpaprMachineState *spapr, void *fdt,
486 int offset, MemoryDeviceInfoList *dimms)
487 {
488 MachineState *machine = MACHINE(spapr);
489 int i, ret;
490 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
491 uint32_t device_lmb_start = machine->device_memory->base / lmb_size;
492 uint32_t nr_lmbs = (machine->device_memory->base +
493 memory_region_size(&machine->device_memory->mr)) /
494 lmb_size;
495 uint32_t *int_buf, *cur_index, buf_len;
496
497 /*
498 * Allocate enough buffer size to fit in ibm,dynamic-memory
499 */
500 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t);
501 cur_index = int_buf = g_malloc0(buf_len);
502 int_buf[0] = cpu_to_be32(nr_lmbs);
503 cur_index++;
504 for (i = 0; i < nr_lmbs; i++) {
505 uint64_t addr = i * lmb_size;
506 uint32_t *dynamic_memory = cur_index;
507
508 if (i >= device_lmb_start) {
509 SpaprDrc *drc;
510
511 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i);
512 g_assert(drc);
513
514 dynamic_memory[0] = cpu_to_be32(addr >> 32);
515 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
516 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc));
517 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
518 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr));
519 if (memory_region_present(get_system_memory(), addr)) {
520 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED);
521 } else {
522 dynamic_memory[5] = cpu_to_be32(0);
523 }
524 } else {
525 /*
526 * LMB information for RMA, boot time RAM and gap b/n RAM and
527 * device memory region -- all these are marked as reserved
528 * and as having no valid DRC.
529 */
530 dynamic_memory[0] = cpu_to_be32(addr >> 32);
531 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
532 dynamic_memory[2] = cpu_to_be32(0);
533 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
534 dynamic_memory[4] = cpu_to_be32(-1);
535 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED |
536 SPAPR_LMB_FLAGS_DRC_INVALID);
537 }
538
539 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE;
540 }
541 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len);
542 g_free(int_buf);
543 if (ret < 0) {
544 return -1;
545 }
546 return 0;
547 }
548
549 /*
550 * Adds ibm,dynamic-reconfiguration-memory node.
551 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
552 * of this device tree node.
553 */
554 static int spapr_dt_dynamic_reconfiguration_memory(SpaprMachineState *spapr,
555 void *fdt)
556 {
557 MachineState *machine = MACHINE(spapr);
558 int nb_numa_nodes = machine->numa_state->num_nodes;
559 int ret, i, offset;
560 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
561 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)};
562 uint32_t *int_buf, *cur_index, buf_len;
563 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1;
564 MemoryDeviceInfoList *dimms = NULL;
565
566 /*
567 * Don't create the node if there is no device memory
568 */
569 if (machine->ram_size == machine->maxram_size) {
570 return 0;
571 }
572
573 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory");
574
575 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size,
576 sizeof(prop_lmb_size));
577 if (ret < 0) {
578 return ret;
579 }
580
581 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff);
582 if (ret < 0) {
583 return ret;
584 }
585
586 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0);
587 if (ret < 0) {
588 return ret;
589 }
590
591 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */
592 dimms = qmp_memory_device_list();
593 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) {
594 ret = spapr_dt_dynamic_memory_v2(spapr, fdt, offset, dimms);
595 } else {
596 ret = spapr_dt_dynamic_memory(spapr, fdt, offset, dimms);
597 }
598 qapi_free_MemoryDeviceInfoList(dimms);
599
600 if (ret < 0) {
601 return ret;
602 }
603
604 /* ibm,associativity-lookup-arrays */
605 buf_len = (nr_nodes * 4 + 2) * sizeof(uint32_t);
606 cur_index = int_buf = g_malloc0(buf_len);
607 int_buf[0] = cpu_to_be32(nr_nodes);
608 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */
609 cur_index += 2;
610 for (i = 0; i < nr_nodes; i++) {
611 uint32_t associativity[] = {
612 cpu_to_be32(0x0),
613 cpu_to_be32(0x0),
614 cpu_to_be32(0x0),
615 cpu_to_be32(i)
616 };
617 memcpy(cur_index, associativity, sizeof(associativity));
618 cur_index += 4;
619 }
620 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf,
621 (cur_index - int_buf) * sizeof(uint32_t));
622 g_free(int_buf);
623
624 return ret;
625 }
626
627 static int spapr_dt_memory(SpaprMachineState *spapr, void *fdt)
628 {
629 MachineState *machine = MACHINE(spapr);
630 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
631 hwaddr mem_start, node_size;
632 int i, nb_nodes = machine->numa_state->num_nodes;
633 NodeInfo *nodes = machine->numa_state->nodes;
634
635 for (i = 0, mem_start = 0; i < nb_nodes; ++i) {
636 if (!nodes[i].node_mem) {
637 continue;
638 }
639 if (mem_start >= machine->ram_size) {
640 node_size = 0;
641 } else {
642 node_size = nodes[i].node_mem;
643 if (node_size > machine->ram_size - mem_start) {
644 node_size = machine->ram_size - mem_start;
645 }
646 }
647 if (!mem_start) {
648 /* spapr_machine_init() checks for rma_size <= node0_size
649 * already */
650 spapr_dt_memory_node(fdt, i, 0, spapr->rma_size);
651 mem_start += spapr->rma_size;
652 node_size -= spapr->rma_size;
653 }
654 for ( ; node_size; ) {
655 hwaddr sizetmp = pow2floor(node_size);
656
657 /* mem_start != 0 here */
658 if (ctzl(mem_start) < ctzl(sizetmp)) {
659 sizetmp = 1ULL << ctzl(mem_start);
660 }
661
662 spapr_dt_memory_node(fdt, i, mem_start, sizetmp);
663 node_size -= sizetmp;
664 mem_start += sizetmp;
665 }
666 }
667
668 /* Generate ibm,dynamic-reconfiguration-memory node if required */
669 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRCONF_MEMORY)) {
670 int ret;
671
672 g_assert(smc->dr_lmb_enabled);
673 ret = spapr_dt_dynamic_reconfiguration_memory(spapr, fdt);
674 if (ret) {
675 return ret;
676 }
677 }
678
679 return 0;
680 }
681
682 static void spapr_dt_cpu(CPUState *cs, void *fdt, int offset,
683 SpaprMachineState *spapr)
684 {
685 MachineState *ms = MACHINE(spapr);
686 PowerPCCPU *cpu = POWERPC_CPU(cs);
687 CPUPPCState *env = &cpu->env;
688 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
689 int index = spapr_get_vcpu_id(cpu);
690 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
691 0xffffffff, 0xffffffff};
692 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq()
693 : SPAPR_TIMEBASE_FREQ;
694 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
695 uint32_t page_sizes_prop[64];
696 size_t page_sizes_prop_size;
697 unsigned int smp_threads = ms->smp.threads;
698 uint32_t vcpus_per_socket = smp_threads * ms->smp.cores;
699 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
700 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu));
701 SpaprDrc *drc;
702 int drc_index;
703 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ];
704 int i;
705
706 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index);
707 if (drc) {
708 drc_index = spapr_drc_index(drc);
709 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)));
710 }
711
712 _FDT((fdt_setprop_cell(fdt, offset, "reg", index)));
713 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
714
715 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
716 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
717 env->dcache_line_size)));
718 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
719 env->dcache_line_size)));
720 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
721 env->icache_line_size)));
722 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
723 env->icache_line_size)));
724
725 if (pcc->l1_dcache_size) {
726 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
727 pcc->l1_dcache_size)));
728 } else {
729 warn_report("Unknown L1 dcache size for cpu");
730 }
731 if (pcc->l1_icache_size) {
732 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
733 pcc->l1_icache_size)));
734 } else {
735 warn_report("Unknown L1 icache size for cpu");
736 }
737
738 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
739 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
740 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size)));
741 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size)));
742 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
743 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
744
745 if (env->spr_cb[SPR_PURR].oea_read) {
746 _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1)));
747 }
748 if (env->spr_cb[SPR_SPURR].oea_read) {
749 _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1)));
750 }
751
752 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) {
753 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
754 segs, sizeof(segs))));
755 }
756
757 /* Advertise VSX (vector extensions) if available
758 * 1 == VMX / Altivec available
759 * 2 == VSX available
760 *
761 * Only CPUs for which we create core types in spapr_cpu_core.c
762 * are possible, and all of those have VMX */
763 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) {
764 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2)));
765 } else {
766 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1)));
767 }
768
769 /* Advertise DFP (Decimal Floating Point) if available
770 * 0 / no property == no DFP
771 * 1 == DFP available */
772 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) {
773 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
774 }
775
776 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop,
777 sizeof(page_sizes_prop));
778 if (page_sizes_prop_size) {
779 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
780 page_sizes_prop, page_sizes_prop_size)));
781 }
782
783 spapr_dt_pa_features(spapr, cpu, fdt, offset);
784
785 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
786 cs->cpu_index / vcpus_per_socket)));
787
788 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size",
789 pft_size_prop, sizeof(pft_size_prop))));
790
791 if (ms->numa_state->num_nodes > 1) {
792 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu));
793 }
794
795 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt));
796
797 if (pcc->radix_page_info) {
798 for (i = 0; i < pcc->radix_page_info->count; i++) {
799 radix_AP_encodings[i] =
800 cpu_to_be32(pcc->radix_page_info->entries[i]);
801 }
802 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings",
803 radix_AP_encodings,
804 pcc->radix_page_info->count *
805 sizeof(radix_AP_encodings[0]))));
806 }
807
808 /*
809 * We set this property to let the guest know that it can use the large
810 * decrementer and its width in bits.
811 */
812 if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF)
813 _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits",
814 pcc->lrg_decr_bits)));
815 }
816
817 static void spapr_dt_cpus(void *fdt, SpaprMachineState *spapr)
818 {
819 CPUState **rev;
820 CPUState *cs;
821 int n_cpus;
822 int cpus_offset;
823 char *nodename;
824 int i;
825
826 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
827 _FDT(cpus_offset);
828 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
829 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
830
831 /*
832 * We walk the CPUs in reverse order to ensure that CPU DT nodes
833 * created by fdt_add_subnode() end up in the right order in FDT
834 * for the guest kernel the enumerate the CPUs correctly.
835 *
836 * The CPU list cannot be traversed in reverse order, so we need
837 * to do extra work.
838 */
839 n_cpus = 0;
840 rev = NULL;
841 CPU_FOREACH(cs) {
842 rev = g_renew(CPUState *, rev, n_cpus + 1);
843 rev[n_cpus++] = cs;
844 }
845
846 for (i = n_cpus - 1; i >= 0; i--) {
847 CPUState *cs = rev[i];
848 PowerPCCPU *cpu = POWERPC_CPU(cs);
849 int index = spapr_get_vcpu_id(cpu);
850 DeviceClass *dc = DEVICE_GET_CLASS(cs);
851 int offset;
852
853 if (!spapr_is_thread0_in_vcore(spapr, cpu)) {
854 continue;
855 }
856
857 nodename = g_strdup_printf("%s@%x", dc->fw_name, index);
858 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
859 g_free(nodename);
860 _FDT(offset);
861 spapr_dt_cpu(cs, fdt, offset, spapr);
862 }
863
864 g_free(rev);
865 }
866
867 static int spapr_dt_rng(void *fdt)
868 {
869 int node;
870 int ret;
871
872 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities");
873 if (node <= 0) {
874 return -1;
875 }
876 ret = fdt_setprop_string(fdt, node, "device_type",
877 "ibm,platform-facilities");
878 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1);
879 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0);
880
881 node = fdt_add_subnode(fdt, node, "ibm,random-v1");
882 if (node <= 0) {
883 return -1;
884 }
885 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random");
886
887 return ret ? -1 : 0;
888 }
889
890 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt)
891 {
892 MachineState *ms = MACHINE(spapr);
893 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms);
894 int rtas;
895 GString *hypertas = g_string_sized_new(256);
896 GString *qemu_hypertas = g_string_sized_new(256);
897 uint32_t refpoints[] = {
898 cpu_to_be32(0x4),
899 cpu_to_be32(0x4),
900 cpu_to_be32(0x2),
901 };
902 uint32_t nr_refpoints = ARRAY_SIZE(refpoints);
903 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base +
904 memory_region_size(&MACHINE(spapr)->device_memory->mr);
905 uint32_t lrdr_capacity[] = {
906 cpu_to_be32(max_device_addr >> 32),
907 cpu_to_be32(max_device_addr & 0xffffffff),
908 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE),
909 cpu_to_be32(ms->smp.max_cpus / ms->smp.threads),
910 };
911 uint32_t maxdomain = cpu_to_be32(spapr->gpu_numa_id > 1 ? 1 : 0);
912 uint32_t maxdomains[] = {
913 cpu_to_be32(4),
914 maxdomain,
915 maxdomain,
916 maxdomain,
917 cpu_to_be32(spapr->gpu_numa_id),
918 };
919
920 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas"));
921
922 /* hypertas */
923 add_str(hypertas, "hcall-pft");
924 add_str(hypertas, "hcall-term");
925 add_str(hypertas, "hcall-dabr");
926 add_str(hypertas, "hcall-interrupt");
927 add_str(hypertas, "hcall-tce");
928 add_str(hypertas, "hcall-vio");
929 add_str(hypertas, "hcall-splpar");
930 add_str(hypertas, "hcall-join");
931 add_str(hypertas, "hcall-bulk");
932 add_str(hypertas, "hcall-set-mode");
933 add_str(hypertas, "hcall-sprg0");
934 add_str(hypertas, "hcall-copy");
935 add_str(hypertas, "hcall-debug");
936 add_str(hypertas, "hcall-vphn");
937 add_str(qemu_hypertas, "hcall-memop1");
938
939 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
940 add_str(hypertas, "hcall-multi-tce");
941 }
942
943 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) {
944 add_str(hypertas, "hcall-hpt-resize");
945 }
946
947 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions",
948 hypertas->str, hypertas->len));
949 g_string_free(hypertas, TRUE);
950 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions",
951 qemu_hypertas->str, qemu_hypertas->len));
952 g_string_free(qemu_hypertas, TRUE);
953
954 if (smc->pre_5_1_assoc_refpoints) {
955 nr_refpoints = 2;
956 }
957
958 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points",
959 refpoints, nr_refpoints * sizeof(refpoints[0])));
960
961 _FDT(fdt_setprop(fdt, rtas, "ibm,max-associativity-domains",
962 maxdomains, sizeof(maxdomains)));
963
964 /*
965 * FWNMI reserves RTAS_ERROR_LOG_MAX for the machine check error log,
966 * and 16 bytes per CPU for system reset error log plus an extra 8 bytes.
967 *
968 * The system reset requirements are driven by existing Linux and PowerVM
969 * implementation which (contrary to PAPR) saves r3 in the error log
970 * structure like machine check, so Linux expects to find the saved r3
971 * value at the address in r3 upon FWNMI-enabled sreset interrupt (and
972 * does not look at the error value).
973 *
974 * System reset interrupts are not subject to interlock like machine
975 * check, so this memory area could be corrupted if the sreset is
976 * interrupted by a machine check (or vice versa) if it was shared. To
977 * prevent this, system reset uses per-CPU areas for the sreset save
978 * area. A system reset that interrupts a system reset handler could
979 * still overwrite this area, but Linux doesn't try to recover in that
980 * case anyway.
981 *
982 * The extra 8 bytes is required because Linux's FWNMI error log check
983 * is off-by-one.
984 */
985 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-size", RTAS_ERROR_LOG_MAX +
986 ms->smp.max_cpus * sizeof(uint64_t)*2 + sizeof(uint64_t)));
987 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max",
988 RTAS_ERROR_LOG_MAX));
989 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate",
990 RTAS_EVENT_SCAN_RATE));
991
992 g_assert(msi_nonbroken);
993 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0));
994
995 /*
996 * According to PAPR, rtas ibm,os-term does not guarantee a return
997 * back to the guest cpu.
998 *
999 * While an additional ibm,extended-os-term property indicates
1000 * that rtas call return will always occur. Set this property.
1001 */
1002 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0));
1003
1004 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity",
1005 lrdr_capacity, sizeof(lrdr_capacity)));
1006
1007 spapr_dt_rtas_tokens(fdt, rtas);
1008 }
1009
1010 /*
1011 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU
1012 * and the XIVE features that the guest may request and thus the valid
1013 * values for bytes 23..26 of option vector 5:
1014 */
1015 static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt,
1016 int chosen)
1017 {
1018 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu);
1019
1020 char val[2 * 4] = {
1021 23, 0x00, /* XICS / XIVE mode */
1022 24, 0x00, /* Hash/Radix, filled in below. */
1023 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */
1024 26, 0x40, /* Radix options: GTSE == yes. */
1025 };
1026
1027 if (spapr->irq->xics && spapr->irq->xive) {
1028 val[1] = SPAPR_OV5_XIVE_BOTH;
1029 } else if (spapr->irq->xive) {
1030 val[1] = SPAPR_OV5_XIVE_EXPLOIT;
1031 } else {
1032 assert(spapr->irq->xics);
1033 val[1] = SPAPR_OV5_XIVE_LEGACY;
1034 }
1035
1036 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0,
1037 first_ppc_cpu->compat_pvr)) {
1038 /*
1039 * If we're in a pre POWER9 compat mode then the guest should
1040 * do hash and use the legacy interrupt mode
1041 */
1042 val[1] = SPAPR_OV5_XIVE_LEGACY; /* XICS */
1043 val[3] = 0x00; /* Hash */
1044 } else if (kvm_enabled()) {
1045 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) {
1046 val[3] = 0x80; /* OV5_MMU_BOTH */
1047 } else if (kvmppc_has_cap_mmu_radix()) {
1048 val[3] = 0x40; /* OV5_MMU_RADIX_300 */
1049 } else {
1050 val[3] = 0x00; /* Hash */
1051 }
1052 } else {
1053 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */
1054 val[3] = 0xC0;
1055 }
1056 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support",
1057 val, sizeof(val)));
1058 }
1059
1060 static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt, bool reset)
1061 {
1062 MachineState *machine = MACHINE(spapr);
1063 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
1064 int chosen;
1065
1066 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen"));
1067
1068 if (reset) {
1069 const char *boot_device = machine->boot_order;
1070 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus);
1071 size_t cb = 0;
1072 char *bootlist = get_boot_devices_list(&cb);
1073
1074 if (machine->kernel_cmdline && machine->kernel_cmdline[0]) {
1075 _FDT(fdt_setprop_string(fdt, chosen, "bootargs",
1076 machine->kernel_cmdline));
1077 }
1078
1079 if (spapr->initrd_size) {
1080 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start",
1081 spapr->initrd_base));
1082 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end",
1083 spapr->initrd_base + spapr->initrd_size));
1084 }
1085
1086 if (spapr->kernel_size) {
1087 uint64_t kprop[2] = { cpu_to_be64(spapr->kernel_addr),
1088 cpu_to_be64(spapr->kernel_size) };
1089
1090 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel",
1091 &kprop, sizeof(kprop)));
1092 if (spapr->kernel_le) {
1093 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0));
1094 }
1095 }
1096 if (boot_menu) {
1097 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu)));
1098 }
1099 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width));
1100 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height));
1101 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth));
1102
1103 if (cb && bootlist) {
1104 int i;
1105
1106 for (i = 0; i < cb; i++) {
1107 if (bootlist[i] == '\n') {
1108 bootlist[i] = ' ';
1109 }
1110 }
1111 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist));
1112 }
1113
1114 if (boot_device && strlen(boot_device)) {
1115 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device));
1116 }
1117
1118 if (!spapr->has_graphics && stdout_path) {
1119 /*
1120 * "linux,stdout-path" and "stdout" properties are
1121 * deprecated by linux kernel. New platforms should only
1122 * use the "stdout-path" property. Set the new property
1123 * and continue using older property to remain compatible
1124 * with the existing firmware.
1125 */
1126 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path));
1127 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path));
1128 }
1129
1130 /*
1131 * We can deal with BAR reallocation just fine, advertise it
1132 * to the guest
1133 */
1134 if (smc->linux_pci_probe) {
1135 _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0));
1136 }
1137
1138 spapr_dt_ov5_platform_support(spapr, fdt, chosen);
1139
1140 g_free(stdout_path);
1141 g_free(bootlist);
1142 }
1143
1144 _FDT(spapr_dt_ovec(fdt, chosen, spapr->ov5_cas, "ibm,architecture-vec-5"));
1145 }
1146
1147 static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt)
1148 {
1149 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR
1150 * KVM to work under pHyp with some guest co-operation */
1151 int hypervisor;
1152 uint8_t hypercall[16];
1153
1154 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor"));
1155 /* indicate KVM hypercall interface */
1156 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm"));
1157 if (kvmppc_has_cap_fixup_hcalls()) {
1158 /*
1159 * Older KVM versions with older guest kernels were broken
1160 * with the magic page, don't allow the guest to map it.
1161 */
1162 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall,
1163 sizeof(hypercall))) {
1164 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions",
1165 hypercall, sizeof(hypercall)));
1166 }
1167 }
1168 }
1169
1170 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space)
1171 {
1172 MachineState *machine = MACHINE(spapr);
1173 MachineClass *mc = MACHINE_GET_CLASS(machine);
1174 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
1175 int ret;
1176 void *fdt;
1177 SpaprPhbState *phb;
1178 char *buf;
1179
1180 fdt = g_malloc0(space);
1181 _FDT((fdt_create_empty_tree(fdt, space)));
1182
1183 /* Root node */
1184 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp"));
1185 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)"));
1186 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries"));
1187
1188 /* Guest UUID & Name*/
1189 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
1190 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf));
1191 if (qemu_uuid_set) {
1192 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf));
1193 }
1194 g_free(buf);
1195
1196 if (qemu_get_vm_name()) {
1197 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name",
1198 qemu_get_vm_name()));
1199 }
1200
1201 /* Host Model & Serial Number */
1202 if (spapr->host_model) {
1203 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model));
1204 } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) {
1205 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf));
1206 g_free(buf);
1207 }
1208
1209 if (spapr->host_serial) {
1210 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial));
1211 } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) {
1212 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf));
1213 g_free(buf);
1214 }
1215
1216 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2));
1217 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2));
1218
1219 /* /interrupt controller */
1220 spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC);
1221
1222 ret = spapr_dt_memory(spapr, fdt);
1223 if (ret < 0) {
1224 error_report("couldn't setup memory nodes in fdt");
1225 exit(1);
1226 }
1227
1228 /* /vdevice */
1229 spapr_dt_vdevice(spapr->vio_bus, fdt);
1230
1231 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) {
1232 ret = spapr_dt_rng(fdt);
1233 if (ret < 0) {
1234 error_report("could not set up rng device in the fdt");
1235 exit(1);
1236 }
1237 }
1238
1239 QLIST_FOREACH(phb, &spapr->phbs, list) {
1240 ret = spapr_dt_phb(spapr, phb, PHANDLE_INTC, fdt, NULL);
1241 if (ret < 0) {
1242 error_report("couldn't setup PCI devices in fdt");
1243 exit(1);
1244 }
1245 }
1246
1247 spapr_dt_cpus(fdt, spapr);
1248
1249 if (smc->dr_lmb_enabled) {
1250 _FDT(spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB));
1251 }
1252
1253 if (mc->has_hotpluggable_cpus) {
1254 int offset = fdt_path_offset(fdt, "/cpus");
1255 ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU);
1256 if (ret < 0) {
1257 error_report("Couldn't set up CPU DR device tree properties");
1258 exit(1);
1259 }
1260 }
1261
1262 /* /event-sources */
1263 spapr_dt_events(spapr, fdt);
1264
1265 /* /rtas */
1266 spapr_dt_rtas(spapr, fdt);
1267
1268 /* /chosen */
1269 spapr_dt_chosen(spapr, fdt, reset);
1270
1271 /* /hypervisor */
1272 if (kvm_enabled()) {
1273 spapr_dt_hypervisor(spapr, fdt);
1274 }
1275
1276 /* Build memory reserve map */
1277 if (reset) {
1278 if (spapr->kernel_size) {
1279 _FDT((fdt_add_mem_rsv(fdt, spapr->kernel_addr,
1280 spapr->kernel_size)));
1281 }
1282 if (spapr->initrd_size) {
1283 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base,
1284 spapr->initrd_size)));
1285 }
1286 }
1287
1288 if (smc->dr_phb_enabled) {
1289 ret = spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_PHB);
1290 if (ret < 0) {
1291 error_report("Couldn't set up PHB DR device tree properties");
1292 exit(1);
1293 }
1294 }
1295
1296 /* NVDIMM devices */
1297 if (mc->nvdimm_supported) {
1298 spapr_dt_persistent_memory(fdt);
1299 }
1300
1301 return fdt;
1302 }
1303
1304 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
1305 {
1306 SpaprMachineState *spapr = opaque;
1307
1308 return (addr & 0x0fffffff) + spapr->kernel_addr;
1309 }
1310
1311 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp,
1312 PowerPCCPU *cpu)
1313 {
1314 CPUPPCState *env = &cpu->env;
1315
1316 /* The TCG path should also be holding the BQL at this point */
1317 g_assert(qemu_mutex_iothread_locked());
1318
1319 if (msr_pr) {
1320 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1321 env->gpr[3] = H_PRIVILEGE;
1322 } else {
1323 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]);
1324 }
1325 }
1326
1327 struct LPCRSyncState {
1328 target_ulong value;
1329 target_ulong mask;
1330 };
1331
1332 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg)
1333 {
1334 struct LPCRSyncState *s = arg.host_ptr;
1335 PowerPCCPU *cpu = POWERPC_CPU(cs);
1336 CPUPPCState *env = &cpu->env;
1337 target_ulong lpcr;
1338
1339 cpu_synchronize_state(cs);
1340 lpcr = env->spr[SPR_LPCR];
1341 lpcr &= ~s->mask;
1342 lpcr |= s->value;
1343 ppc_store_lpcr(cpu, lpcr);
1344 }
1345
1346 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask)
1347 {
1348 CPUState *cs;
1349 struct LPCRSyncState s = {
1350 .value = value,
1351 .mask = mask
1352 };
1353 CPU_FOREACH(cs) {
1354 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s));
1355 }
1356 }
1357
1358 static void spapr_get_pate(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry)
1359 {
1360 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1361
1362 /* Copy PATE1:GR into PATE0:HR */
1363 entry->dw0 = spapr->patb_entry & PATE0_HR;
1364 entry->dw1 = spapr->patb_entry;
1365 }
1366
1367 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1368 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1369 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1370 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1371 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1372
1373 /*
1374 * Get the fd to access the kernel htab, re-opening it if necessary
1375 */
1376 static int get_htab_fd(SpaprMachineState *spapr)
1377 {
1378 Error *local_err = NULL;
1379
1380 if (spapr->htab_fd >= 0) {
1381 return spapr->htab_fd;
1382 }
1383
1384 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err);
1385 if (spapr->htab_fd < 0) {
1386 error_report_err(local_err);
1387 }
1388
1389 return spapr->htab_fd;
1390 }
1391
1392 void close_htab_fd(SpaprMachineState *spapr)
1393 {
1394 if (spapr->htab_fd >= 0) {
1395 close(spapr->htab_fd);
1396 }
1397 spapr->htab_fd = -1;
1398 }
1399
1400 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp)
1401 {
1402 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1403
1404 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1;
1405 }
1406
1407 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp)
1408 {
1409 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1410
1411 assert(kvm_enabled());
1412
1413 if (!spapr->htab) {
1414 return 0;
1415 }
1416
1417 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18);
1418 }
1419
1420 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp,
1421 hwaddr ptex, int n)
1422 {
1423 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1424 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64;
1425
1426 if (!spapr->htab) {
1427 /*
1428 * HTAB is controlled by KVM. Fetch into temporary buffer
1429 */
1430 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64);
1431 kvmppc_read_hptes(hptes, ptex, n);
1432 return hptes;
1433 }
1434
1435 /*
1436 * HTAB is controlled by QEMU. Just point to the internally
1437 * accessible PTEG.
1438 */
1439 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset);
1440 }
1441
1442 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp,
1443 const ppc_hash_pte64_t *hptes,
1444 hwaddr ptex, int n)
1445 {
1446 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1447
1448 if (!spapr->htab) {
1449 g_free((void *)hptes);
1450 }
1451
1452 /* Nothing to do for qemu managed HPT */
1453 }
1454
1455 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex,
1456 uint64_t pte0, uint64_t pte1)
1457 {
1458 SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp);
1459 hwaddr offset = ptex * HASH_PTE_SIZE_64;
1460
1461 if (!spapr->htab) {
1462 kvmppc_write_hpte(ptex, pte0, pte1);
1463 } else {
1464 if (pte0 & HPTE64_V_VALID) {
1465 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1);
1466 /*
1467 * When setting valid, we write PTE1 first. This ensures
1468 * proper synchronization with the reading code in
1469 * ppc_hash64_pteg_search()
1470 */
1471 smp_wmb();
1472 stq_p(spapr->htab + offset, pte0);
1473 } else {
1474 stq_p(spapr->htab + offset, pte0);
1475 /*
1476 * When clearing it we set PTE0 first. This ensures proper
1477 * synchronization with the reading code in
1478 * ppc_hash64_pteg_search()
1479 */
1480 smp_wmb();
1481 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1);
1482 }
1483 }
1484 }
1485
1486 static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex,
1487 uint64_t pte1)
1488 {
1489 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 15;
1490 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1491
1492 if (!spapr->htab) {
1493 /* There should always be a hash table when this is called */
1494 error_report("spapr_hpte_set_c called with no hash table !");
1495 return;
1496 }
1497
1498 /* The HW performs a non-atomic byte update */
1499 stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80);
1500 }
1501
1502 static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex,
1503 uint64_t pte1)
1504 {
1505 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 14;
1506 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1507
1508 if (!spapr->htab) {
1509 /* There should always be a hash table when this is called */
1510 error_report("spapr_hpte_set_r called with no hash table !");
1511 return;
1512 }
1513
1514 /* The HW performs a non-atomic byte update */
1515 stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01);
1516 }
1517
1518 int spapr_hpt_shift_for_ramsize(uint64_t ramsize)
1519 {
1520 int shift;
1521
1522 /* We aim for a hash table of size 1/128 the size of RAM (rounded
1523 * up). The PAPR recommendation is actually 1/64 of RAM size, but
1524 * that's much more than is needed for Linux guests */
1525 shift = ctz64(pow2ceil(ramsize)) - 7;
1526 shift = MAX(shift, 18); /* Minimum architected size */
1527 shift = MIN(shift, 46); /* Maximum architected size */
1528 return shift;
1529 }
1530
1531 void spapr_free_hpt(SpaprMachineState *spapr)
1532 {
1533 g_free(spapr->htab);
1534 spapr->htab = NULL;
1535 spapr->htab_shift = 0;
1536 close_htab_fd(spapr);
1537 }
1538
1539 void spapr_reallocate_hpt(SpaprMachineState *spapr, int shift,
1540 Error **errp)
1541 {
1542 long rc;
1543
1544 /* Clean up any HPT info from a previous boot */
1545 spapr_free_hpt(spapr);
1546
1547 rc = kvmppc_reset_htab(shift);
1548 if (rc < 0) {
1549 /* kernel-side HPT needed, but couldn't allocate one */
1550 error_setg_errno(errp, errno,
1551 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1552 shift);
1553 /* This is almost certainly fatal, but if the caller really
1554 * wants to carry on with shift == 0, it's welcome to try */
1555 } else if (rc > 0) {
1556 /* kernel-side HPT allocated */
1557 if (rc != shift) {
1558 error_setg(errp,
1559 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1560 shift, rc);
1561 }
1562
1563 spapr->htab_shift = shift;
1564 spapr->htab = NULL;
1565 } else {
1566 /* kernel-side HPT not needed, allocate in userspace instead */
1567 size_t size = 1ULL << shift;
1568 int i;
1569
1570 spapr->htab = qemu_memalign(size, size);
1571 if (!spapr->htab) {
1572 error_setg_errno(errp, errno,
1573 "Could not allocate HPT of order %d", shift);
1574 return;
1575 }
1576
1577 memset(spapr->htab, 0, size);
1578 spapr->htab_shift = shift;
1579
1580 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) {
1581 DIRTY_HPTE(HPTE(spapr->htab, i));
1582 }
1583 }
1584 /* We're setting up a hash table, so that means we're not radix */
1585 spapr->patb_entry = 0;
1586 spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT);
1587 }
1588
1589 void spapr_setup_hpt(SpaprMachineState *spapr)
1590 {
1591 int hpt_shift;
1592
1593 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) {
1594 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size);
1595 } else {
1596 uint64_t current_ram_size;
1597
1598 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size();
1599 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size);
1600 }
1601 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal);
1602
1603 if (kvm_enabled()) {
1604 hwaddr vrma_limit = kvmppc_vrma_limit(spapr->htab_shift);
1605
1606 /* Check our RMA fits in the possible VRMA */
1607 if (vrma_limit < spapr->rma_size) {
1608 error_report("Unable to create %" HWADDR_PRIu
1609 "MiB RMA (VRMA only allows %" HWADDR_PRIu "MiB",
1610 spapr->rma_size / MiB, vrma_limit / MiB);
1611 exit(EXIT_FAILURE);
1612 }
1613 }
1614 }
1615
1616 static int spapr_reset_drcs(Object *child, void *opaque)
1617 {
1618 SpaprDrc *drc =
1619 (SpaprDrc *) object_dynamic_cast(child,
1620 TYPE_SPAPR_DR_CONNECTOR);
1621
1622 if (drc) {
1623 spapr_drc_reset(drc);
1624 }
1625
1626 return 0;
1627 }
1628
1629 static void spapr_machine_reset(MachineState *machine)
1630 {
1631 SpaprMachineState *spapr = SPAPR_MACHINE(machine);
1632 PowerPCCPU *first_ppc_cpu;
1633 hwaddr fdt_addr;
1634 void *fdt;
1635 int rc;
1636
1637 kvmppc_svm_off(&error_fatal);
1638 spapr_caps_apply(spapr);
1639
1640 first_ppc_cpu = POWERPC_CPU(first_cpu);
1641 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() &&
1642 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0,
1643 spapr->max_compat_pvr)) {
1644 /*
1645 * If using KVM with radix mode available, VCPUs can be started
1646 * without a HPT because KVM will start them in radix mode.
1647 * Set the GR bit in PATE so that we know there is no HPT.
1648 */
1649 spapr->patb_entry = PATE1_GR;
1650 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT);
1651 } else {
1652 spapr_setup_hpt(spapr);
1653 }
1654
1655 qemu_devices_reset();
1656
1657 spapr_ovec_cleanup(spapr->ov5_cas);
1658 spapr->ov5_cas = spapr_ovec_new();
1659
1660 ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal);
1661
1662 /*
1663 * This is fixing some of the default configuration of the XIVE
1664 * devices. To be called after the reset of the machine devices.
1665 */
1666 spapr_irq_reset(spapr, &error_fatal);
1667
1668 /*
1669 * There is no CAS under qtest. Simulate one to please the code that
1670 * depends on spapr->ov5_cas. This is especially needed to test device
1671 * unplug, so we do that before resetting the DRCs.
1672 */
1673 if (qtest_enabled()) {
1674 spapr_ovec_cleanup(spapr->ov5_cas);
1675 spapr->ov5_cas = spapr_ovec_clone(spapr->ov5);
1676 }
1677
1678 /* DRC reset may cause a device to be unplugged. This will cause troubles
1679 * if this device is used by another device (eg, a running vhost backend
1680 * will crash QEMU if the DIMM holding the vring goes away). To avoid such
1681 * situations, we reset DRCs after all devices have been reset.
1682 */
1683 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL);
1684
1685 spapr_clear_pending_events(spapr);
1686
1687 /*
1688 * We place the device tree and RTAS just below either the top of the RMA,
1689 * or just below 2GB, whichever is lower, so that it can be
1690 * processed with 32-bit real mode code if necessary
1691 */
1692 fdt_addr = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FDT_MAX_SIZE;
1693
1694 fdt = spapr_build_fdt(spapr, true, FDT_MAX_SIZE);
1695
1696 rc = fdt_pack(fdt);
1697
1698 /* Should only fail if we've built a corrupted tree */
1699 assert(rc == 0);
1700
1701 /* Load the fdt */
1702 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
1703 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
1704 g_free(spapr->fdt_blob);
1705 spapr->fdt_size = fdt_totalsize(fdt);
1706 spapr->fdt_initial_size = spapr->fdt_size;
1707 spapr->fdt_blob = fdt;
1708
1709 /* Set up the entry state */
1710 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, 0, fdt_addr, 0);
1711 first_ppc_cpu->env.gpr[5] = 0;
1712
1713 spapr->fwnmi_system_reset_addr = -1;
1714 spapr->fwnmi_machine_check_addr = -1;
1715 spapr->fwnmi_machine_check_interlock = -1;
1716
1717 /* Signal all vCPUs waiting on this condition */
1718 qemu_cond_broadcast(&spapr->fwnmi_machine_check_interlock_cond);
1719
1720 migrate_del_blocker(spapr->fwnmi_migration_blocker);
1721 }
1722
1723 static void spapr_create_nvram(SpaprMachineState *spapr)
1724 {
1725 DeviceState *dev = qdev_new("spapr-nvram");
1726 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
1727
1728 if (dinfo) {
1729 qdev_prop_set_drive_err(dev, "drive", blk_by_legacy_dinfo(dinfo),
1730 &error_fatal);
1731 }
1732
1733 qdev_realize_and_unref(dev, &spapr->vio_bus->bus, &error_fatal);
1734
1735 spapr->nvram = (struct SpaprNvram *)dev;
1736 }
1737
1738 static void spapr_rtc_create(SpaprMachineState *spapr)
1739 {
1740 object_initialize_child_with_props(OBJECT(spapr), "rtc", &spapr->rtc,
1741 sizeof(spapr->rtc), TYPE_SPAPR_RTC,
1742 &error_fatal, NULL);
1743 qdev_realize(DEVICE(&spapr->rtc), NULL, &error_fatal);
1744 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc),
1745 "date");
1746 }
1747
1748 /* Returns whether we want to use VGA or not */
1749 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp)
1750 {
1751 switch (vga_interface_type) {
1752 case VGA_NONE:
1753 return false;
1754 case VGA_DEVICE:
1755 return true;
1756 case VGA_STD:
1757 case VGA_VIRTIO:
1758 case VGA_CIRRUS:
1759 return pci_vga_init(pci_bus) != NULL;
1760 default:
1761 error_setg(errp,
1762 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1763 return false;
1764 }
1765 }
1766
1767 static int spapr_pre_load(void *opaque)
1768 {
1769 int rc;
1770
1771 rc = spapr_caps_pre_load(opaque);
1772 if (rc) {
1773 return rc;
1774 }
1775
1776 return 0;
1777 }
1778
1779 static int spapr_post_load(void *opaque, int version_id)
1780 {
1781 SpaprMachineState *spapr = (SpaprMachineState *)opaque;
1782 int err = 0;
1783
1784 err = spapr_caps_post_migration(spapr);
1785 if (err) {
1786 return err;
1787 }
1788
1789 /*
1790 * In earlier versions, there was no separate qdev for the PAPR
1791 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1792 * So when migrating from those versions, poke the incoming offset
1793 * value into the RTC device
1794 */
1795 if (version_id < 3) {
1796 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset);
1797 if (err) {
1798 return err;
1799 }
1800 }
1801
1802 if (kvm_enabled() && spapr->patb_entry) {
1803 PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
1804 bool radix = !!(spapr->patb_entry & PATE1_GR);
1805 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE);
1806
1807 /*
1808 * Update LPCR:HR and UPRT as they may not be set properly in
1809 * the stream
1810 */
1811 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0,
1812 LPCR_HR | LPCR_UPRT);
1813
1814 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry);
1815 if (err) {
1816 error_report("Process table config unsupported by the host");
1817 return -EINVAL;
1818 }
1819 }
1820
1821 err = spapr_irq_post_load(spapr, version_id);
1822 if (err) {
1823 return err;
1824 }
1825
1826 return err;
1827 }
1828
1829 static int spapr_pre_save(void *opaque)
1830 {
1831 int rc;
1832
1833 rc = spapr_caps_pre_save(opaque);
1834 if (rc) {
1835 return rc;
1836 }
1837
1838 return 0;
1839 }
1840
1841 static bool version_before_3(void *opaque, int version_id)
1842 {
1843 return version_id < 3;
1844 }
1845
1846 static bool spapr_pending_events_needed(void *opaque)
1847 {
1848 SpaprMachineState *spapr = (SpaprMachineState *)opaque;
1849 return !QTAILQ_EMPTY(&spapr->pending_events);
1850 }
1851
1852 static const VMStateDescription vmstate_spapr_event_entry = {
1853 .name = "spapr_event_log_entry",
1854 .version_id = 1,
1855 .minimum_version_id = 1,
1856 .fields = (VMStateField[]) {
1857 VMSTATE_UINT32(summary, SpaprEventLogEntry),
1858 VMSTATE_UINT32(extended_length, SpaprEventLogEntry),
1859 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0,
1860 NULL, extended_length),
1861 VMSTATE_END_OF_LIST()
1862 },
1863 };
1864
1865 static const VMStateDescription vmstate_spapr_pending_events = {
1866 .name = "spapr_pending_events",
1867 .version_id = 1,
1868 .minimum_version_id = 1,
1869 .needed = spapr_pending_events_needed,
1870 .fields = (VMStateField[]) {
1871 VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1,
1872 vmstate_spapr_event_entry, SpaprEventLogEntry, next),
1873 VMSTATE_END_OF_LIST()
1874 },
1875 };
1876
1877 static bool spapr_ov5_cas_needed(void *opaque)
1878 {
1879 SpaprMachineState *spapr = opaque;
1880 SpaprOptionVector *ov5_mask = spapr_ovec_new();
1881 bool cas_needed;
1882
1883 /* Prior to the introduction of SpaprOptionVector, we had two option
1884 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY.
1885 * Both of these options encode machine topology into the device-tree
1886 * in such a way that the now-booted OS should still be able to interact
1887 * appropriately with QEMU regardless of what options were actually
1888 * negotiatied on the source side.
1889 *
1890 * As such, we can avoid migrating the CAS-negotiated options if these
1891 * are the only options available on the current machine/platform.
1892 * Since these are the only options available for pseries-2.7 and
1893 * earlier, this allows us to maintain old->new/new->old migration
1894 * compatibility.
1895 *
1896 * For QEMU 2.8+, there are additional CAS-negotiatable options available
1897 * via default pseries-2.8 machines and explicit command-line parameters.
1898 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware
1899 * of the actual CAS-negotiated values to continue working properly. For
1900 * example, availability of memory unplug depends on knowing whether
1901 * OV5_HP_EVT was negotiated via CAS.
1902 *
1903 * Thus, for any cases where the set of available CAS-negotiatable
1904 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we
1905 * include the CAS-negotiated options in the migration stream, unless
1906 * if they affect boot time behaviour only.
1907 */
1908 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY);
1909 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY);
1910 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2);
1911
1912 /* We need extra information if we have any bits outside the mask
1913 * defined above */
1914 cas_needed = !spapr_ovec_subset(spapr->ov5, ov5_mask);
1915
1916 spapr_ovec_cleanup(ov5_mask);
1917
1918 return cas_needed;
1919 }
1920
1921 static const VMStateDescription vmstate_spapr_ov5_cas = {
1922 .name = "spapr_option_vector_ov5_cas",
1923 .version_id = 1,
1924 .minimum_version_id = 1,
1925 .needed = spapr_ov5_cas_needed,
1926 .fields = (VMStateField[]) {
1927 VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1,
1928 vmstate_spapr_ovec, SpaprOptionVector),
1929 VMSTATE_END_OF_LIST()
1930 },
1931 };
1932
1933 static bool spapr_patb_entry_needed(void *opaque)
1934 {
1935 SpaprMachineState *spapr = opaque;
1936
1937 return !!spapr->patb_entry;
1938 }
1939
1940 static const VMStateDescription vmstate_spapr_patb_entry = {
1941 .name = "spapr_patb_entry",
1942 .version_id = 1,
1943 .minimum_version_id = 1,
1944 .needed = spapr_patb_entry_needed,
1945 .fields = (VMStateField[]) {
1946 VMSTATE_UINT64(patb_entry, SpaprMachineState),
1947 VMSTATE_END_OF_LIST()
1948 },
1949 };
1950
1951 static bool spapr_irq_map_needed(void *opaque)
1952 {
1953 SpaprMachineState *spapr = opaque;
1954
1955 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr);
1956 }
1957
1958 static const VMStateDescription vmstate_spapr_irq_map = {
1959 .name = "spapr_irq_map",
1960 .version_id = 1,
1961 .minimum_version_id = 1,
1962 .needed = spapr_irq_map_needed,
1963 .fields = (VMStateField[]) {
1964 VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr),
1965 VMSTATE_END_OF_LIST()
1966 },
1967 };
1968
1969 static bool spapr_dtb_needed(void *opaque)
1970 {
1971 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque);
1972
1973 return smc->update_dt_enabled;
1974 }
1975
1976 static int spapr_dtb_pre_load(void *opaque)
1977 {
1978 SpaprMachineState *spapr = (SpaprMachineState *)opaque;
1979
1980 g_free(spapr->fdt_blob);
1981 spapr->fdt_blob = NULL;
1982 spapr->fdt_size = 0;
1983
1984 return 0;
1985 }
1986
1987 static const VMStateDescription vmstate_spapr_dtb = {
1988 .name = "spapr_dtb",
1989 .version_id = 1,
1990 .minimum_version_id = 1,
1991 .needed = spapr_dtb_needed,
1992 .pre_load = spapr_dtb_pre_load,
1993 .fields = (VMStateField[]) {
1994 VMSTATE_UINT32(fdt_initial_size, SpaprMachineState),
1995 VMSTATE_UINT32(fdt_size, SpaprMachineState),
1996 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL,
1997 fdt_size),
1998 VMSTATE_END_OF_LIST()
1999 },
2000 };
2001
2002 static bool spapr_fwnmi_needed(void *opaque)
2003 {
2004 SpaprMachineState *spapr = (SpaprMachineState *)opaque;
2005
2006 return spapr->fwnmi_machine_check_addr != -1;
2007 }
2008
2009 static int spapr_fwnmi_pre_save(void *opaque)
2010 {
2011 SpaprMachineState *spapr = (SpaprMachineState *)opaque;
2012
2013 /*
2014 * Check if machine check handling is in progress and print a
2015 * warning message.
2016 */
2017 if (spapr->fwnmi_machine_check_interlock != -1) {
2018 warn_report("A machine check is being handled during migration. The"
2019 "handler may run and log hardware error on the destination");
2020 }
2021
2022 return 0;
2023 }
2024
2025 static const VMStateDescription vmstate_spapr_fwnmi = {
2026 .name = "spapr_fwnmi",
2027 .version_id = 1,
2028 .minimum_version_id = 1,
2029 .needed = spapr_fwnmi_needed,
2030 .pre_save = spapr_fwnmi_pre_save,
2031 .fields = (VMStateField[]) {
2032 VMSTATE_UINT64(fwnmi_system_reset_addr, SpaprMachineState),
2033 VMSTATE_UINT64(fwnmi_machine_check_addr, SpaprMachineState),
2034 VMSTATE_INT32(fwnmi_machine_check_interlock, SpaprMachineState),
2035 VMSTATE_END_OF_LIST()
2036 },
2037 };
2038
2039 static const VMStateDescription vmstate_spapr = {
2040 .name = "spapr",
2041 .version_id = 3,
2042 .minimum_version_id = 1,
2043 .pre_load = spapr_pre_load,
2044 .post_load = spapr_post_load,
2045 .pre_save = spapr_pre_save,
2046 .fields = (VMStateField[]) {
2047 /* used to be @next_irq */
2048 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4),
2049
2050 /* RTC offset */
2051 VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3),
2052
2053 VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2),
2054 VMSTATE_END_OF_LIST()
2055 },
2056 .subsections = (const VMStateDescription*[]) {
2057 &vmstate_spapr_ov5_cas,
2058 &vmstate_spapr_patb_entry,
2059 &vmstate_spapr_pending_events,
2060 &vmstate_spapr_cap_htm,
2061 &vmstate_spapr_cap_vsx,
2062 &vmstate_spapr_cap_dfp,
2063 &vmstate_spapr_cap_cfpc,
2064 &vmstate_spapr_cap_sbbc,
2065 &vmstate_spapr_cap_ibs,
2066 &vmstate_spapr_cap_hpt_maxpagesize,
2067 &vmstate_spapr_irq_map,
2068 &vmstate_spapr_cap_nested_kvm_hv,
2069 &vmstate_spapr_dtb,
2070 &vmstate_spapr_cap_large_decr,
2071 &vmstate_spapr_cap_ccf_assist,
2072 &vmstate_spapr_cap_fwnmi,
2073 &vmstate_spapr_fwnmi,
2074 NULL
2075 }
2076 };
2077
2078 static int htab_save_setup(QEMUFile *f, void *opaque)
2079 {
2080 SpaprMachineState *spapr = opaque;
2081
2082 /* "Iteration" header */
2083 if (!spapr->htab_shift) {
2084 qemu_put_be32(f, -1);
2085 } else {
2086 qemu_put_be32(f, spapr->htab_shift);
2087 }
2088
2089 if (spapr->htab) {
2090 spapr->htab_save_index = 0;
2091 spapr->htab_first_pass = true;
2092 } else {
2093 if (spapr->htab_shift) {
2094 assert(kvm_enabled());
2095 }
2096 }
2097
2098
2099 return 0;
2100 }
2101
2102 static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr,
2103 int chunkstart, int n_valid, int n_invalid)
2104 {
2105 qemu_put_be32(f, chunkstart);
2106 qemu_put_be16(f, n_valid);
2107 qemu_put_be16(f, n_invalid);
2108 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
2109 HASH_PTE_SIZE_64 * n_valid);
2110 }
2111
2112 static void htab_save_end_marker(QEMUFile *f)
2113 {
2114 qemu_put_be32(f, 0);
2115 qemu_put_be16(f, 0);
2116 qemu_put_be16(f, 0);
2117 }
2118
2119 static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr,
2120 int64_t max_ns)
2121 {
2122 bool has_timeout = max_ns != -1;
2123 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
2124 int index = spapr->htab_save_index;
2125 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
2126
2127 assert(spapr->htab_first_pass);
2128
2129 do {
2130 int chunkstart;
2131
2132 /* Consume invalid HPTEs */
2133 while ((index < htabslots)
2134 && !HPTE_VALID(HPTE(spapr->htab, index))) {
2135 CLEAN_HPTE(HPTE(spapr->htab, index));
2136 index++;
2137 }
2138
2139 /* Consume valid HPTEs */
2140 chunkstart = index;
2141 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
2142 && HPTE_VALID(HPTE(spapr->htab, index))) {
2143 CLEAN_HPTE(HPTE(spapr->htab, index));
2144 index++;
2145 }
2146
2147 if (index > chunkstart) {
2148 int n_valid = index - chunkstart;
2149
2150 htab_save_chunk(f, spapr, chunkstart, n_valid, 0);
2151
2152 if (has_timeout &&
2153 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
2154 break;
2155 }
2156 }
2157 } while ((index < htabslots) && !qemu_file_rate_limit(f));
2158
2159 if (index >= htabslots) {
2160 assert(index == htabslots);
2161 index = 0;
2162 spapr->htab_first_pass = false;
2163 }
2164 spapr->htab_save_index = index;
2165 }
2166
2167 static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr,
2168 int64_t max_ns)
2169 {
2170 bool final = max_ns < 0;
2171 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
2172 int examined = 0, sent = 0;
2173 int index = spapr->htab_save_index;
2174 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
2175
2176 assert(!spapr->htab_first_pass);
2177
2178 do {
2179 int chunkstart, invalidstart;
2180
2181 /* Consume non-dirty HPTEs */
2182 while ((index < htabslots)
2183 && !HPTE_DIRTY(HPTE(spapr->htab, index))) {
2184 index++;
2185 examined++;
2186 }
2187
2188 chunkstart = index;
2189 /* Consume valid dirty HPTEs */
2190 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
2191 && HPTE_DIRTY(HPTE(spapr->htab, index))
2192 && HPTE_VALID(HPTE(spapr->htab, index))) {
2193 CLEAN_HPTE(HPTE(spapr->htab, index));
2194 index++;
2195 examined++;
2196 }
2197
2198 invalidstart = index;
2199 /* Consume invalid dirty HPTEs */
2200 while ((index < htabslots) && (index - invalidstart < USHRT_MAX)
2201 && HPTE_DIRTY(HPTE(spapr->htab, index))
2202 && !HPTE_VALID(HPTE(spapr->htab, index))) {
2203 CLEAN_HPTE(HPTE(spapr->htab, index));
2204 index++;
2205 examined++;
2206 }
2207
2208 if (index > chunkstart) {
2209 int n_valid = invalidstart - chunkstart;
2210 int n_invalid = index - invalidstart;
2211
2212 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid);
2213 sent += index - chunkstart;
2214
2215 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
2216 break;
2217 }
2218 }
2219
2220 if (examined >= htabslots) {
2221 break;
2222 }
2223
2224 if (index >= htabslots) {
2225 assert(index == htabslots);
2226 index = 0;
2227 }
2228 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final));
2229
2230 if (index >= htabslots) {
2231 assert(index == htabslots);
2232 index = 0;
2233 }
2234
2235 spapr->htab_save_index = index;
2236
2237 return (examined >= htabslots) && (sent == 0) ? 1 : 0;
2238 }
2239
2240 #define MAX_ITERATION_NS 5000000 /* 5 ms */
2241 #define MAX_KVM_BUF_SIZE 2048
2242
2243 static int htab_save_iterate(QEMUFile *f, void *opaque)
2244 {
2245 SpaprMachineState *spapr = opaque;
2246 int fd;
2247 int rc = 0;
2248
2249 /* Iteration header */
2250 if (!spapr->htab_shift) {
2251 qemu_put_be32(f, -1);
2252 return 1;
2253 } else {
2254 qemu_put_be32(f, 0);
2255 }
2256
2257 if (!spapr->htab) {
2258 assert(kvm_enabled());
2259
2260 fd = get_htab_fd(spapr);
2261 if (fd < 0) {
2262 return fd;
2263 }
2264
2265 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS);
2266 if (rc < 0) {
2267 return rc;
2268 }
2269 } else if (spapr->htab_first_pass) {
2270 htab_save_first_pass(f, spapr, MAX_ITERATION_NS);
2271 } else {
2272 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS);
2273 }
2274
2275 htab_save_end_marker(f);
2276
2277 return rc;
2278 }
2279
2280 static int htab_save_complete(QEMUFile *f, void *opaque)
2281 {
2282 SpaprMachineState *spapr = opaque;
2283 int fd;
2284
2285 /* Iteration header */
2286 if (!spapr->htab_shift) {
2287 qemu_put_be32(f, -1);
2288 return 0;
2289 } else {
2290 qemu_put_be32(f, 0);
2291 }
2292
2293 if (!spapr->htab) {
2294 int rc;
2295
2296 assert(kvm_enabled());
2297
2298 fd = get_htab_fd(spapr);
2299 if (fd < 0) {
2300 return fd;
2301 }
2302
2303 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1);
2304 if (rc < 0) {
2305 return rc;
2306 }
2307 } else {
2308 if (spapr->htab_first_pass) {
2309 htab_save_first_pass(f, spapr, -1);
2310 }
2311 htab_save_later_pass(f, spapr, -1);
2312 }
2313
2314 /* End marker */
2315 htab_save_end_marker(f);
2316
2317 return 0;
2318 }
2319
2320 static int htab_load(QEMUFile *f, void *opaque, int version_id)
2321 {
2322 SpaprMachineState *spapr = opaque;
2323 uint32_t section_hdr;
2324 int fd = -1;
2325 Error *local_err = NULL;
2326
2327 if (version_id < 1 || version_id > 1) {
2328 error_report("htab_load() bad version");
2329 return -EINVAL;
2330 }
2331
2332 section_hdr = qemu_get_be32(f);
2333
2334 if (section_hdr == -1) {
2335 spapr_free_hpt(spapr);
2336 return 0;
2337 }
2338
2339 if (section_hdr) {
2340 /* First section gives the htab size */
2341 spapr_reallocate_hpt(spapr, section_hdr, &local_err);
2342 if (local_err) {
2343 error_report_err(local_err);
2344 return -EINVAL;
2345 }
2346 return 0;
2347 }
2348
2349 if (!spapr->htab) {
2350 assert(kvm_enabled());
2351
2352 fd = kvmppc_get_htab_fd(true, 0, &local_err);
2353 if (fd < 0) {
2354 error_report_err(local_err);
2355 return fd;
2356 }
2357 }
2358
2359 while (true) {
2360 uint32_t index;
2361 uint16_t n_valid, n_invalid;
2362
2363 index = qemu_get_be32(f);
2364 n_valid = qemu_get_be16(f);
2365 n_invalid = qemu_get_be16(f);
2366
2367 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) {
2368 /* End of Stream */
2369 break;
2370 }
2371
2372 if ((index + n_valid + n_invalid) >
2373 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) {
2374 /* Bad index in stream */
2375 error_report(
2376 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
2377 index, n_valid, n_invalid, spapr->htab_shift);
2378 return -EINVAL;
2379 }
2380
2381 if (spapr->htab) {
2382 if (n_valid) {
2383 qemu_get_buffer(f, HPTE(spapr->htab, index),
2384 HASH_PTE_SIZE_64 * n_valid);
2385 }
2386 if (n_invalid) {
2387 memset(HPTE(spapr->htab, index + n_valid), 0,
2388 HASH_PTE_SIZE_64 * n_invalid);
2389 }
2390 } else {
2391 int rc;
2392
2393 assert(fd >= 0);
2394
2395 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid);
2396 if (rc < 0) {
2397 return rc;
2398 }
2399 }
2400 }
2401
2402 if (!spapr->htab) {
2403 assert(fd >= 0);
2404 close(fd);
2405 }
2406
2407 return 0;
2408 }
2409
2410 static void htab_save_cleanup(void *opaque)
2411 {
2412 SpaprMachineState *spapr = opaque;
2413
2414 close_htab_fd(spapr);
2415 }
2416
2417 static SaveVMHandlers savevm_htab_handlers = {
2418 .save_setup = htab_save_setup,
2419 .save_live_iterate = htab_save_iterate,
2420 .save_live_complete_precopy = htab_save_complete,
2421 .save_cleanup = htab_save_cleanup,
2422 .load_state = htab_load,
2423 };
2424
2425 static void spapr_boot_set(void *opaque, const char *boot_device,
2426 Error **errp)
2427 {
2428 MachineState *machine = MACHINE(opaque);
2429 machine->boot_order = g_strdup(boot_device);
2430 }
2431
2432 static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr)
2433 {
2434 MachineState *machine = MACHINE(spapr);
2435 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
2436 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size;
2437 int i;
2438
2439 for (i = 0; i < nr_lmbs; i++) {
2440 uint64_t addr;
2441
2442 addr = i * lmb_size + machine->device_memory->base;
2443 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB,
2444 addr / lmb_size);
2445 }
2446 }
2447
2448 /*
2449 * If RAM size, maxmem size and individual node mem sizes aren't aligned
2450 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
2451 * since we can't support such unaligned sizes with DRCONF_MEMORY.
2452 */
2453 static void spapr_validate_node_memory(MachineState *machine, Error **errp)
2454 {
2455 int i;
2456
2457 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) {
2458 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT
2459 " is not aligned to %" PRIu64 " MiB",
2460 machine->ram_size,
2461 SPAPR_MEMORY_BLOCK_SIZE / MiB);
2462 return;
2463 }
2464
2465 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) {
2466 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT
2467 " is not aligned to %" PRIu64 " MiB",
2468 machine->ram_size,
2469 SPAPR_MEMORY_BLOCK_SIZE / MiB);
2470 return;
2471 }
2472
2473 for (i = 0; i < machine->numa_state->num_nodes; i++) {
2474 if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) {
2475 error_setg(errp,
2476 "Node %d memory size 0x%" PRIx64
2477 " is not aligned to %" PRIu64 " MiB",
2478 i, machine->numa_state->nodes[i].node_mem,
2479 SPAPR_MEMORY_BLOCK_SIZE / MiB);
2480 return;
2481 }
2482 }
2483 }
2484
2485 /* find cpu slot in machine->possible_cpus by core_id */
2486 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
2487 {
2488 int index = id / ms->smp.threads;
2489
2490 if (index >= ms->possible_cpus->len) {
2491 return NULL;
2492 }
2493 if (idx) {
2494 *idx = index;
2495 }
2496 return &ms->possible_cpus->cpus[index];
2497 }
2498
2499 static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp)
2500 {
2501 MachineState *ms = MACHINE(spapr);
2502 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
2503 Error *local_err = NULL;
2504 bool vsmt_user = !!spapr->vsmt;
2505 int kvm_smt = kvmppc_smt_threads();
2506 int ret;
2507 unsigned int smp_threads = ms->smp.threads;
2508
2509 if (!kvm_enabled() && (smp_threads > 1)) {
2510 error_setg(errp, "TCG cannot support more than 1 thread/core "
2511 "on a pseries machine");
2512 return;
2513 }
2514 if (!is_power_of_2(smp_threads)) {
2515 error_setg(errp, "Cannot support %d threads/core on a pseries "
2516 "machine because it must be a power of 2", smp_threads);
2517 return;
2518 }
2519
2520 /* Detemine the VSMT mode to use: */
2521 if (vsmt_user) {
2522 if (spapr->vsmt < smp_threads) {
2523 error_setg(errp, "Cannot support VSMT mode %d"
2524 " because it must be >= threads/core (%d)",
2525 spapr->vsmt, smp_threads);
2526 return;
2527 }
2528 /* In this case, spapr->vsmt has been set by the command line */
2529 } else if (!smc->smp_threads_vsmt) {
2530 /*
2531 * Default VSMT value is tricky, because we need it to be as
2532 * consistent as possible (for migration), but this requires
2533 * changing it for at least some existing cases. We pick 8 as
2534 * the value that we'd get with KVM on POWER8, the
2535 * overwhelmingly common case in production systems.
2536 */
2537 spapr->vsmt = MAX(8, smp_threads);
2538 } else {
2539 spapr->vsmt = smp_threads;
2540 }
2541
2542 /* KVM: If necessary, set the SMT mode: */
2543 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) {
2544 ret = kvmppc_set_smt_threads(spapr->vsmt);
2545 if (ret) {
2546 /* Looks like KVM isn't able to change VSMT mode */
2547 error_setg(&local_err,
2548 "Failed to set KVM's VSMT mode to %d (errno %d)",
2549 spapr->vsmt, ret);
2550 /* We can live with that if the default one is big enough
2551 * for the number of threads, and a submultiple of the one
2552 * we want. In this case we'll waste some vcpu ids, but
2553 * behaviour will be correct */
2554 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) {
2555 warn_report_err(local_err);
2556 } else {
2557 if (!vsmt_user) {
2558 error_append_hint(&local_err,
2559 "On PPC, a VM with %d threads/core"
2560 " on a host with %d threads/core"
2561 " requires the use of VSMT mode %d.\n",
2562 smp_threads, kvm_smt, spapr->vsmt);
2563 }
2564 kvmppc_error_append_smt_possible_hint(&local_err);
2565 error_propagate(errp, local_err);
2566 }
2567 }
2568 }
2569 /* else TCG: nothing to do currently */
2570 }
2571
2572 static void spapr_init_cpus(SpaprMachineState *spapr)
2573 {
2574 MachineState *machine = MACHINE(spapr);
2575 MachineClass *mc = MACHINE_GET_CLASS(machine);
2576 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
2577 const char *type = spapr_get_cpu_core_type(machine->cpu_type);
2578 const CPUArchIdList *possible_cpus;
2579 unsigned int smp_cpus = machine->smp.cpus;
2580 unsigned int smp_threads = machine->smp.threads;
2581 unsigned int max_cpus = machine->smp.max_cpus;
2582 int boot_cores_nr = smp_cpus / smp_threads;
2583 int i;
2584
2585 possible_cpus = mc->possible_cpu_arch_ids(machine);
2586 if (mc->has_hotpluggable_cpus) {
2587 if (smp_cpus % smp_threads) {
2588 error_report("smp_cpus (%u) must be multiple of threads (%u)",
2589 smp_cpus, smp_threads);
2590 exit(1);
2591 }
2592 if (max_cpus % smp_threads) {
2593 error_report("max_cpus (%u) must be multiple of threads (%u)",
2594 max_cpus, smp_threads);
2595 exit(1);
2596 }
2597 } else {
2598 if (max_cpus != smp_cpus) {
2599 error_report("This machine version does not support CPU hotplug");
2600 exit(1);
2601 }
2602 boot_cores_nr = possible_cpus->len;
2603 }
2604
2605 if (smc->pre_2_10_has_unused_icps) {
2606 int i;
2607
2608 for (i = 0; i < spapr_max_server_number(spapr); i++) {
2609 /* Dummy entries get deregistered when real ICPState objects
2610 * are registered during CPU core hotplug.
2611 */
2612 pre_2_10_vmstate_register_dummy_icp(i);
2613 }
2614 }
2615
2616 for (i = 0; i < possible_cpus->len; i++) {
2617 int core_id = i * smp_threads;
2618
2619 if (mc->has_hotpluggable_cpus) {
2620 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU,
2621 spapr_vcpu_id(spapr, core_id));
2622 }
2623
2624 if (i < boot_cores_nr) {
2625 Object *core = object_new(type);
2626 int nr_threads = smp_threads;
2627
2628 /* Handle the partially filled core for older machine types */
2629 if ((i + 1) * smp_threads >= smp_cpus) {
2630 nr_threads = smp_cpus - i * smp_threads;
2631 }
2632
2633 object_property_set_int(core, "nr-threads", nr_threads,
2634 &error_fatal);
2635 object_property_set_int(core, CPU_CORE_PROP_CORE_ID, core_id,
2636 &error_fatal);
2637 qdev_realize(DEVICE(core), NULL, &error_fatal);
2638
2639 object_unref(core);
2640 }
2641 }
2642 }
2643
2644 static PCIHostState *spapr_create_default_phb(void)
2645 {
2646 DeviceState *dev;
2647
2648 dev = qdev_new(TYPE_SPAPR_PCI_HOST_BRIDGE);
2649 qdev_prop_set_uint32(dev, "index", 0);
2650 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
2651
2652 return PCI_HOST_BRIDGE(dev);
2653 }
2654
2655 static hwaddr spapr_rma_size(SpaprMachineState *spapr, Error **errp)
2656 {
2657 MachineState *machine = MACHINE(spapr);
2658 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
2659 hwaddr rma_size = machine->ram_size;
2660 hwaddr node0_size = spapr_node0_size(machine);
2661
2662 /* RMA has to fit in the first NUMA node */
2663 rma_size = MIN(rma_size, node0_size);
2664
2665 /*
2666 * VRMA access is via a special 1TiB SLB mapping, so the RMA can
2667 * never exceed that
2668 */
2669 rma_size = MIN(rma_size, 1 * TiB);
2670
2671 /*
2672 * Clamp the RMA size based on machine type. This is for
2673 * migration compatibility with older qemu versions, which limited
2674 * the RMA size for complicated and mostly bad reasons.
2675 */
2676 if (smc->rma_limit) {
2677 rma_size = MIN(rma_size, smc->rma_limit);
2678 }
2679
2680 if (rma_size < MIN_RMA_SLOF) {
2681 error_setg(errp,
2682 "pSeries SLOF firmware requires >= %" HWADDR_PRIx
2683 "ldMiB guest RMA (Real Mode Area memory)",
2684 MIN_RMA_SLOF / MiB);
2685 return 0;
2686 }
2687
2688 return rma_size;
2689 }
2690
2691 /* pSeries LPAR / sPAPR hardware init */
2692 static void spapr_machine_init(MachineState *machine)
2693 {
2694 SpaprMachineState *spapr = SPAPR_MACHINE(machine);
2695 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
2696 MachineClass *mc = MACHINE_GET_CLASS(machine);
2697 const char *kernel_filename = machine->kernel_filename;
2698 const char *initrd_filename = machine->initrd_filename;
2699 PCIHostState *phb;
2700 int i;
2701 MemoryRegion *sysmem = get_system_memory();
2702 long load_limit, fw_size;
2703 char *filename;
2704 Error *resize_hpt_err = NULL;
2705
2706 msi_nonbroken = true;
2707
2708 QLIST_INIT(&spapr->phbs);
2709 QTAILQ_INIT(&spapr->pending_dimm_unplugs);
2710
2711 /* Determine capabilities to run with */
2712 spapr_caps_init(spapr);
2713
2714 kvmppc_check_papr_resize_hpt(&resize_hpt_err);
2715 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) {
2716 /*
2717 * If the user explicitly requested a mode we should either
2718 * supply it, or fail completely (which we do below). But if
2719 * it's not set explicitly, we reset our mode to something
2720 * that works
2721 */
2722 if (resize_hpt_err) {
2723 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED;
2724 error_free(resize_hpt_err);
2725 resize_hpt_err = NULL;
2726 } else {
2727 spapr->resize_hpt = smc->resize_hpt_default;
2728 }
2729 }
2730
2731 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT);
2732
2733 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) {
2734 /*
2735 * User requested HPT resize, but this host can't supply it. Bail out
2736 */
2737 error_report_err(resize_hpt_err);
2738 exit(1);
2739 }
2740 error_free(resize_hpt_err);
2741
2742 spapr->rma_size = spapr_rma_size(spapr, &error_fatal);
2743
2744 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
2745 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD;
2746
2747 /*
2748 * VSMT must be set in order to be able to compute VCPU ids, ie to
2749 * call spapr_max_server_number() or spapr_vcpu_id().
2750 */
2751 spapr_set_vsmt_mode(spapr, &error_fatal);
2752
2753 /* Set up Interrupt Controller before we create the VCPUs */
2754 spapr_irq_init(spapr, &error_fatal);
2755
2756 /* Set up containers for ibm,client-architecture-support negotiated options
2757 */
2758 spapr->ov5 = spapr_ovec_new();
2759 spapr->ov5_cas = spapr_ovec_new();
2760
2761 if (smc->dr_lmb_enabled) {
2762 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY);
2763 spapr_validate_node_memory(machine, &error_fatal);
2764 }
2765
2766 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY);
2767
2768 /* advertise support for dedicated HP event source to guests */
2769 if (spapr->use_hotplug_event_source) {
2770 spapr_ovec_set(spapr->ov5, OV5_HP_EVT);
2771 }
2772
2773 /* advertise support for HPT resizing */
2774 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) {
2775 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE);
2776 }
2777
2778 /* advertise support for ibm,dyamic-memory-v2 */
2779 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2);
2780
2781 /* advertise XIVE on POWER9 machines */
2782 if (spapr->irq->xive) {
2783 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT);
2784 }
2785
2786 /* init CPUs */
2787 spapr_init_cpus(spapr);
2788
2789 /*
2790 * check we don't have a memory-less/cpu-less NUMA node
2791 * Firmware relies on the existing memory/cpu topology to provide the
2792 * NUMA topology to the kernel.
2793 * And the linux kernel needs to know the NUMA topology at start
2794 * to be able to hotplug CPUs later.
2795 */
2796 if (machine->numa_state->num_nodes) {
2797 for (i = 0; i < machine->numa_state->num_nodes; ++i) {
2798 /* check for memory-less node */
2799 if (machine->numa_state->nodes[i].node_mem == 0) {
2800 CPUState *cs;
2801 int found = 0;
2802 /* check for cpu-less node */
2803 CPU_FOREACH(cs) {
2804 PowerPCCPU *cpu = POWERPC_CPU(cs);
2805 if (cpu->node_id == i) {
2806 found = 1;
2807 break;
2808 }
2809 }
2810 /* memory-less and cpu-less node */
2811 if (!found) {
2812 error_report(
2813 "Memory-less/cpu-less nodes are not supported (node %d)",
2814 i);
2815 exit(1);
2816 }
2817 }
2818 }
2819
2820 }
2821
2822 /*
2823 * NVLink2-connected GPU RAM needs to be placed on a separate NUMA node.
2824 * We assign a new numa ID per GPU in spapr_pci_collect_nvgpu() which is
2825 * called from vPHB reset handler so we initialize the counter here.
2826 * If no NUMA is configured from the QEMU side, we start from 1 as GPU RAM
2827 * must be equally distant from any other node.
2828 * The final value of spapr->gpu_numa_id is going to be written to
2829 * max-associativity-domains in spapr_build_fdt().
2830 */
2831 spapr->gpu_numa_id = MAX(1, machine->numa_state->num_nodes);
2832
2833 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) &&
2834 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0,
2835 spapr->max_compat_pvr)) {
2836 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_300);
2837 /* KVM and TCG always allow GTSE with radix... */
2838 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE);
2839 }
2840 /* ... but not with hash (currently). */
2841
2842 if (kvm_enabled()) {
2843 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
2844 kvmppc_enable_logical_ci_hcalls();
2845 kvmppc_enable_set_mode_hcall();
2846
2847 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */
2848 kvmppc_enable_clear_ref_mod_hcalls();
2849
2850 /* Enable H_PAGE_INIT */
2851 kvmppc_enable_h_page_init();
2852 }
2853
2854 /* map RAM */
2855 memory_region_add_subregion(sysmem, 0, machine->ram);
2856
2857 /* always allocate the device memory information */
2858 machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
2859
2860 /* initialize hotplug memory address space */
2861 if (machine->ram_size < machine->maxram_size) {
2862 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size;
2863 /*
2864 * Limit the number of hotpluggable memory slots to half the number
2865 * slots that KVM supports, leaving the other half for PCI and other
2866 * devices. However ensure that number of slots doesn't drop below 32.
2867 */
2868 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 :
2869 SPAPR_MAX_RAM_SLOTS;
2870
2871 if (max_memslots < SPAPR_MAX_RAM_SLOTS) {
2872 max_memslots = SPAPR_MAX_RAM_SLOTS;
2873 }
2874 if (machine->ram_slots > max_memslots) {
2875 error_report("Specified number of memory slots %"
2876 PRIu64" exceeds max supported %d",
2877 machine->ram_slots, max_memslots);
2878 exit(1);
2879 }
2880
2881 machine->device_memory->base = ROUND_UP(machine->ram_size,
2882 SPAPR_DEVICE_MEM_ALIGN);
2883 memory_region_init(&machine->device_memory->mr, OBJECT(spapr),
2884 "device-memory", device_mem_size);
2885 memory_region_add_subregion(sysmem, machine->device_memory->base,
2886 &machine->device_memory->mr);
2887 }
2888
2889 if (smc->dr_lmb_enabled) {
2890 spapr_create_lmb_dr_connectors(spapr);
2891 }
2892
2893 if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI) == SPAPR_CAP_ON) {
2894 /* Create the error string for live migration blocker */
2895 error_setg(&spapr->fwnmi_migration_blocker,
2896 "A machine check is being handled during migration. The handler"
2897 "may run and log hardware error on the destination");
2898 }
2899
2900 if (mc->nvdimm_supported) {
2901 spapr_create_nvdimm_dr_connectors(spapr);
2902 }
2903
2904 /* Set up RTAS event infrastructure */
2905 spapr_events_init(spapr);
2906
2907 /* Set up the RTC RTAS interfaces */
2908 spapr_rtc_create(spapr);
2909
2910 /* Set up VIO bus */
2911 spapr->vio_bus = spapr_vio_bus_init();
2912
2913 for (i = 0; i < serial_max_hds(); i++) {
2914 if (serial_hd(i)) {
2915 spapr_vty_create(spapr->vio_bus, serial_hd(i));
2916 }
2917 }
2918
2919 /* We always have at least the nvram device on VIO */
2920 spapr_create_nvram(spapr);
2921
2922 /*
2923 * Setup hotplug / dynamic-reconfiguration connectors. top-level
2924 * connectors (described in root DT node's "ibm,drc-types" property)
2925 * are pre-initialized here. additional child connectors (such as
2926 * connectors for a PHBs PCI slots) are added as needed during their
2927 * parent's realization.
2928 */
2929 if (smc->dr_phb_enabled) {
2930 for (i = 0; i < SPAPR_MAX_PHBS; i++) {
2931 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i);
2932 }
2933 }
2934
2935 /* Set up PCI */
2936 spapr_pci_rtas_init();
2937
2938 phb = spapr_create_default_phb();
2939
2940 for (i = 0; i < nb_nics; i++) {
2941 NICInfo *nd = &nd_table[i];
2942
2943 if (!nd->model) {
2944 nd->model = g_strdup("spapr-vlan");
2945 }
2946
2947 if (g_str_equal(nd->model, "spapr-vlan") ||
2948 g_str_equal(nd->model, "ibmveth")) {
2949 spapr_vlan_create(spapr->vio_bus, nd);
2950 } else {
2951 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL);
2952 }
2953 }
2954
2955 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
2956 spapr_vscsi_create(spapr->vio_bus);
2957 }
2958
2959 /* Graphics */
2960 if (spapr_vga_init(phb->bus, &error_fatal)) {
2961 spapr->has_graphics = true;
2962 machine->usb |= defaults_enabled() && !machine->usb_disabled;
2963 }
2964
2965 if (machine->usb) {
2966 if (smc->use_ohci_by_default) {
2967 pci_create_simple(phb->bus, -1, "pci-ohci");
2968 } else {
2969 pci_create_simple(phb->bus, -1, "nec-usb-xhci");
2970 }
2971
2972 if (spapr->has_graphics) {
2973 USBBus *usb_bus = usb_bus_find(-1);
2974
2975 usb_create_simple(usb_bus, "usb-kbd");
2976 usb_create_simple(usb_bus, "usb-mouse");
2977 }
2978 }
2979
2980 if (kernel_filename) {
2981 uint64_t lowaddr = 0;
2982
2983 spapr->kernel_size = load_elf(kernel_filename, NULL,
2984 translate_kernel_address, spapr,
2985 NULL, &lowaddr, NULL, NULL, 1,
2986 PPC_ELF_MACHINE, 0, 0);
2987 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) {
2988 spapr->kernel_size = load_elf(kernel_filename, NULL,
2989 translate_kernel_address, spapr, NULL,
2990 &lowaddr, NULL, NULL, 0,
2991 PPC_ELF_MACHINE,
2992 0, 0);
2993 spapr->kernel_le = spapr->kernel_size > 0;
2994 }
2995 if (spapr->kernel_size < 0) {
2996 error_report("error loading %s: %s", kernel_filename,
2997 load_elf_strerror(spapr->kernel_size));
2998 exit(1);
2999 }
3000
3001 /* load initrd */
3002 if (initrd_filename) {
3003 /* Try to locate the initrd in the gap between the kernel
3004 * and the firmware. Add a bit of space just in case
3005 */
3006 spapr->initrd_base = (spapr->kernel_addr + spapr->kernel_size
3007 + 0x1ffff) & ~0xffff;
3008 spapr->initrd_size = load_image_targphys(initrd_filename,
3009 spapr->initrd_base,
3010 load_limit
3011 - spapr->initrd_base);
3012 if (spapr->initrd_size < 0) {
3013 error_report("could not load initial ram disk '%s'",
3014 initrd_filename);
3015 exit(1);
3016 }
3017 }
3018 }
3019
3020 if (bios_name == NULL) {
3021 bios_name = FW_FILE_NAME;
3022 }
3023 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
3024 if (!filename) {
3025 error_report("Could not find LPAR firmware '%s'", bios_name);
3026 exit(1);
3027 }
3028 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
3029 if (fw_size <= 0) {
3030 error_report("Could not load LPAR firmware '%s'", filename);
3031 exit(1);
3032 }
3033 g_free(filename);
3034
3035 /* FIXME: Should register things through the MachineState's qdev
3036 * interface, this is a legacy from the sPAPREnvironment structure
3037 * which predated MachineState but had a similar function */
3038 vmstate_register(NULL, 0, &vmstate_spapr, spapr);
3039 register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY, 1,
3040 &savevm_htab_handlers, spapr);
3041
3042 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine));
3043
3044 qemu_register_boot_set(spapr_boot_set, spapr);
3045
3046 /*
3047 * Nothing needs to be done to resume a suspended guest because
3048 * suspending does not change the machine state, so no need for
3049 * a ->wakeup method.
3050 */
3051 qemu_register_wakeup_support();
3052
3053 if (kvm_enabled()) {
3054 /* to stop and start vmclock */
3055 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change,
3056 &spapr->tb);
3057
3058 kvmppc_spapr_enable_inkernel_multitce();
3059 }
3060
3061 qemu_cond_init(&spapr->fwnmi_machine_check_interlock_cond);
3062 }
3063
3064 static int spapr_kvm_type(MachineState *machine, const char *vm_type)
3065 {
3066 if (!vm_type) {
3067 return 0;
3068 }
3069
3070 if (!strcmp(vm_type, "HV")) {
3071 return 1;
3072 }
3073
3074 if (!strcmp(vm_type, "PR")) {
3075 return 2;
3076 }
3077
3078 error_report("Unknown kvm-type specified '%s'", vm_type);
3079 exit(1);
3080 }
3081
3082 /*
3083 * Implementation of an interface to adjust firmware path
3084 * for the bootindex property handling.
3085 */
3086 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus,
3087 DeviceState *dev)
3088 {
3089 #define CAST(type, obj, name) \
3090 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
3091 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE);
3092 SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE);
3093 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON);
3094
3095 if (d) {
3096 void *spapr = CAST(void, bus->parent, "spapr-vscsi");
3097 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI);
3098 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE);
3099
3100 if (spapr) {
3101 /*
3102 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
3103 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form
3104 * 0x8000 | (target << 8) | (bus << 5) | lun
3105 * (see the "Logical unit addressing format" table in SAM5)
3106 */
3107 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun;
3108 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
3109 (uint64_t)id << 48);
3110 } else if (virtio) {
3111 /*
3112 * We use SRP luns of the form 01000000 | (target << 8) | lun
3113 * in the top 32 bits of the 64-bit LUN
3114 * Note: the quote above is from SLOF and it is wrong,
3115 * the actual binding is:
3116 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
3117 */
3118 unsigned id = 0x1000000 | (d->id << 16) | d->lun;
3119 if (d->lun >= 256) {
3120 /* Use the LUN "flat space addressing method" */
3121 id |= 0x4000;
3122 }
3123 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
3124 (uint64_t)id << 32);
3125 } else if (usb) {
3126 /*
3127 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
3128 * in the top 32 bits of the 64-bit LUN
3129 */
3130 unsigned usb_port = atoi(usb->port->path);
3131 unsigned id = 0x1000000 | (usb_port << 16) | d->lun;
3132 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
3133 (uint64_t)id << 32);
3134 }
3135 }
3136
3137 /*
3138 * SLOF probes the USB devices, and if it recognizes that the device is a
3139 * storage device, it changes its name to "storage" instead of "usb-host",
3140 * and additionally adds a child node for the SCSI LUN, so the correct
3141 * boot path in SLOF is something like .../storage@1/disk@xxx" instead.
3142 */
3143 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) {
3144 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE);
3145 if (usb_host_dev_is_scsi_storage(usbdev)) {
3146 return g_strdup_printf("storage@%s/disk", usbdev->port->path);
3147 }
3148 }
3149
3150 if (phb) {
3151 /* Replace "pci" with "pci@800000020000000" */
3152 return g_strdup_printf("pci@%"PRIX64, phb->buid);
3153 }
3154
3155 if (vsc) {
3156 /* Same logic as virtio above */
3157 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun;
3158 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32);
3159 }
3160
3161 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) {
3162 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */
3163 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE);
3164 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn));
3165 }
3166
3167 return NULL;
3168 }
3169
3170 static char *spapr_get_kvm_type(Object *obj, Error **errp)
3171 {
3172 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3173
3174 return g_strdup(spapr->kvm_type);
3175 }
3176
3177 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp)
3178 {
3179 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3180
3181 g_free(spapr->kvm_type);
3182 spapr->kvm_type = g_strdup(value);
3183 }
3184
3185 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp)
3186 {
3187 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3188
3189 return spapr->use_hotplug_event_source;
3190 }
3191
3192 static void spapr_set_modern_hotplug_events(Object *obj, bool value,
3193 Error **errp)
3194 {
3195 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3196
3197 spapr->use_hotplug_event_source = value;
3198 }
3199
3200 static bool spapr_get_msix_emulation(Object *obj, Error **errp)
3201 {
3202 return true;
3203 }
3204
3205 static char *spapr_get_resize_hpt(Object *obj, Error **errp)
3206 {
3207 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3208
3209 switch (spapr->resize_hpt) {
3210 case SPAPR_RESIZE_HPT_DEFAULT:
3211 return g_strdup("default");
3212 case SPAPR_RESIZE_HPT_DISABLED:
3213 return g_strdup("disabled");
3214 case SPAPR_RESIZE_HPT_ENABLED:
3215 return g_strdup("enabled");
3216 case SPAPR_RESIZE_HPT_REQUIRED:
3217 return g_strdup("required");
3218 }
3219 g_assert_not_reached();
3220 }
3221
3222 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp)
3223 {
3224 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3225
3226 if (strcmp(value, "default") == 0) {
3227 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT;
3228 } else if (strcmp(value, "disabled") == 0) {
3229 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED;
3230 } else if (strcmp(value, "enabled") == 0) {
3231 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED;
3232 } else if (strcmp(value, "required") == 0) {
3233 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED;
3234 } else {
3235 error_setg(errp, "Bad value for \"resize-hpt\" property");
3236 }
3237 }
3238
3239 static char *spapr_get_ic_mode(Object *obj, Error **errp)
3240 {
3241 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3242
3243 if (spapr->irq == &spapr_irq_xics_legacy) {
3244 return g_strdup("legacy");
3245 } else if (spapr->irq == &spapr_irq_xics) {
3246 return g_strdup("xics");
3247 } else if (spapr->irq == &spapr_irq_xive) {
3248 return g_strdup("xive");
3249 } else if (spapr->irq == &spapr_irq_dual) {
3250 return g_strdup("dual");
3251 }
3252 g_assert_not_reached();
3253 }
3254
3255 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp)
3256 {
3257 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3258
3259 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) {
3260 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode");
3261 return;
3262 }
3263
3264 /* The legacy IRQ backend can not be set */
3265 if (strcmp(value, "xics") == 0) {
3266 spapr->irq = &spapr_irq_xics;
3267 } else if (strcmp(value, "xive") == 0) {
3268 spapr->irq = &spapr_irq_xive;
3269 } else if (strcmp(value, "dual") == 0) {
3270 spapr->irq = &spapr_irq_dual;
3271 } else {
3272 error_setg(errp, "Bad value for \"ic-mode\" property");
3273 }
3274 }
3275
3276 static char *spapr_get_host_model(Object *obj, Error **errp)
3277 {
3278 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3279
3280 return g_strdup(spapr->host_model);
3281 }
3282
3283 static void spapr_set_host_model(Object *obj, const char *value, Error **errp)
3284 {
3285 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3286
3287 g_free(spapr->host_model);
3288 spapr->host_model = g_strdup(value);
3289 }
3290
3291 static char *spapr_get_host_serial(Object *obj, Error **errp)
3292 {
3293 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3294
3295 return g_strdup(spapr->host_serial);
3296 }
3297
3298 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp)
3299 {
3300 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3301
3302 g_free(spapr->host_serial);
3303 spapr->host_serial = g_strdup(value);
3304 }
3305
3306 static void spapr_instance_init(Object *obj)
3307 {
3308 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3309 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
3310
3311 spapr->htab_fd = -1;
3312 spapr->use_hotplug_event_source = true;
3313 object_property_add_str(obj, "kvm-type",
3314 spapr_get_kvm_type, spapr_set_kvm_type);
3315 object_property_set_description(obj, "kvm-type",
3316 "Specifies the KVM virtualization mode (HV, PR)");
3317 object_property_add_bool(obj, "modern-hotplug-events",
3318 spapr_get_modern_hotplug_events,
3319 spapr_set_modern_hotplug_events);
3320