spapr: Fix return value of vga initialization
[qemu.git] / hw / ppc / spapr.c
1 /*
2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
3 *
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 *
26 */
27 #include "sysemu/sysemu.h"
28 #include "hw/hw.h"
29 #include "elf.h"
30 #include "net/net.h"
31 #include "sysemu/blockdev.h"
32 #include "sysemu/cpus.h"
33 #include "sysemu/kvm.h"
34 #include "kvm_ppc.h"
35 #include "mmu-hash64.h"
36
37 #include "hw/boards.h"
38 #include "hw/ppc/ppc.h"
39 #include "hw/loader.h"
40
41 #include "hw/ppc/spapr.h"
42 #include "hw/ppc/spapr_vio.h"
43 #include "hw/pci-host/spapr.h"
44 #include "hw/ppc/xics.h"
45 #include "hw/pci/msi.h"
46
47 #include "hw/pci/pci.h"
48
49 #include "exec/address-spaces.h"
50 #include "hw/usb.h"
51 #include "qemu/config-file.h"
52 #include "qemu/error-report.h"
53
54 #include <libfdt.h>
55
56 /* SLOF memory layout:
57 *
58 * SLOF raw image loaded at 0, copies its romfs right below the flat
59 * device-tree, then position SLOF itself 31M below that
60 *
61 * So we set FW_OVERHEAD to 40MB which should account for all of that
62 * and more
63 *
64 * We load our kernel at 4M, leaving space for SLOF initial image
65 */
66 #define FDT_MAX_SIZE 0x40000
67 #define RTAS_MAX_SIZE 0x10000
68 #define FW_MAX_SIZE 0x400000
69 #define FW_FILE_NAME "slof.bin"
70 #define FW_OVERHEAD 0x2800000
71 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
72
73 #define MIN_RMA_SLOF 128UL
74
75 #define TIMEBASE_FREQ 512000000ULL
76
77 #define MAX_CPUS 256
78 #define XICS_IRQS 1024
79
80 #define PHANDLE_XICP 0x00001111
81
82 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift))
83
84 sPAPREnvironment *spapr;
85
86 int spapr_allocate_irq(int hint, bool lsi)
87 {
88 int irq;
89
90 if (hint) {
91 irq = hint;
92 if (hint >= spapr->next_irq) {
93 spapr->next_irq = hint + 1;
94 }
95 /* FIXME: we should probably check for collisions somehow */
96 } else {
97 irq = spapr->next_irq++;
98 }
99
100 /* Configure irq type */
101 if (!xics_get_qirq(spapr->icp, irq)) {
102 return 0;
103 }
104
105 xics_set_irq_type(spapr->icp, irq, lsi);
106
107 return irq;
108 }
109
110 /*
111 * Allocate block of consequtive IRQs, returns a number of the first.
112 * If msi==true, aligns the first IRQ number to num.
113 */
114 int spapr_allocate_irq_block(int num, bool lsi, bool msi)
115 {
116 int first = -1;
117 int i, hint = 0;
118
119 /*
120 * MSIMesage::data is used for storing VIRQ so
121 * it has to be aligned to num to support multiple
122 * MSI vectors. MSI-X is not affected by this.
123 * The hint is used for the first IRQ, the rest should
124 * be allocated continuously.
125 */
126 if (msi) {
127 assert((num == 1) || (num == 2) || (num == 4) ||
128 (num == 8) || (num == 16) || (num == 32));
129 hint = (spapr->next_irq + num - 1) & ~(num - 1);
130 }
131
132 for (i = 0; i < num; ++i) {
133 int irq;
134
135 irq = spapr_allocate_irq(hint, lsi);
136 if (!irq) {
137 return -1;
138 }
139
140 if (0 == i) {
141 first = irq;
142 hint = 0;
143 }
144
145 /* If the above doesn't create a consecutive block then that's
146 * an internal bug */
147 assert(irq == (first + i));
148 }
149
150 return first;
151 }
152
153 static XICSState *try_create_xics(const char *type, int nr_servers,
154 int nr_irqs)
155 {
156 DeviceState *dev;
157
158 dev = qdev_create(NULL, type);
159 qdev_prop_set_uint32(dev, "nr_servers", nr_servers);
160 qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs);
161 if (qdev_init(dev) < 0) {
162 return NULL;
163 }
164
165 return XICS_COMMON(dev);
166 }
167
168 static XICSState *xics_system_init(int nr_servers, int nr_irqs)
169 {
170 XICSState *icp = NULL;
171
172 if (kvm_enabled()) {
173 QemuOpts *machine_opts = qemu_get_machine_opts();
174 bool irqchip_allowed = qemu_opt_get_bool(machine_opts,
175 "kernel_irqchip", true);
176 bool irqchip_required = qemu_opt_get_bool(machine_opts,
177 "kernel_irqchip", false);
178 if (irqchip_allowed) {
179 icp = try_create_xics(TYPE_KVM_XICS, nr_servers, nr_irqs);
180 }
181
182 if (irqchip_required && !icp) {
183 perror("Failed to create in-kernel XICS\n");
184 abort();
185 }
186 }
187
188 if (!icp) {
189 icp = try_create_xics(TYPE_XICS, nr_servers, nr_irqs);
190 }
191
192 if (!icp) {
193 perror("Failed to create XICS\n");
194 abort();
195 }
196
197 return icp;
198 }
199
200 static int spapr_fixup_cpu_dt(void *fdt, sPAPREnvironment *spapr)
201 {
202 int ret = 0, offset;
203 CPUState *cpu;
204 char cpu_model[32];
205 int smt = kvmppc_smt_threads();
206 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
207
208 CPU_FOREACH(cpu) {
209 DeviceClass *dc = DEVICE_GET_CLASS(cpu);
210 int index = ppc_get_vcpu_dt_id(POWERPC_CPU(cpu));
211 uint32_t associativity[] = {cpu_to_be32(0x5),
212 cpu_to_be32(0x0),
213 cpu_to_be32(0x0),
214 cpu_to_be32(0x0),
215 cpu_to_be32(cpu->numa_node),
216 cpu_to_be32(index)};
217
218 if ((index % smt) != 0) {
219 continue;
220 }
221
222 snprintf(cpu_model, 32, "/cpus/%s@%x", dc->fw_name,
223 index);
224
225 offset = fdt_path_offset(fdt, cpu_model);
226 if (offset < 0) {
227 return offset;
228 }
229
230 if (nb_numa_nodes > 1) {
231 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity,
232 sizeof(associativity));
233 if (ret < 0) {
234 return ret;
235 }
236 }
237
238 ret = fdt_setprop(fdt, offset, "ibm,pft-size",
239 pft_size_prop, sizeof(pft_size_prop));
240 if (ret < 0) {
241 return ret;
242 }
243 }
244 return ret;
245 }
246
247
248 static size_t create_page_sizes_prop(CPUPPCState *env, uint32_t *prop,
249 size_t maxsize)
250 {
251 size_t maxcells = maxsize / sizeof(uint32_t);
252 int i, j, count;
253 uint32_t *p = prop;
254
255 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
256 struct ppc_one_seg_page_size *sps = &env->sps.sps[i];
257
258 if (!sps->page_shift) {
259 break;
260 }
261 for (count = 0; count < PPC_PAGE_SIZES_MAX_SZ; count++) {
262 if (sps->enc[count].page_shift == 0) {
263 break;
264 }
265 }
266 if ((p - prop) >= (maxcells - 3 - count * 2)) {
267 break;
268 }
269 *(p++) = cpu_to_be32(sps->page_shift);
270 *(p++) = cpu_to_be32(sps->slb_enc);
271 *(p++) = cpu_to_be32(count);
272 for (j = 0; j < count; j++) {
273 *(p++) = cpu_to_be32(sps->enc[j].page_shift);
274 *(p++) = cpu_to_be32(sps->enc[j].pte_enc);
275 }
276 }
277
278 return (p - prop) * sizeof(uint32_t);
279 }
280
281 #define _FDT(exp) \
282 do { \
283 int ret = (exp); \
284 if (ret < 0) { \
285 fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \
286 #exp, fdt_strerror(ret)); \
287 exit(1); \
288 } \
289 } while (0)
290
291
292 static void *spapr_create_fdt_skel(hwaddr initrd_base,
293 hwaddr initrd_size,
294 hwaddr kernel_size,
295 bool little_endian,
296 const char *boot_device,
297 const char *kernel_cmdline,
298 uint32_t epow_irq)
299 {
300 void *fdt;
301 CPUState *cs;
302 uint32_t start_prop = cpu_to_be32(initrd_base);
303 uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size);
304 char hypertas_prop[] = "hcall-pft\0hcall-term\0hcall-dabr\0hcall-interrupt"
305 "\0hcall-tce\0hcall-vio\0hcall-splpar\0hcall-bulk\0hcall-set-mode";
306 char qemu_hypertas_prop[] = "hcall-memop1";
307 uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)};
308 uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(smp_cpus)};
309 int i, smt = kvmppc_smt_threads();
310 unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80};
311
312 fdt = g_malloc0(FDT_MAX_SIZE);
313 _FDT((fdt_create(fdt, FDT_MAX_SIZE)));
314
315 if (kernel_size) {
316 _FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size)));
317 }
318 if (initrd_size) {
319 _FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size)));
320 }
321 _FDT((fdt_finish_reservemap(fdt)));
322
323 /* Root node */
324 _FDT((fdt_begin_node(fdt, "")));
325 _FDT((fdt_property_string(fdt, "device_type", "chrp")));
326 _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)")));
327 _FDT((fdt_property_string(fdt, "compatible", "qemu,pseries")));
328
329 _FDT((fdt_property_cell(fdt, "#address-cells", 0x2)));
330 _FDT((fdt_property_cell(fdt, "#size-cells", 0x2)));
331
332 /* /chosen */
333 _FDT((fdt_begin_node(fdt, "chosen")));
334
335 /* Set Form1_affinity */
336 _FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5))));
337
338 _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline)));
339 _FDT((fdt_property(fdt, "linux,initrd-start",
340 &start_prop, sizeof(start_prop))));
341 _FDT((fdt_property(fdt, "linux,initrd-end",
342 &end_prop, sizeof(end_prop))));
343 if (kernel_size) {
344 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR),
345 cpu_to_be64(kernel_size) };
346
347 _FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop))));
348 if (little_endian) {
349 _FDT((fdt_property(fdt, "qemu,boot-kernel-le", NULL, 0)));
350 }
351 }
352 if (boot_device) {
353 _FDT((fdt_property_string(fdt, "qemu,boot-device", boot_device)));
354 }
355 _FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width)));
356 _FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height)));
357 _FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth)));
358
359 _FDT((fdt_end_node(fdt)));
360
361 /* cpus */
362 _FDT((fdt_begin_node(fdt, "cpus")));
363
364 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1)));
365 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0)));
366
367 CPU_FOREACH(cs) {
368 PowerPCCPU *cpu = POWERPC_CPU(cs);
369 CPUPPCState *env = &cpu->env;
370 DeviceClass *dc = DEVICE_GET_CLASS(cs);
371 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
372 int index = ppc_get_vcpu_dt_id(cpu);
373 uint32_t servers_prop[smp_threads];
374 uint32_t gservers_prop[smp_threads * 2];
375 char *nodename;
376 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
377 0xffffffff, 0xffffffff};
378 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ;
379 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
380 uint32_t page_sizes_prop[64];
381 size_t page_sizes_prop_size;
382
383 if ((index % smt) != 0) {
384 continue;
385 }
386
387 nodename = g_strdup_printf("%s@%x", dc->fw_name, index);
388
389 _FDT((fdt_begin_node(fdt, nodename)));
390
391 g_free(nodename);
392
393 _FDT((fdt_property_cell(fdt, "reg", index)));
394 _FDT((fdt_property_string(fdt, "device_type", "cpu")));
395
396 _FDT((fdt_property_cell(fdt, "cpu-version", env->spr[SPR_PVR])));
397 _FDT((fdt_property_cell(fdt, "d-cache-block-size",
398 env->dcache_line_size)));
399 _FDT((fdt_property_cell(fdt, "d-cache-line-size",
400 env->dcache_line_size)));
401 _FDT((fdt_property_cell(fdt, "i-cache-block-size",
402 env->icache_line_size)));
403 _FDT((fdt_property_cell(fdt, "i-cache-line-size",
404 env->icache_line_size)));
405
406 if (pcc->l1_dcache_size) {
407 _FDT((fdt_property_cell(fdt, "d-cache-size", pcc->l1_dcache_size)));
408 } else {
409 fprintf(stderr, "Warning: Unknown L1 dcache size for cpu\n");
410 }
411 if (pcc->l1_icache_size) {
412 _FDT((fdt_property_cell(fdt, "i-cache-size", pcc->l1_icache_size)));
413 } else {
414 fprintf(stderr, "Warning: Unknown L1 icache size for cpu\n");
415 }
416
417 _FDT((fdt_property_cell(fdt, "timebase-frequency", tbfreq)));
418 _FDT((fdt_property_cell(fdt, "clock-frequency", cpufreq)));
419 _FDT((fdt_property_cell(fdt, "ibm,slb-size", env->slb_nr)));
420 _FDT((fdt_property_string(fdt, "status", "okay")));
421 _FDT((fdt_property(fdt, "64-bit", NULL, 0)));
422
423 /* Build interrupt servers and gservers properties */
424 for (i = 0; i < smp_threads; i++) {
425 servers_prop[i] = cpu_to_be32(index + i);
426 /* Hack, direct the group queues back to cpu 0 */
427 gservers_prop[i*2] = cpu_to_be32(index + i);
428 gservers_prop[i*2 + 1] = 0;
429 }
430 _FDT((fdt_property(fdt, "ibm,ppc-interrupt-server#s",
431 servers_prop, sizeof(servers_prop))));
432 _FDT((fdt_property(fdt, "ibm,ppc-interrupt-gserver#s",
433 gservers_prop, sizeof(gservers_prop))));
434
435 if (env->spr_cb[SPR_PURR].oea_read) {
436 _FDT((fdt_property(fdt, "ibm,purr", NULL, 0)));
437 }
438
439 if (env->mmu_model & POWERPC_MMU_1TSEG) {
440 _FDT((fdt_property(fdt, "ibm,processor-segment-sizes",
441 segs, sizeof(segs))));
442 }
443
444 /* Advertise VMX/VSX (vector extensions) if available
445 * 0 / no property == no vector extensions
446 * 1 == VMX / Altivec available
447 * 2 == VSX available */
448 if (env->insns_flags & PPC_ALTIVEC) {
449 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
450
451 _FDT((fdt_property_cell(fdt, "ibm,vmx", vmx)));
452 }
453
454 /* Advertise DFP (Decimal Floating Point) if available
455 * 0 / no property == no DFP
456 * 1 == DFP available */
457 if (env->insns_flags2 & PPC2_DFP) {
458 _FDT((fdt_property_cell(fdt, "ibm,dfp", 1)));
459 }
460
461 page_sizes_prop_size = create_page_sizes_prop(env, page_sizes_prop,
462 sizeof(page_sizes_prop));
463 if (page_sizes_prop_size) {
464 _FDT((fdt_property(fdt, "ibm,segment-page-sizes",
465 page_sizes_prop, page_sizes_prop_size)));
466 }
467
468 _FDT((fdt_end_node(fdt)));
469 }
470
471 _FDT((fdt_end_node(fdt)));
472
473 /* RTAS */
474 _FDT((fdt_begin_node(fdt, "rtas")));
475
476 _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas_prop,
477 sizeof(hypertas_prop))));
478 _FDT((fdt_property(fdt, "qemu,hypertas-functions", qemu_hypertas_prop,
479 sizeof(qemu_hypertas_prop))));
480
481 _FDT((fdt_property(fdt, "ibm,associativity-reference-points",
482 refpoints, sizeof(refpoints))));
483
484 _FDT((fdt_property_cell(fdt, "rtas-error-log-max", RTAS_ERROR_LOG_MAX)));
485
486 _FDT((fdt_end_node(fdt)));
487
488 /* interrupt controller */
489 _FDT((fdt_begin_node(fdt, "interrupt-controller")));
490
491 _FDT((fdt_property_string(fdt, "device_type",
492 "PowerPC-External-Interrupt-Presentation")));
493 _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp")));
494 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
495 _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges",
496 interrupt_server_ranges_prop,
497 sizeof(interrupt_server_ranges_prop))));
498 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2)));
499 _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP)));
500 _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP)));
501
502 _FDT((fdt_end_node(fdt)));
503
504 /* vdevice */
505 _FDT((fdt_begin_node(fdt, "vdevice")));
506
507 _FDT((fdt_property_string(fdt, "device_type", "vdevice")));
508 _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice")));
509 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1)));
510 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0)));
511 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2)));
512 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
513
514 _FDT((fdt_end_node(fdt)));
515
516 /* event-sources */
517 spapr_events_fdt_skel(fdt, epow_irq);
518
519 _FDT((fdt_end_node(fdt))); /* close root node */
520 _FDT((fdt_finish(fdt)));
521
522 return fdt;
523 }
524
525 static int spapr_populate_memory(sPAPREnvironment *spapr, void *fdt)
526 {
527 uint32_t associativity[] = {cpu_to_be32(0x4), cpu_to_be32(0x0),
528 cpu_to_be32(0x0), cpu_to_be32(0x0),
529 cpu_to_be32(0x0)};
530 char mem_name[32];
531 hwaddr node0_size, mem_start, node_size;
532 uint64_t mem_reg_property[2];
533 int i, off;
534
535 /* memory node(s) */
536 if (nb_numa_nodes > 1 && node_mem[0] < ram_size) {
537 node0_size = node_mem[0];
538 } else {
539 node0_size = ram_size;
540 }
541
542 /* RMA */
543 mem_reg_property[0] = 0;
544 mem_reg_property[1] = cpu_to_be64(spapr->rma_size);
545 off = fdt_add_subnode(fdt, 0, "memory@0");
546 _FDT(off);
547 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
548 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
549 sizeof(mem_reg_property))));
550 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
551 sizeof(associativity))));
552
553 /* RAM: Node 0 */
554 if (node0_size > spapr->rma_size) {
555 mem_reg_property[0] = cpu_to_be64(spapr->rma_size);
556 mem_reg_property[1] = cpu_to_be64(node0_size - spapr->rma_size);
557
558 sprintf(mem_name, "memory@" TARGET_FMT_lx, spapr->rma_size);
559 off = fdt_add_subnode(fdt, 0, mem_name);
560 _FDT(off);
561 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
562 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
563 sizeof(mem_reg_property))));
564 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
565 sizeof(associativity))));
566 }
567
568 /* RAM: Node 1 and beyond */
569 mem_start = node0_size;
570 for (i = 1; i < nb_numa_nodes; i++) {
571 mem_reg_property[0] = cpu_to_be64(mem_start);
572 if (mem_start >= ram_size) {
573 node_size = 0;
574 } else {
575 node_size = node_mem[i];
576 if (node_size > ram_size - mem_start) {
577 node_size = ram_size - mem_start;
578 }
579 }
580 mem_reg_property[1] = cpu_to_be64(node_size);
581 associativity[3] = associativity[4] = cpu_to_be32(i);
582 sprintf(mem_name, "memory@" TARGET_FMT_lx, mem_start);
583 off = fdt_add_subnode(fdt, 0, mem_name);
584 _FDT(off);
585 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
586 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
587 sizeof(mem_reg_property))));
588 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
589 sizeof(associativity))));
590 mem_start += node_size;
591 }
592
593 return 0;
594 }
595
596 static void spapr_finalize_fdt(sPAPREnvironment *spapr,
597 hwaddr fdt_addr,
598 hwaddr rtas_addr,
599 hwaddr rtas_size)
600 {
601 int ret;
602 void *fdt;
603 sPAPRPHBState *phb;
604
605 fdt = g_malloc(FDT_MAX_SIZE);
606
607 /* open out the base tree into a temp buffer for the final tweaks */
608 _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE)));
609
610 ret = spapr_populate_memory(spapr, fdt);
611 if (ret < 0) {
612 fprintf(stderr, "couldn't setup memory nodes in fdt\n");
613 exit(1);
614 }
615
616 ret = spapr_populate_vdevice(spapr->vio_bus, fdt);
617 if (ret < 0) {
618 fprintf(stderr, "couldn't setup vio devices in fdt\n");
619 exit(1);
620 }
621
622 QLIST_FOREACH(phb, &spapr->phbs, list) {
623 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt);
624 }
625
626 if (ret < 0) {
627 fprintf(stderr, "couldn't setup PCI devices in fdt\n");
628 exit(1);
629 }
630
631 /* RTAS */
632 ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size);
633 if (ret < 0) {
634 fprintf(stderr, "Couldn't set up RTAS device tree properties\n");
635 }
636
637 /* Advertise NUMA via ibm,associativity */
638 ret = spapr_fixup_cpu_dt(fdt, spapr);
639 if (ret < 0) {
640 fprintf(stderr, "Couldn't finalize CPU device tree properties\n");
641 }
642
643 if (!spapr->has_graphics) {
644 spapr_populate_chosen_stdout(fdt, spapr->vio_bus);
645 }
646
647 _FDT((fdt_pack(fdt)));
648
649 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) {
650 hw_error("FDT too big ! 0x%x bytes (max is 0x%x)\n",
651 fdt_totalsize(fdt), FDT_MAX_SIZE);
652 exit(1);
653 }
654
655 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
656
657 g_free(fdt);
658 }
659
660 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
661 {
662 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
663 }
664
665 static void emulate_spapr_hypercall(PowerPCCPU *cpu)
666 {
667 CPUPPCState *env = &cpu->env;
668
669 if (msr_pr) {
670 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
671 env->gpr[3] = H_PRIVILEGE;
672 } else {
673 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]);
674 }
675 }
676
677 static void spapr_reset_htab(sPAPREnvironment *spapr)
678 {
679 long shift;
680
681 /* allocate hash page table. For now we always make this 16mb,
682 * later we should probably make it scale to the size of guest
683 * RAM */
684
685 shift = kvmppc_reset_htab(spapr->htab_shift);
686
687 if (shift > 0) {
688 /* Kernel handles htab, we don't need to allocate one */
689 spapr->htab_shift = shift;
690 kvmppc_kern_htab = true;
691 } else {
692 if (!spapr->htab) {
693 /* Allocate an htab if we don't yet have one */
694 spapr->htab = qemu_memalign(HTAB_SIZE(spapr), HTAB_SIZE(spapr));
695 }
696
697 /* And clear it */
698 memset(spapr->htab, 0, HTAB_SIZE(spapr));
699 }
700
701 /* Update the RMA size if necessary */
702 if (spapr->vrma_adjust) {
703 hwaddr node0_size = (nb_numa_nodes > 1) ? node_mem[0] : ram_size;
704 spapr->rma_size = kvmppc_rma_size(node0_size, spapr->htab_shift);
705 }
706 }
707
708 static void ppc_spapr_reset(void)
709 {
710 PowerPCCPU *first_ppc_cpu;
711
712 /* Reset the hash table & recalc the RMA */
713 spapr_reset_htab(spapr);
714
715 qemu_devices_reset();
716
717 /* Load the fdt */
718 spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr,
719 spapr->rtas_size);
720
721 /* Set up the entry state */
722 first_ppc_cpu = POWERPC_CPU(first_cpu);
723 first_ppc_cpu->env.gpr[3] = spapr->fdt_addr;
724 first_ppc_cpu->env.gpr[5] = 0;
725 first_cpu->halted = 0;
726 first_ppc_cpu->env.nip = spapr->entry_point;
727
728 }
729
730 static void spapr_cpu_reset(void *opaque)
731 {
732 PowerPCCPU *cpu = opaque;
733 CPUState *cs = CPU(cpu);
734 CPUPPCState *env = &cpu->env;
735
736 cpu_reset(cs);
737
738 /* All CPUs start halted. CPU0 is unhalted from the machine level
739 * reset code and the rest are explicitly started up by the guest
740 * using an RTAS call */
741 cs->halted = 1;
742
743 env->spr[SPR_HIOR] = 0;
744
745 env->external_htab = (uint8_t *)spapr->htab;
746 if (kvm_enabled() && !env->external_htab) {
747 /*
748 * HV KVM, set external_htab to 1 so our ppc_hash64_load_hpte*
749 * functions do the right thing.
750 */
751 env->external_htab = (void *)1;
752 }
753 env->htab_base = -1;
754 /*
755 * htab_mask is the mask used to normalize hash value to PTEG index.
756 * htab_shift is log2 of hash table size.
757 * We have 8 hpte per group, and each hpte is 16 bytes.
758 * ie have 128 bytes per hpte entry.
759 */
760 env->htab_mask = (1ULL << ((spapr)->htab_shift - 7)) - 1;
761 env->spr[SPR_SDR1] = (target_ulong)(uintptr_t)spapr->htab |
762 (spapr->htab_shift - 18);
763 }
764
765 static void spapr_create_nvram(sPAPREnvironment *spapr)
766 {
767 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram");
768 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
769
770 if (dinfo) {
771 qdev_prop_set_drive_nofail(dev, "drive", dinfo->bdrv);
772 }
773
774 qdev_init_nofail(dev);
775
776 spapr->nvram = (struct sPAPRNVRAM *)dev;
777 }
778
779 /* Returns whether we want to use VGA or not */
780 static int spapr_vga_init(PCIBus *pci_bus)
781 {
782 switch (vga_interface_type) {
783 case VGA_NONE:
784 return false;
785 case VGA_DEVICE:
786 return true;
787 case VGA_STD:
788 return pci_vga_init(pci_bus) != NULL;
789 default:
790 fprintf(stderr, "This vga model is not supported,"
791 "currently it only supports -vga std\n");
792 exit(0);
793 }
794 }
795
796 static const VMStateDescription vmstate_spapr = {
797 .name = "spapr",
798 .version_id = 1,
799 .minimum_version_id = 1,
800 .minimum_version_id_old = 1,
801 .fields = (VMStateField []) {
802 VMSTATE_UINT32(next_irq, sPAPREnvironment),
803
804 /* RTC offset */
805 VMSTATE_UINT64(rtc_offset, sPAPREnvironment),
806
807 VMSTATE_END_OF_LIST()
808 },
809 };
810
811 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
812 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
813 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
814 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
815
816 static int htab_save_setup(QEMUFile *f, void *opaque)
817 {
818 sPAPREnvironment *spapr = opaque;
819
820 /* "Iteration" header */
821 qemu_put_be32(f, spapr->htab_shift);
822
823 if (spapr->htab) {
824 spapr->htab_save_index = 0;
825 spapr->htab_first_pass = true;
826 } else {
827 assert(kvm_enabled());
828
829 spapr->htab_fd = kvmppc_get_htab_fd(false);
830 if (spapr->htab_fd < 0) {
831 fprintf(stderr, "Unable to open fd for reading hash table from KVM: %s\n",
832 strerror(errno));
833 return -1;
834 }
835 }
836
837
838 return 0;
839 }
840
841 static void htab_save_first_pass(QEMUFile *f, sPAPREnvironment *spapr,
842 int64_t max_ns)
843 {
844 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
845 int index = spapr->htab_save_index;
846 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
847
848 assert(spapr->htab_first_pass);
849
850 do {
851 int chunkstart;
852
853 /* Consume invalid HPTEs */
854 while ((index < htabslots)
855 && !HPTE_VALID(HPTE(spapr->htab, index))) {
856 index++;
857 CLEAN_HPTE(HPTE(spapr->htab, index));
858 }
859
860 /* Consume valid HPTEs */
861 chunkstart = index;
862 while ((index < htabslots)
863 && HPTE_VALID(HPTE(spapr->htab, index))) {
864 index++;
865 CLEAN_HPTE(HPTE(spapr->htab, index));
866 }
867
868 if (index > chunkstart) {
869 int n_valid = index - chunkstart;
870
871 qemu_put_be32(f, chunkstart);
872 qemu_put_be16(f, n_valid);
873 qemu_put_be16(f, 0);
874 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
875 HASH_PTE_SIZE_64 * n_valid);
876
877 if ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
878 break;
879 }
880 }
881 } while ((index < htabslots) && !qemu_file_rate_limit(f));
882
883 if (index >= htabslots) {
884 assert(index == htabslots);
885 index = 0;
886 spapr->htab_first_pass = false;
887 }
888 spapr->htab_save_index = index;
889 }
890
891 static int htab_save_later_pass(QEMUFile *f, sPAPREnvironment *spapr,
892 int64_t max_ns)
893 {
894 bool final = max_ns < 0;
895 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
896 int examined = 0, sent = 0;
897 int index = spapr->htab_save_index;
898 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
899
900 assert(!spapr->htab_first_pass);
901
902 do {
903 int chunkstart, invalidstart;
904
905 /* Consume non-dirty HPTEs */
906 while ((index < htabslots)
907 && !HPTE_DIRTY(HPTE(spapr->htab, index))) {
908 index++;
909 examined++;
910 }
911
912 chunkstart = index;
913 /* Consume valid dirty HPTEs */
914 while ((index < htabslots)
915 && HPTE_DIRTY(HPTE(spapr->htab, index))
916 && HPTE_VALID(HPTE(spapr->htab, index))) {
917 CLEAN_HPTE(HPTE(spapr->htab, index));
918 index++;
919 examined++;
920 }
921
922 invalidstart = index;
923 /* Consume invalid dirty HPTEs */
924 while ((index < htabslots)
925 && HPTE_DIRTY(HPTE(spapr->htab, index))
926 && !HPTE_VALID(HPTE(spapr->htab, index))) {
927 CLEAN_HPTE(HPTE(spapr->htab, index));
928 index++;
929 examined++;
930 }
931
932 if (index > chunkstart) {
933 int n_valid = invalidstart - chunkstart;
934 int n_invalid = index - invalidstart;
935
936 qemu_put_be32(f, chunkstart);
937 qemu_put_be16(f, n_valid);
938 qemu_put_be16(f, n_invalid);
939 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
940 HASH_PTE_SIZE_64 * n_valid);
941 sent += index - chunkstart;
942
943 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
944 break;
945 }
946 }
947
948 if (examined >= htabslots) {
949 break;
950 }
951
952 if (index >= htabslots) {
953 assert(index == htabslots);
954 index = 0;
955 }
956 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final));
957
958 if (index >= htabslots) {
959 assert(index == htabslots);
960 index = 0;
961 }
962
963 spapr->htab_save_index = index;
964
965 return (examined >= htabslots) && (sent == 0) ? 1 : 0;
966 }
967
968 #define MAX_ITERATION_NS 5000000 /* 5 ms */
969 #define MAX_KVM_BUF_SIZE 2048
970
971 static int htab_save_iterate(QEMUFile *f, void *opaque)
972 {
973 sPAPREnvironment *spapr = opaque;
974 int rc = 0;
975
976 /* Iteration header */
977 qemu_put_be32(f, 0);
978
979 if (!spapr->htab) {
980 assert(kvm_enabled());
981
982 rc = kvmppc_save_htab(f, spapr->htab_fd,
983 MAX_KVM_BUF_SIZE, MAX_ITERATION_NS);
984 if (rc < 0) {
985 return rc;
986 }
987 } else if (spapr->htab_first_pass) {
988 htab_save_first_pass(f, spapr, MAX_ITERATION_NS);
989 } else {
990 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS);
991 }
992
993 /* End marker */
994 qemu_put_be32(f, 0);
995 qemu_put_be16(f, 0);
996 qemu_put_be16(f, 0);
997
998 return rc;
999 }
1000
1001 static int htab_save_complete(QEMUFile *f, void *opaque)
1002 {
1003 sPAPREnvironment *spapr = opaque;
1004
1005 /* Iteration header */
1006 qemu_put_be32(f, 0);
1007
1008 if (!spapr->htab) {
1009 int rc;
1010
1011 assert(kvm_enabled());
1012
1013 rc = kvmppc_save_htab(f, spapr->htab_fd, MAX_KVM_BUF_SIZE, -1);
1014 if (rc < 0) {
1015 return rc;
1016 }
1017 close(spapr->htab_fd);
1018 spapr->htab_fd = -1;
1019 } else {
1020 htab_save_later_pass(f, spapr, -1);
1021 }
1022
1023 /* End marker */
1024 qemu_put_be32(f, 0);
1025 qemu_put_be16(f, 0);
1026 qemu_put_be16(f, 0);
1027
1028 return 0;
1029 }
1030
1031 static int htab_load(QEMUFile *f, void *opaque, int version_id)
1032 {
1033 sPAPREnvironment *spapr = opaque;
1034 uint32_t section_hdr;
1035 int fd = -1;
1036
1037 if (version_id < 1 || version_id > 1) {
1038 fprintf(stderr, "htab_load() bad version\n");
1039 return -EINVAL;
1040 }
1041
1042 section_hdr = qemu_get_be32(f);
1043
1044 if (section_hdr) {
1045 /* First section, just the hash shift */
1046 if (spapr->htab_shift != section_hdr) {
1047 return -EINVAL;
1048 }
1049 return 0;
1050 }
1051
1052 if (!spapr->htab) {
1053 assert(kvm_enabled());
1054
1055 fd = kvmppc_get_htab_fd(true);
1056 if (fd < 0) {
1057 fprintf(stderr, "Unable to open fd to restore KVM hash table: %s\n",
1058 strerror(errno));
1059 }
1060 }
1061
1062 while (true) {
1063 uint32_t index;
1064 uint16_t n_valid, n_invalid;
1065
1066 index = qemu_get_be32(f);
1067 n_valid = qemu_get_be16(f);
1068 n_invalid = qemu_get_be16(f);
1069
1070 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) {
1071 /* End of Stream */
1072 break;
1073 }
1074
1075 if ((index + n_valid + n_invalid) >
1076 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) {
1077 /* Bad index in stream */
1078 fprintf(stderr, "htab_load() bad index %d (%hd+%hd entries) "
1079 "in htab stream (htab_shift=%d)\n", index, n_valid, n_invalid,
1080 spapr->htab_shift);
1081 return -EINVAL;
1082 }
1083
1084 if (spapr->htab) {
1085 if (n_valid) {
1086 qemu_get_buffer(f, HPTE(spapr->htab, index),
1087 HASH_PTE_SIZE_64 * n_valid);
1088 }
1089 if (n_invalid) {
1090 memset(HPTE(spapr->htab, index + n_valid), 0,
1091 HASH_PTE_SIZE_64 * n_invalid);
1092 }
1093 } else {
1094 int rc;
1095
1096 assert(fd >= 0);
1097
1098 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid);
1099 if (rc < 0) {
1100 return rc;
1101 }
1102 }
1103 }
1104
1105 if (!spapr->htab) {
1106 assert(fd >= 0);
1107 close(fd);
1108 }
1109
1110 return 0;
1111 }
1112
1113 static SaveVMHandlers savevm_htab_handlers = {
1114 .save_live_setup = htab_save_setup,
1115 .save_live_iterate = htab_save_iterate,
1116 .save_live_complete = htab_save_complete,
1117 .load_state = htab_load,
1118 };
1119
1120 /* pSeries LPAR / sPAPR hardware init */
1121 static void ppc_spapr_init(QEMUMachineInitArgs *args)
1122 {
1123 ram_addr_t ram_size = args->ram_size;
1124 const char *cpu_model = args->cpu_model;
1125 const char *kernel_filename = args->kernel_filename;
1126 const char *kernel_cmdline = args->kernel_cmdline;
1127 const char *initrd_filename = args->initrd_filename;
1128 const char *boot_device = args->boot_order;
1129 PowerPCCPU *cpu;
1130 CPUPPCState *env;
1131 PCIHostState *phb;
1132 int i;
1133 MemoryRegion *sysmem = get_system_memory();
1134 MemoryRegion *ram = g_new(MemoryRegion, 1);
1135 hwaddr rma_alloc_size;
1136 hwaddr node0_size = (nb_numa_nodes > 1) ? node_mem[0] : ram_size;
1137 uint32_t initrd_base = 0;
1138 long kernel_size = 0, initrd_size = 0;
1139 long load_limit, rtas_limit, fw_size;
1140 bool kernel_le = false;
1141 char *filename;
1142
1143 msi_supported = true;
1144
1145 spapr = g_malloc0(sizeof(*spapr));
1146 QLIST_INIT(&spapr->phbs);
1147
1148 cpu_ppc_hypercall = emulate_spapr_hypercall;
1149
1150 /* Allocate RMA if necessary */
1151 rma_alloc_size = kvmppc_alloc_rma("ppc_spapr.rma", sysmem);
1152
1153 if (rma_alloc_size == -1) {
1154 hw_error("qemu: Unable to create RMA\n");
1155 exit(1);
1156 }
1157
1158 if (rma_alloc_size && (rma_alloc_size < node0_size)) {
1159 spapr->rma_size = rma_alloc_size;
1160 } else {
1161 spapr->rma_size = node0_size;
1162
1163 /* With KVM, we don't actually know whether KVM supports an
1164 * unbounded RMA (PR KVM) or is limited by the hash table size
1165 * (HV KVM using VRMA), so we always assume the latter
1166 *
1167 * In that case, we also limit the initial allocations for RTAS
1168 * etc... to 256M since we have no way to know what the VRMA size
1169 * is going to be as it depends on the size of the hash table
1170 * isn't determined yet.
1171 */
1172 if (kvm_enabled()) {
1173 spapr->vrma_adjust = 1;
1174 spapr->rma_size = MIN(spapr->rma_size, 0x10000000);
1175 }
1176 }
1177
1178 if (spapr->rma_size > node0_size) {
1179 fprintf(stderr, "Error: Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")\n",
1180 spapr->rma_size);
1181 exit(1);
1182 }
1183
1184 /* We place the device tree and RTAS just below either the top of the RMA,
1185 * or just below 2GB, whichever is lowere, so that it can be
1186 * processed with 32-bit real mode code if necessary */
1187 rtas_limit = MIN(spapr->rma_size, 0x80000000);
1188 spapr->rtas_addr = rtas_limit - RTAS_MAX_SIZE;
1189 spapr->fdt_addr = spapr->rtas_addr - FDT_MAX_SIZE;
1190 load_limit = spapr->fdt_addr - FW_OVERHEAD;
1191
1192 /* We aim for a hash table of size 1/128 the size of RAM. The
1193 * normal rule of thumb is 1/64 the size of RAM, but that's much
1194 * more than needed for the Linux guests we support. */
1195 spapr->htab_shift = 18; /* Minimum architected size */
1196 while (spapr->htab_shift <= 46) {
1197 if ((1ULL << (spapr->htab_shift + 7)) >= ram_size) {
1198 break;
1199 }
1200 spapr->htab_shift++;
1201 }
1202
1203 /* Set up Interrupt Controller before we create the VCPUs */
1204 spapr->icp = xics_system_init(smp_cpus * kvmppc_smt_threads() / smp_threads,
1205 XICS_IRQS);
1206 spapr->next_irq = XICS_IRQ_BASE;
1207
1208 /* init CPUs */
1209 if (cpu_model == NULL) {
1210 cpu_model = kvm_enabled() ? "host" : "POWER7";
1211 }
1212 for (i = 0; i < smp_cpus; i++) {
1213 cpu = cpu_ppc_init(cpu_model);
1214 if (cpu == NULL) {
1215 fprintf(stderr, "Unable to find PowerPC CPU definition\n");
1216 exit(1);
1217 }
1218 env = &cpu->env;
1219
1220 /* Set time-base frequency to 512 MHz */
1221 cpu_ppc_tb_init(env, TIMEBASE_FREQ);
1222
1223 /* PAPR always has exception vectors in RAM not ROM. To ensure this,
1224 * MSR[IP] should never be set.
1225 */
1226 env->msr_mask &= ~(1 << 6);
1227
1228 /* Tell KVM that we're in PAPR mode */
1229 if (kvm_enabled()) {
1230 kvmppc_set_papr(cpu);
1231 }
1232
1233 xics_cpu_setup(spapr->icp, cpu);
1234
1235 qemu_register_reset(spapr_cpu_reset, cpu);
1236 }
1237
1238 /* allocate RAM */
1239 spapr->ram_limit = ram_size;
1240 if (spapr->ram_limit > rma_alloc_size) {
1241 ram_addr_t nonrma_base = rma_alloc_size;
1242 ram_addr_t nonrma_size = spapr->ram_limit - rma_alloc_size;
1243
1244 memory_region_init_ram(ram, NULL, "ppc_spapr.ram", nonrma_size);
1245 vmstate_register_ram_global(ram);
1246 memory_region_add_subregion(sysmem, nonrma_base, ram);
1247 }
1248
1249 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
1250 spapr->rtas_size = load_image_targphys(filename, spapr->rtas_addr,
1251 rtas_limit - spapr->rtas_addr);
1252 if (spapr->rtas_size < 0) {
1253 hw_error("qemu: could not load LPAR rtas '%s'\n", filename);
1254 exit(1);
1255 }
1256 if (spapr->rtas_size > RTAS_MAX_SIZE) {
1257 hw_error("RTAS too big ! 0x%lx bytes (max is 0x%x)\n",
1258 spapr->rtas_size, RTAS_MAX_SIZE);
1259 exit(1);
1260 }
1261 g_free(filename);
1262
1263 /* Set up EPOW events infrastructure */
1264 spapr_events_init(spapr);
1265
1266 /* Set up VIO bus */
1267 spapr->vio_bus = spapr_vio_bus_init();
1268
1269 for (i = 0; i < MAX_SERIAL_PORTS; i++) {
1270 if (serial_hds[i]) {
1271 spapr_vty_create(spapr->vio_bus, serial_hds[i]);
1272 }
1273 }
1274
1275 /* We always have at least the nvram device on VIO */
1276 spapr_create_nvram(spapr);
1277
1278 /* Set up PCI */
1279 spapr_pci_msi_init(spapr, SPAPR_PCI_MSI_WINDOW);
1280 spapr_pci_rtas_init();
1281
1282 phb = spapr_create_phb(spapr, 0);
1283
1284 for (i = 0; i < nb_nics; i++) {
1285 NICInfo *nd = &nd_table[i];
1286
1287 if (!nd->model) {
1288 nd->model = g_strdup("ibmveth");
1289 }
1290
1291 if (strcmp(nd->model, "ibmveth") == 0) {
1292 spapr_vlan_create(spapr->vio_bus, nd);
1293 } else {
1294 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL);
1295 }
1296 }
1297
1298 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
1299 spapr_vscsi_create(spapr->vio_bus);
1300 }
1301
1302 /* Graphics */
1303 if (spapr_vga_init(phb->bus)) {
1304 spapr->has_graphics = true;
1305 }
1306
1307 if (usb_enabled(spapr->has_graphics)) {
1308 pci_create_simple(phb->bus, -1, "pci-ohci");
1309 if (spapr->has_graphics) {
1310 usbdevice_create("keyboard");
1311 usbdevice_create("mouse");
1312 }
1313 }
1314
1315 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) {
1316 fprintf(stderr, "qemu: pSeries SLOF firmware requires >= "
1317 "%ldM guest RMA (Real Mode Area memory)\n", MIN_RMA_SLOF);
1318 exit(1);
1319 }
1320
1321 if (kernel_filename) {
1322 uint64_t lowaddr = 0;
1323
1324 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
1325 NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0);
1326 if (kernel_size == ELF_LOAD_WRONG_ENDIAN) {
1327 kernel_size = load_elf(kernel_filename,
1328 translate_kernel_address, NULL,
1329 NULL, &lowaddr, NULL, 0, ELF_MACHINE, 0);
1330 kernel_le = kernel_size > 0;
1331 }
1332 if (kernel_size < 0) {
1333 fprintf(stderr, "qemu: error loading %s: %s\n",
1334 kernel_filename, load_elf_strerror(kernel_size));
1335 exit(1);
1336 }
1337
1338 /* load initrd */
1339 if (initrd_filename) {
1340 /* Try to locate the initrd in the gap between the kernel
1341 * and the firmware. Add a bit of space just in case
1342 */
1343 initrd_base = (KERNEL_LOAD_ADDR + kernel_size + 0x1ffff) & ~0xffff;
1344 initrd_size = load_image_targphys(initrd_filename, initrd_base,
1345 load_limit - initrd_base);
1346 if (initrd_size < 0) {
1347 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
1348 initrd_filename);
1349 exit(1);
1350 }
1351 } else {
1352 initrd_base = 0;
1353 initrd_size = 0;
1354 }
1355 }
1356
1357 if (bios_name == NULL) {
1358 bios_name = FW_FILE_NAME;
1359 }
1360 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1361 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
1362 if (fw_size < 0) {
1363 hw_error("qemu: could not load LPAR rtas '%s'\n", filename);
1364 exit(1);
1365 }
1366 g_free(filename);
1367
1368 spapr->entry_point = 0x100;
1369
1370 vmstate_register(NULL, 0, &vmstate_spapr, spapr);
1371 register_savevm_live(NULL, "spapr/htab", -1, 1,
1372 &savevm_htab_handlers, spapr);
1373
1374 /* Prepare the device tree */
1375 spapr->fdt_skel = spapr_create_fdt_skel(initrd_base, initrd_size,
1376 kernel_size, kernel_le,
1377 boot_device, kernel_cmdline,
1378 spapr->epow_irq);
1379 assert(spapr->fdt_skel != NULL);
1380 }
1381
1382 static int spapr_kvm_type(const char *vm_type)
1383 {
1384 if (!vm_type) {
1385 return 0;
1386 }
1387
1388 if (!strcmp(vm_type, "HV")) {
1389 return 1;
1390 }
1391
1392 if (!strcmp(vm_type, "PR")) {
1393 return 2;
1394 }
1395
1396 error_report("Unknown kvm-type specified '%s'", vm_type);
1397 exit(1);
1398 }
1399
1400 static QEMUMachine spapr_machine = {
1401 .name = "pseries",
1402 .desc = "pSeries Logical Partition (PAPR compliant)",
1403 .is_default = 1,
1404 .init = ppc_spapr_init,
1405 .reset = ppc_spapr_reset,
1406 .block_default_type = IF_SCSI,
1407 .max_cpus = MAX_CPUS,
1408 .no_parallel = 1,
1409 .default_boot_order = NULL,
1410 .kvm_type = spapr_kvm_type,
1411 };
1412
1413 static void spapr_machine_init(void)
1414 {
1415 qemu_register_machine(&spapr_machine);
1416 }
1417
1418 machine_init(spapr_machine_init);