hw/arm/raspi: fix CPRMAN base address
[qemu.git] / hw / ppc / spapr.c
1 /*
2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
3 *
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 */
26
27 #include "qemu/osdep.h"
28 #include "qemu-common.h"
29 #include "qapi/error.h"
30 #include "qapi/visitor.h"
31 #include "sysemu/sysemu.h"
32 #include "sysemu/hostmem.h"
33 #include "sysemu/numa.h"
34 #include "sysemu/qtest.h"
35 #include "sysemu/reset.h"
36 #include "sysemu/runstate.h"
37 #include "qemu/log.h"
38 #include "hw/fw-path-provider.h"
39 #include "elf.h"
40 #include "net/net.h"
41 #include "sysemu/device_tree.h"
42 #include "sysemu/cpus.h"
43 #include "sysemu/hw_accel.h"
44 #include "kvm_ppc.h"
45 #include "migration/misc.h"
46 #include "migration/qemu-file-types.h"
47 #include "migration/global_state.h"
48 #include "migration/register.h"
49 #include "migration/blocker.h"
50 #include "mmu-hash64.h"
51 #include "mmu-book3s-v3.h"
52 #include "cpu-models.h"
53 #include "hw/core/cpu.h"
54
55 #include "hw/boards.h"
56 #include "hw/ppc/ppc.h"
57 #include "hw/loader.h"
58
59 #include "hw/ppc/fdt.h"
60 #include "hw/ppc/spapr.h"
61 #include "hw/ppc/spapr_vio.h"
62 #include "hw/qdev-properties.h"
63 #include "hw/pci-host/spapr.h"
64 #include "hw/pci/msi.h"
65
66 #include "hw/pci/pci.h"
67 #include "hw/scsi/scsi.h"
68 #include "hw/virtio/virtio-scsi.h"
69 #include "hw/virtio/vhost-scsi-common.h"
70
71 #include "exec/address-spaces.h"
72 #include "exec/ram_addr.h"
73 #include "hw/usb.h"
74 #include "qemu/config-file.h"
75 #include "qemu/error-report.h"
76 #include "trace.h"
77 #include "hw/nmi.h"
78 #include "hw/intc/intc.h"
79
80 #include "hw/ppc/spapr_cpu_core.h"
81 #include "hw/mem/memory-device.h"
82 #include "hw/ppc/spapr_tpm_proxy.h"
83 #include "hw/ppc/spapr_nvdimm.h"
84 #include "hw/ppc/spapr_numa.h"
85
86 #include "monitor/monitor.h"
87
88 #include <libfdt.h>
89
90 /* SLOF memory layout:
91 *
92 * SLOF raw image loaded at 0, copies its romfs right below the flat
93 * device-tree, then position SLOF itself 31M below that
94 *
95 * So we set FW_OVERHEAD to 40MB which should account for all of that
96 * and more
97 *
98 * We load our kernel at 4M, leaving space for SLOF initial image
99 */
100 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */
101 #define FW_MAX_SIZE 0x400000
102 #define FW_FILE_NAME "slof.bin"
103 #define FW_OVERHEAD 0x2800000
104 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
105
106 #define MIN_RMA_SLOF (128 * MiB)
107
108 #define PHANDLE_INTC 0x00001111
109
110 /* These two functions implement the VCPU id numbering: one to compute them
111 * all and one to identify thread 0 of a VCORE. Any change to the first one
112 * is likely to have an impact on the second one, so let's keep them close.
113 */
114 static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index)
115 {
116 MachineState *ms = MACHINE(spapr);
117 unsigned int smp_threads = ms->smp.threads;
118
119 assert(spapr->vsmt);
120 return
121 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads;
122 }
123 static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr,
124 PowerPCCPU *cpu)
125 {
126 assert(spapr->vsmt);
127 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0;
128 }
129
130 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque)
131 {
132 /* Dummy entries correspond to unused ICPState objects in older QEMUs,
133 * and newer QEMUs don't even have them. In both cases, we don't want
134 * to send anything on the wire.
135 */
136 return false;
137 }
138
139 static const VMStateDescription pre_2_10_vmstate_dummy_icp = {
140 .name = "icp/server",
141 .version_id = 1,
142 .minimum_version_id = 1,
143 .needed = pre_2_10_vmstate_dummy_icp_needed,
144 .fields = (VMStateField[]) {
145 VMSTATE_UNUSED(4), /* uint32_t xirr */
146 VMSTATE_UNUSED(1), /* uint8_t pending_priority */
147 VMSTATE_UNUSED(1), /* uint8_t mfrr */
148 VMSTATE_END_OF_LIST()
149 },
150 };
151
152 static void pre_2_10_vmstate_register_dummy_icp(int i)
153 {
154 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp,
155 (void *)(uintptr_t) i);
156 }
157
158 static void pre_2_10_vmstate_unregister_dummy_icp(int i)
159 {
160 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp,
161 (void *)(uintptr_t) i);
162 }
163
164 int spapr_max_server_number(SpaprMachineState *spapr)
165 {
166 MachineState *ms = MACHINE(spapr);
167
168 assert(spapr->vsmt);
169 return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads);
170 }
171
172 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
173 int smt_threads)
174 {
175 int i, ret = 0;
176 uint32_t servers_prop[smt_threads];
177 uint32_t gservers_prop[smt_threads * 2];
178 int index = spapr_get_vcpu_id(cpu);
179
180 if (cpu->compat_pvr) {
181 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr);
182 if (ret < 0) {
183 return ret;
184 }
185 }
186
187 /* Build interrupt servers and gservers properties */
188 for (i = 0; i < smt_threads; i++) {
189 servers_prop[i] = cpu_to_be32(index + i);
190 /* Hack, direct the group queues back to cpu 0 */
191 gservers_prop[i*2] = cpu_to_be32(index + i);
192 gservers_prop[i*2 + 1] = 0;
193 }
194 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
195 servers_prop, sizeof(servers_prop));
196 if (ret < 0) {
197 return ret;
198 }
199 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s",
200 gservers_prop, sizeof(gservers_prop));
201
202 return ret;
203 }
204
205 static void spapr_dt_pa_features(SpaprMachineState *spapr,
206 PowerPCCPU *cpu,
207 void *fdt, int offset)
208 {
209 uint8_t pa_features_206[] = { 6, 0,
210 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
211 uint8_t pa_features_207[] = { 24, 0,
212 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
213 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
214 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
215 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
216 uint8_t pa_features_300[] = { 66, 0,
217 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
218 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */
219 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */
220 /* 6: DS207 */
221 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
222 /* 16: Vector */
223 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
224 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */
225 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
226 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
227 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
228 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */
229 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
230 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */
231 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */
232 /* 42: PM, 44: PC RA, 46: SC vec'd */
233 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
234 /* 48: SIMD, 50: QP BFP, 52: String */
235 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
236 /* 54: DecFP, 56: DecI, 58: SHA */
237 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
238 /* 60: NM atomic, 62: RNG */
239 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
240 };
241 uint8_t *pa_features = NULL;
242 size_t pa_size;
243
244 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) {
245 pa_features = pa_features_206;
246 pa_size = sizeof(pa_features_206);
247 }
248 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) {
249 pa_features = pa_features_207;
250 pa_size = sizeof(pa_features_207);
251 }
252 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) {
253 pa_features = pa_features_300;
254 pa_size = sizeof(pa_features_300);
255 }
256 if (!pa_features) {
257 return;
258 }
259
260 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) {
261 /*
262 * Note: we keep CI large pages off by default because a 64K capable
263 * guest provisioned with large pages might otherwise try to map a qemu
264 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
265 * even if that qemu runs on a 4k host.
266 * We dd this bit back here if we are confident this is not an issue
267 */
268 pa_features[3] |= 0x20;
269 }
270 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) {
271 pa_features[24] |= 0x80; /* Transactional memory support */
272 }
273 if (spapr->cas_pre_isa3_guest && pa_size > 40) {
274 /* Workaround for broken kernels that attempt (guest) radix
275 * mode when they can't handle it, if they see the radix bit set
276 * in pa-features. So hide it from them. */
277 pa_features[40 + 2] &= ~0x80; /* Radix MMU */
278 }
279
280 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size)));
281 }
282
283 static hwaddr spapr_node0_size(MachineState *machine)
284 {
285 if (machine->numa_state->num_nodes) {
286 int i;
287 for (i = 0; i < machine->numa_state->num_nodes; ++i) {
288 if (machine->numa_state->nodes[i].node_mem) {
289 return MIN(pow2floor(machine->numa_state->nodes[i].node_mem),
290 machine->ram_size);
291 }
292 }
293 }
294 return machine->ram_size;
295 }
296
297 bool spapr_machine_using_legacy_numa(SpaprMachineState *spapr)
298 {
299 MachineState *machine = MACHINE(spapr);
300 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
301
302 return smc->pre_5_2_numa_associativity ||
303 machine->numa_state->num_nodes <= 1;
304 }
305
306 static void add_str(GString *s, const gchar *s1)
307 {
308 g_string_append_len(s, s1, strlen(s1) + 1);
309 }
310
311 static int spapr_dt_memory_node(SpaprMachineState *spapr, void *fdt, int nodeid,
312 hwaddr start, hwaddr size)
313 {
314 char mem_name[32];
315 uint64_t mem_reg_property[2];
316 int off;
317
318 mem_reg_property[0] = cpu_to_be64(start);
319 mem_reg_property[1] = cpu_to_be64(size);
320
321 sprintf(mem_name, "memory@%" HWADDR_PRIx, start);
322 off = fdt_add_subnode(fdt, 0, mem_name);
323 _FDT(off);
324 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
325 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
326 sizeof(mem_reg_property))));
327 spapr_numa_write_associativity_dt(spapr, fdt, off, nodeid);
328 return off;
329 }
330
331 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr)
332 {
333 MemoryDeviceInfoList *info;
334
335 for (info = list; info; info = info->next) {
336 MemoryDeviceInfo *value = info->value;
337
338 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) {
339 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data;
340
341 if (addr >= pcdimm_info->addr &&
342 addr < (pcdimm_info->addr + pcdimm_info->size)) {
343 return pcdimm_info->node;
344 }
345 }
346 }
347
348 return -1;
349 }
350
351 struct sPAPRDrconfCellV2 {
352 uint32_t seq_lmbs;
353 uint64_t base_addr;
354 uint32_t drc_index;
355 uint32_t aa_index;
356 uint32_t flags;
357 } QEMU_PACKED;
358
359 typedef struct DrconfCellQueue {
360 struct sPAPRDrconfCellV2 cell;
361 QSIMPLEQ_ENTRY(DrconfCellQueue) entry;
362 } DrconfCellQueue;
363
364 static DrconfCellQueue *
365 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr,
366 uint32_t drc_index, uint32_t aa_index,
367 uint32_t flags)
368 {
369 DrconfCellQueue *elem;
370
371 elem = g_malloc0(sizeof(*elem));
372 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs);
373 elem->cell.base_addr = cpu_to_be64(base_addr);
374 elem->cell.drc_index = cpu_to_be32(drc_index);
375 elem->cell.aa_index = cpu_to_be32(aa_index);
376 elem->cell.flags = cpu_to_be32(flags);
377
378 return elem;
379 }
380
381 static int spapr_dt_dynamic_memory_v2(SpaprMachineState *spapr, void *fdt,
382 int offset, MemoryDeviceInfoList *dimms)
383 {
384 MachineState *machine = MACHINE(spapr);
385 uint8_t *int_buf, *cur_index;
386 int ret;
387 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
388 uint64_t addr, cur_addr, size;
389 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size);
390 uint64_t mem_end = machine->device_memory->base +
391 memory_region_size(&machine->device_memory->mr);
392 uint32_t node, buf_len, nr_entries = 0;
393 SpaprDrc *drc;
394 DrconfCellQueue *elem, *next;
395 MemoryDeviceInfoList *info;
396 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue
397 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue);
398
399 /* Entry to cover RAM and the gap area */
400 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1,
401 SPAPR_LMB_FLAGS_RESERVED |
402 SPAPR_LMB_FLAGS_DRC_INVALID);
403 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
404 nr_entries++;
405
406 cur_addr = machine->device_memory->base;
407 for (info = dimms; info; info = info->next) {
408 PCDIMMDeviceInfo *di = info->value->u.dimm.data;
409
410 addr = di->addr;
411 size = di->size;
412 node = di->node;
413
414 /*
415 * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The
416 * area is marked hotpluggable in the next iteration for the bigger
417 * chunk including the NVDIMM occupied area.
418 */
419 if (info->value->type == MEMORY_DEVICE_INFO_KIND_NVDIMM)
420 continue;
421
422 /* Entry for hot-pluggable area */
423 if (cur_addr < addr) {
424 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size);
425 g_assert(drc);
426 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size,
427 cur_addr, spapr_drc_index(drc), -1, 0);
428 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
429 nr_entries++;
430 }
431
432 /* Entry for DIMM */
433 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size);
434 g_assert(drc);
435 elem = spapr_get_drconf_cell(size / lmb_size, addr,
436 spapr_drc_index(drc), node,
437 (SPAPR_LMB_FLAGS_ASSIGNED |
438 SPAPR_LMB_FLAGS_HOTREMOVABLE));
439 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
440 nr_entries++;
441 cur_addr = addr + size;
442 }
443
444 /* Entry for remaining hotpluggable area */
445 if (cur_addr < mem_end) {
446 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size);
447 g_assert(drc);
448 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size,
449 cur_addr, spapr_drc_index(drc), -1, 0);
450 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
451 nr_entries++;
452 }
453
454 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t);
455 int_buf = cur_index = g_malloc0(buf_len);
456 *(uint32_t *)int_buf = cpu_to_be32(nr_entries);
457 cur_index += sizeof(nr_entries);
458
459 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) {
460 memcpy(cur_index, &elem->cell, sizeof(elem->cell));
461 cur_index += sizeof(elem->cell);
462 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry);
463 g_free(elem);
464 }
465
466 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len);
467 g_free(int_buf);
468 if (ret < 0) {
469 return -1;
470 }
471 return 0;
472 }
473
474 static int spapr_dt_dynamic_memory(SpaprMachineState *spapr, void *fdt,
475 int offset, MemoryDeviceInfoList *dimms)
476 {
477 MachineState *machine = MACHINE(spapr);
478 int i, ret;
479 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
480 uint32_t device_lmb_start = machine->device_memory->base / lmb_size;
481 uint32_t nr_lmbs = (machine->device_memory->base +
482 memory_region_size(&machine->device_memory->mr)) /
483 lmb_size;
484 uint32_t *int_buf, *cur_index, buf_len;
485
486 /*
487 * Allocate enough buffer size to fit in ibm,dynamic-memory
488 */
489 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t);
490 cur_index = int_buf = g_malloc0(buf_len);
491 int_buf[0] = cpu_to_be32(nr_lmbs);
492 cur_index++;
493 for (i = 0; i < nr_lmbs; i++) {
494 uint64_t addr = i * lmb_size;
495 uint32_t *dynamic_memory = cur_index;
496
497 if (i >= device_lmb_start) {
498 SpaprDrc *drc;
499
500 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i);
501 g_assert(drc);
502
503 dynamic_memory[0] = cpu_to_be32(addr >> 32);
504 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
505 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc));
506 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
507 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr));
508 if (memory_region_present(get_system_memory(), addr)) {
509 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED);
510 } else {
511 dynamic_memory[5] = cpu_to_be32(0);
512 }
513 } else {
514 /*
515 * LMB information for RMA, boot time RAM and gap b/n RAM and
516 * device memory region -- all these are marked as reserved
517 * and as having no valid DRC.
518 */
519 dynamic_memory[0] = cpu_to_be32(addr >> 32);
520 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
521 dynamic_memory[2] = cpu_to_be32(0);
522 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
523 dynamic_memory[4] = cpu_to_be32(-1);
524 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED |
525 SPAPR_LMB_FLAGS_DRC_INVALID);
526 }
527
528 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE;
529 }
530 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len);
531 g_free(int_buf);
532 if (ret < 0) {
533 return -1;
534 }
535 return 0;
536 }
537
538 /*
539 * Adds ibm,dynamic-reconfiguration-memory node.
540 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
541 * of this device tree node.
542 */
543 static int spapr_dt_dynamic_reconfiguration_memory(SpaprMachineState *spapr,
544 void *fdt)
545 {
546 MachineState *machine = MACHINE(spapr);
547 int ret, offset;
548 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
549 uint32_t prop_lmb_size[] = {cpu_to_be32(lmb_size >> 32),
550 cpu_to_be32(lmb_size & 0xffffffff)};
551 MemoryDeviceInfoList *dimms = NULL;
552
553 /*
554 * Don't create the node if there is no device memory
555 */
556 if (machine->ram_size == machine->maxram_size) {
557 return 0;
558 }
559
560 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory");
561
562 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size,
563 sizeof(prop_lmb_size));
564 if (ret < 0) {
565 return ret;
566 }
567
568 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff);
569 if (ret < 0) {
570 return ret;
571 }
572
573 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0);
574 if (ret < 0) {
575 return ret;
576 }
577
578 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */
579 dimms = qmp_memory_device_list();
580 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) {
581 ret = spapr_dt_dynamic_memory_v2(spapr, fdt, offset, dimms);
582 } else {
583 ret = spapr_dt_dynamic_memory(spapr, fdt, offset, dimms);
584 }
585 qapi_free_MemoryDeviceInfoList(dimms);
586
587 if (ret < 0) {
588 return ret;
589 }
590
591 ret = spapr_numa_write_assoc_lookup_arrays(spapr, fdt, offset);
592
593 return ret;
594 }
595
596 static int spapr_dt_memory(SpaprMachineState *spapr, void *fdt)
597 {
598 MachineState *machine = MACHINE(spapr);
599 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
600 hwaddr mem_start, node_size;
601 int i, nb_nodes = machine->numa_state->num_nodes;
602 NodeInfo *nodes = machine->numa_state->nodes;
603
604 for (i = 0, mem_start = 0; i < nb_nodes; ++i) {
605 if (!nodes[i].node_mem) {
606 continue;
607 }
608 if (mem_start >= machine->ram_size) {
609 node_size = 0;
610 } else {
611 node_size = nodes[i].node_mem;
612 if (node_size > machine->ram_size - mem_start) {
613 node_size = machine->ram_size - mem_start;
614 }
615 }
616 if (!mem_start) {
617 /* spapr_machine_init() checks for rma_size <= node0_size
618 * already */
619 spapr_dt_memory_node(spapr, fdt, i, 0, spapr->rma_size);
620 mem_start += spapr->rma_size;
621 node_size -= spapr->rma_size;
622 }
623 for ( ; node_size; ) {
624 hwaddr sizetmp = pow2floor(node_size);
625
626 /* mem_start != 0 here */
627 if (ctzl(mem_start) < ctzl(sizetmp)) {
628 sizetmp = 1ULL << ctzl(mem_start);
629 }
630
631 spapr_dt_memory_node(spapr, fdt, i, mem_start, sizetmp);
632 node_size -= sizetmp;
633 mem_start += sizetmp;
634 }
635 }
636
637 /* Generate ibm,dynamic-reconfiguration-memory node if required */
638 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRCONF_MEMORY)) {
639 int ret;
640
641 g_assert(smc->dr_lmb_enabled);
642 ret = spapr_dt_dynamic_reconfiguration_memory(spapr, fdt);
643 if (ret) {
644 return ret;
645 }
646 }
647
648 return 0;
649 }
650
651 static void spapr_dt_cpu(CPUState *cs, void *fdt, int offset,
652 SpaprMachineState *spapr)
653 {
654 MachineState *ms = MACHINE(spapr);
655 PowerPCCPU *cpu = POWERPC_CPU(cs);
656 CPUPPCState *env = &cpu->env;
657 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
658 int index = spapr_get_vcpu_id(cpu);
659 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
660 0xffffffff, 0xffffffff};
661 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq()
662 : SPAPR_TIMEBASE_FREQ;
663 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
664 uint32_t page_sizes_prop[64];
665 size_t page_sizes_prop_size;
666 unsigned int smp_threads = ms->smp.threads;
667 uint32_t vcpus_per_socket = smp_threads * ms->smp.cores;
668 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
669 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu));
670 SpaprDrc *drc;
671 int drc_index;
672 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ];
673 int i;
674
675 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index);
676 if (drc) {
677 drc_index = spapr_drc_index(drc);
678 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)));
679 }
680
681 _FDT((fdt_setprop_cell(fdt, offset, "reg", index)));
682 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
683
684 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
685 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
686 env->dcache_line_size)));
687 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
688 env->dcache_line_size)));
689 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
690 env->icache_line_size)));
691 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
692 env->icache_line_size)));
693
694 if (pcc->l1_dcache_size) {
695 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
696 pcc->l1_dcache_size)));
697 } else {
698 warn_report("Unknown L1 dcache size for cpu");
699 }
700 if (pcc->l1_icache_size) {
701 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
702 pcc->l1_icache_size)));
703 } else {
704 warn_report("Unknown L1 icache size for cpu");
705 }
706
707 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
708 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
709 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size)));
710 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size)));
711 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
712 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
713
714 if (env->spr_cb[SPR_PURR].oea_read) {
715 _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1)));
716 }
717 if (env->spr_cb[SPR_SPURR].oea_read) {
718 _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1)));
719 }
720
721 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) {
722 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
723 segs, sizeof(segs))));
724 }
725
726 /* Advertise VSX (vector extensions) if available
727 * 1 == VMX / Altivec available
728 * 2 == VSX available
729 *
730 * Only CPUs for which we create core types in spapr_cpu_core.c
731 * are possible, and all of those have VMX */
732 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) {
733 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2)));
734 } else {
735 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1)));
736 }
737
738 /* Advertise DFP (Decimal Floating Point) if available
739 * 0 / no property == no DFP
740 * 1 == DFP available */
741 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) {
742 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
743 }
744
745 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop,
746 sizeof(page_sizes_prop));
747 if (page_sizes_prop_size) {
748 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
749 page_sizes_prop, page_sizes_prop_size)));
750 }
751
752 spapr_dt_pa_features(spapr, cpu, fdt, offset);
753
754 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
755 cs->cpu_index / vcpus_per_socket)));
756
757 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size",
758 pft_size_prop, sizeof(pft_size_prop))));
759
760 if (ms->numa_state->num_nodes > 1) {
761 _FDT(spapr_numa_fixup_cpu_dt(spapr, fdt, offset, cpu));
762 }
763
764 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt));
765
766 if (pcc->radix_page_info) {
767 for (i = 0; i < pcc->radix_page_info->count; i++) {
768 radix_AP_encodings[i] =
769 cpu_to_be32(pcc->radix_page_info->entries[i]);
770 }
771 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings",
772 radix_AP_encodings,
773 pcc->radix_page_info->count *
774 sizeof(radix_AP_encodings[0]))));
775 }
776
777 /*
778 * We set this property to let the guest know that it can use the large
779 * decrementer and its width in bits.
780 */
781 if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF)
782 _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits",
783 pcc->lrg_decr_bits)));
784 }
785
786 static void spapr_dt_cpus(void *fdt, SpaprMachineState *spapr)
787 {
788 CPUState **rev;
789 CPUState *cs;
790 int n_cpus;
791 int cpus_offset;
792 char *nodename;
793 int i;
794
795 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
796 _FDT(cpus_offset);
797 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
798 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
799
800 /*
801 * We walk the CPUs in reverse order to ensure that CPU DT nodes
802 * created by fdt_add_subnode() end up in the right order in FDT
803 * for the guest kernel the enumerate the CPUs correctly.
804 *
805 * The CPU list cannot be traversed in reverse order, so we need
806 * to do extra work.
807 */
808 n_cpus = 0;
809 rev = NULL;
810 CPU_FOREACH(cs) {
811 rev = g_renew(CPUState *, rev, n_cpus + 1);
812 rev[n_cpus++] = cs;
813 }
814
815 for (i = n_cpus - 1; i >= 0; i--) {
816 CPUState *cs = rev[i];
817 PowerPCCPU *cpu = POWERPC_CPU(cs);
818 int index = spapr_get_vcpu_id(cpu);
819 DeviceClass *dc = DEVICE_GET_CLASS(cs);
820 int offset;
821
822 if (!spapr_is_thread0_in_vcore(spapr, cpu)) {
823 continue;
824 }
825
826 nodename = g_strdup_printf("%s@%x", dc->fw_name, index);
827 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
828 g_free(nodename);
829 _FDT(offset);
830 spapr_dt_cpu(cs, fdt, offset, spapr);
831 }
832
833 g_free(rev);
834 }
835
836 static int spapr_dt_rng(void *fdt)
837 {
838 int node;
839 int ret;
840
841 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities");
842 if (node <= 0) {
843 return -1;
844 }
845 ret = fdt_setprop_string(fdt, node, "device_type",
846 "ibm,platform-facilities");
847 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1);
848 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0);
849
850 node = fdt_add_subnode(fdt, node, "ibm,random-v1");
851 if (node <= 0) {
852 return -1;
853 }
854 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random");
855
856 return ret ? -1 : 0;
857 }
858
859 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt)
860 {
861 MachineState *ms = MACHINE(spapr);
862 int rtas;
863 GString *hypertas = g_string_sized_new(256);
864 GString *qemu_hypertas = g_string_sized_new(256);
865 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base +
866 memory_region_size(&MACHINE(spapr)->device_memory->mr);
867 uint32_t lrdr_capacity[] = {
868 cpu_to_be32(max_device_addr >> 32),
869 cpu_to_be32(max_device_addr & 0xffffffff),
870 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE >> 32),
871 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE & 0xffffffff),
872 cpu_to_be32(ms->smp.max_cpus / ms->smp.threads),
873 };
874
875 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas"));
876
877 /* hypertas */
878 add_str(hypertas, "hcall-pft");
879 add_str(hypertas, "hcall-term");
880 add_str(hypertas, "hcall-dabr");
881 add_str(hypertas, "hcall-interrupt");
882 add_str(hypertas, "hcall-tce");
883 add_str(hypertas, "hcall-vio");
884 add_str(hypertas, "hcall-splpar");
885 add_str(hypertas, "hcall-join");
886 add_str(hypertas, "hcall-bulk");
887 add_str(hypertas, "hcall-set-mode");
888 add_str(hypertas, "hcall-sprg0");
889 add_str(hypertas, "hcall-copy");
890 add_str(hypertas, "hcall-debug");
891 add_str(hypertas, "hcall-vphn");
892 add_str(qemu_hypertas, "hcall-memop1");
893
894 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
895 add_str(hypertas, "hcall-multi-tce");
896 }
897
898 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) {
899 add_str(hypertas, "hcall-hpt-resize");
900 }
901
902 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions",
903 hypertas->str, hypertas->len));
904 g_string_free(hypertas, TRUE);
905 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions",
906 qemu_hypertas->str, qemu_hypertas->len));
907 g_string_free(qemu_hypertas, TRUE);
908
909 spapr_numa_write_rtas_dt(spapr, fdt, rtas);
910
911 /*
912 * FWNMI reserves RTAS_ERROR_LOG_MAX for the machine check error log,
913 * and 16 bytes per CPU for system reset error log plus an extra 8 bytes.
914 *
915 * The system reset requirements are driven by existing Linux and PowerVM
916 * implementation which (contrary to PAPR) saves r3 in the error log
917 * structure like machine check, so Linux expects to find the saved r3
918 * value at the address in r3 upon FWNMI-enabled sreset interrupt (and
919 * does not look at the error value).
920 *
921 * System reset interrupts are not subject to interlock like machine
922 * check, so this memory area could be corrupted if the sreset is
923 * interrupted by a machine check (or vice versa) if it was shared. To
924 * prevent this, system reset uses per-CPU areas for the sreset save
925 * area. A system reset that interrupts a system reset handler could
926 * still overwrite this area, but Linux doesn't try to recover in that
927 * case anyway.
928 *
929 * The extra 8 bytes is required because Linux's FWNMI error log check
930 * is off-by-one.
931 */
932 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-size", RTAS_ERROR_LOG_MAX +
933 ms->smp.max_cpus * sizeof(uint64_t)*2 + sizeof(uint64_t)));
934 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max",
935 RTAS_ERROR_LOG_MAX));
936 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate",
937 RTAS_EVENT_SCAN_RATE));
938
939 g_assert(msi_nonbroken);
940 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0));
941
942 /*
943 * According to PAPR, rtas ibm,os-term does not guarantee a return
944 * back to the guest cpu.
945 *
946 * While an additional ibm,extended-os-term property indicates
947 * that rtas call return will always occur. Set this property.
948 */
949 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0));
950
951 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity",
952 lrdr_capacity, sizeof(lrdr_capacity)));
953
954 spapr_dt_rtas_tokens(fdt, rtas);
955 }
956
957 /*
958 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU
959 * and the XIVE features that the guest may request and thus the valid
960 * values for bytes 23..26 of option vector 5:
961 */
962 static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt,
963 int chosen)
964 {
965 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu);
966
967 char val[2 * 4] = {
968 23, 0x00, /* XICS / XIVE mode */
969 24, 0x00, /* Hash/Radix, filled in below. */
970 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */
971 26, 0x40, /* Radix options: GTSE == yes. */
972 };
973
974 if (spapr->irq->xics && spapr->irq->xive) {
975 val[1] = SPAPR_OV5_XIVE_BOTH;
976 } else if (spapr->irq->xive) {
977 val[1] = SPAPR_OV5_XIVE_EXPLOIT;
978 } else {
979 assert(spapr->irq->xics);
980 val[1] = SPAPR_OV5_XIVE_LEGACY;
981 }
982
983 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0,
984 first_ppc_cpu->compat_pvr)) {
985 /*
986 * If we're in a pre POWER9 compat mode then the guest should
987 * do hash and use the legacy interrupt mode
988 */
989 val[1] = SPAPR_OV5_XIVE_LEGACY; /* XICS */
990 val[3] = 0x00; /* Hash */
991 } else if (kvm_enabled()) {
992 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) {
993 val[3] = 0x80; /* OV5_MMU_BOTH */
994 } else if (kvmppc_has_cap_mmu_radix()) {
995 val[3] = 0x40; /* OV5_MMU_RADIX_300 */
996 } else {
997 val[3] = 0x00; /* Hash */
998 }
999 } else {
1000 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */
1001 val[3] = 0xC0;
1002 }
1003 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support",
1004 val, sizeof(val)));
1005 }
1006
1007 static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt, bool reset)
1008 {
1009 MachineState *machine = MACHINE(spapr);
1010 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
1011 int chosen;
1012
1013 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen"));
1014
1015 if (reset) {
1016 const char *boot_device = machine->boot_order;
1017 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus);
1018 size_t cb = 0;
1019 char *bootlist = get_boot_devices_list(&cb);
1020
1021 if (machine->kernel_cmdline && machine->kernel_cmdline[0]) {
1022 _FDT(fdt_setprop_string(fdt, chosen, "bootargs",
1023 machine->kernel_cmdline));
1024 }
1025
1026 if (spapr->initrd_size) {
1027 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start",
1028 spapr->initrd_base));
1029 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end",
1030 spapr->initrd_base + spapr->initrd_size));
1031 }
1032
1033 if (spapr->kernel_size) {
1034 uint64_t kprop[2] = { cpu_to_be64(spapr->kernel_addr),
1035 cpu_to_be64(spapr->kernel_size) };
1036
1037 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel",
1038 &kprop, sizeof(kprop)));
1039 if (spapr->kernel_le) {
1040 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0));
1041 }
1042 }
1043 if (boot_menu) {
1044 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu)));
1045 }
1046 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width));
1047 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height));
1048 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth));
1049
1050 if (cb && bootlist) {
1051 int i;
1052
1053 for (i = 0; i < cb; i++) {
1054 if (bootlist[i] == '\n') {
1055 bootlist[i] = ' ';
1056 }
1057 }
1058 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist));
1059 }
1060
1061 if (boot_device && strlen(boot_device)) {
1062 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device));
1063 }
1064
1065 if (!spapr->has_graphics && stdout_path) {
1066 /*
1067 * "linux,stdout-path" and "stdout" properties are
1068 * deprecated by linux kernel. New platforms should only
1069 * use the "stdout-path" property. Set the new property
1070 * and continue using older property to remain compatible
1071 * with the existing firmware.
1072 */
1073 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path));
1074 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path));
1075 }
1076
1077 /*
1078 * We can deal with BAR reallocation just fine, advertise it
1079 * to the guest
1080 */
1081 if (smc->linux_pci_probe) {
1082 _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0));
1083 }
1084
1085 spapr_dt_ov5_platform_support(spapr, fdt, chosen);
1086
1087 g_free(stdout_path);
1088 g_free(bootlist);
1089 }
1090
1091 _FDT(spapr_dt_ovec(fdt, chosen, spapr->ov5_cas, "ibm,architecture-vec-5"));
1092 }
1093
1094 static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt)
1095 {
1096 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR
1097 * KVM to work under pHyp with some guest co-operation */
1098 int hypervisor;
1099 uint8_t hypercall[16];
1100
1101 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor"));
1102 /* indicate KVM hypercall interface */
1103 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm"));
1104 if (kvmppc_has_cap_fixup_hcalls()) {
1105 /*
1106 * Older KVM versions with older guest kernels were broken
1107 * with the magic page, don't allow the guest to map it.
1108 */
1109 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall,
1110 sizeof(hypercall))) {
1111 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions",
1112 hypercall, sizeof(hypercall)));
1113 }
1114 }
1115 }
1116
1117 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space)
1118 {
1119 MachineState *machine = MACHINE(spapr);
1120 MachineClass *mc = MACHINE_GET_CLASS(machine);
1121 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
1122 int ret;
1123 void *fdt;
1124 SpaprPhbState *phb;
1125 char *buf;
1126
1127 fdt = g_malloc0(space);
1128 _FDT((fdt_create_empty_tree(fdt, space)));
1129
1130 /* Root node */
1131 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp"));
1132 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)"));
1133 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries"));
1134
1135 /* Guest UUID & Name*/
1136 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
1137 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf));
1138 if (qemu_uuid_set) {
1139 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf));
1140 }
1141 g_free(buf);
1142
1143 if (qemu_get_vm_name()) {
1144 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name",
1145 qemu_get_vm_name()));
1146 }
1147
1148 /* Host Model & Serial Number */
1149 if (spapr->host_model) {
1150 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model));
1151 } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) {
1152 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf));
1153 g_free(buf);
1154 }
1155
1156 if (spapr->host_serial) {
1157 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial));
1158 } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) {
1159 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf));
1160 g_free(buf);
1161 }
1162
1163 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2));
1164 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2));
1165
1166 /* /interrupt controller */
1167 spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC);
1168
1169 ret = spapr_dt_memory(spapr, fdt);
1170 if (ret < 0) {
1171 error_report("couldn't setup memory nodes in fdt");
1172 exit(1);
1173 }
1174
1175 /* /vdevice */
1176 spapr_dt_vdevice(spapr->vio_bus, fdt);
1177
1178 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) {
1179 ret = spapr_dt_rng(fdt);
1180 if (ret < 0) {
1181 error_report("could not set up rng device in the fdt");
1182 exit(1);
1183 }
1184 }
1185
1186 QLIST_FOREACH(phb, &spapr->phbs, list) {
1187 ret = spapr_dt_phb(spapr, phb, PHANDLE_INTC, fdt, NULL);
1188 if (ret < 0) {
1189 error_report("couldn't setup PCI devices in fdt");
1190 exit(1);
1191 }
1192 }
1193
1194 spapr_dt_cpus(fdt, spapr);
1195
1196 if (smc->dr_lmb_enabled) {
1197 _FDT(spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB));
1198 }
1199
1200 if (mc->has_hotpluggable_cpus) {
1201 int offset = fdt_path_offset(fdt, "/cpus");
1202 ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU);
1203 if (ret < 0) {
1204 error_report("Couldn't set up CPU DR device tree properties");
1205 exit(1);
1206 }
1207 }
1208
1209 /* /event-sources */
1210 spapr_dt_events(spapr, fdt);
1211
1212 /* /rtas */
1213 spapr_dt_rtas(spapr, fdt);
1214
1215 /* /chosen */
1216 spapr_dt_chosen(spapr, fdt, reset);
1217
1218 /* /hypervisor */
1219 if (kvm_enabled()) {
1220 spapr_dt_hypervisor(spapr, fdt);
1221 }
1222
1223 /* Build memory reserve map */
1224 if (reset) {
1225 if (spapr->kernel_size) {
1226 _FDT((fdt_add_mem_rsv(fdt, spapr->kernel_addr,
1227 spapr->kernel_size)));
1228 }
1229 if (spapr->initrd_size) {
1230 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base,
1231 spapr->initrd_size)));
1232 }
1233 }
1234
1235 if (smc->dr_phb_enabled) {
1236 ret = spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_PHB);
1237 if (ret < 0) {
1238 error_report("Couldn't set up PHB DR device tree properties");
1239 exit(1);
1240 }
1241 }
1242
1243 /* NVDIMM devices */
1244 if (mc->nvdimm_supported) {
1245 spapr_dt_persistent_memory(spapr, fdt);
1246 }
1247
1248 return fdt;
1249 }
1250
1251 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
1252 {
1253 SpaprMachineState *spapr = opaque;
1254
1255 return (addr & 0x0fffffff) + spapr->kernel_addr;
1256 }
1257
1258 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp,
1259 PowerPCCPU *cpu)
1260 {
1261 CPUPPCState *env = &cpu->env;
1262
1263 /* The TCG path should also be holding the BQL at this point */
1264 g_assert(qemu_mutex_iothread_locked());
1265
1266 if (msr_pr) {
1267 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1268 env->gpr[3] = H_PRIVILEGE;
1269 } else {
1270 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]);
1271 }
1272 }
1273
1274 struct LPCRSyncState {
1275 target_ulong value;
1276 target_ulong mask;
1277 };
1278
1279 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg)
1280 {
1281 struct LPCRSyncState *s = arg.host_ptr;
1282 PowerPCCPU *cpu = POWERPC_CPU(cs);
1283 CPUPPCState *env = &cpu->env;
1284 target_ulong lpcr;
1285
1286 cpu_synchronize_state(cs);
1287 lpcr = env->spr[SPR_LPCR];
1288 lpcr &= ~s->mask;
1289 lpcr |= s->value;
1290 ppc_store_lpcr(cpu, lpcr);
1291 }
1292
1293 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask)
1294 {
1295 CPUState *cs;
1296 struct LPCRSyncState s = {
1297 .value = value,
1298 .mask = mask
1299 };
1300 CPU_FOREACH(cs) {
1301 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s));
1302 }
1303 }
1304
1305 static void spapr_get_pate(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry)
1306 {
1307 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1308
1309 /* Copy PATE1:GR into PATE0:HR */
1310 entry->dw0 = spapr->patb_entry & PATE0_HR;
1311 entry->dw1 = spapr->patb_entry;
1312 }
1313
1314 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1315 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1316 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1317 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1318 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1319
1320 /*
1321 * Get the fd to access the kernel htab, re-opening it if necessary
1322 */
1323 static int get_htab_fd(SpaprMachineState *spapr)
1324 {
1325 Error *local_err = NULL;
1326
1327 if (spapr->htab_fd >= 0) {
1328 return spapr->htab_fd;
1329 }
1330
1331 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err);
1332 if (spapr->htab_fd < 0) {
1333 error_report_err(local_err);
1334 }
1335
1336 return spapr->htab_fd;
1337 }
1338
1339 void close_htab_fd(SpaprMachineState *spapr)
1340 {
1341 if (spapr->htab_fd >= 0) {
1342 close(spapr->htab_fd);
1343 }
1344 spapr->htab_fd = -1;
1345 }
1346
1347 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp)
1348 {
1349 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1350
1351 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1;
1352 }
1353
1354 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp)
1355 {
1356 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1357
1358 assert(kvm_enabled());
1359
1360 if (!spapr->htab) {
1361 return 0;
1362 }
1363
1364 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18);
1365 }
1366
1367 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp,
1368 hwaddr ptex, int n)
1369 {
1370 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1371 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64;
1372
1373 if (!spapr->htab) {
1374 /*
1375 * HTAB is controlled by KVM. Fetch into temporary buffer
1376 */
1377 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64);
1378 kvmppc_read_hptes(hptes, ptex, n);
1379 return hptes;
1380 }
1381
1382 /*
1383 * HTAB is controlled by QEMU. Just point to the internally
1384 * accessible PTEG.
1385 */
1386 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset);
1387 }
1388
1389 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp,
1390 const ppc_hash_pte64_t *hptes,
1391 hwaddr ptex, int n)
1392 {
1393 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1394
1395 if (!spapr->htab) {
1396 g_free((void *)hptes);
1397 }
1398
1399 /* Nothing to do for qemu managed HPT */
1400 }
1401
1402 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex,
1403 uint64_t pte0, uint64_t pte1)
1404 {
1405 SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp);
1406 hwaddr offset = ptex * HASH_PTE_SIZE_64;
1407
1408 if (!spapr->htab) {
1409 kvmppc_write_hpte(ptex, pte0, pte1);
1410 } else {
1411 if (pte0 & HPTE64_V_VALID) {
1412 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1);
1413 /*
1414 * When setting valid, we write PTE1 first. This ensures
1415 * proper synchronization with the reading code in
1416 * ppc_hash64_pteg_search()
1417 */
1418 smp_wmb();
1419 stq_p(spapr->htab + offset, pte0);
1420 } else {
1421 stq_p(spapr->htab + offset, pte0);
1422 /*
1423 * When clearing it we set PTE0 first. This ensures proper
1424 * synchronization with the reading code in
1425 * ppc_hash64_pteg_search()
1426 */
1427 smp_wmb();
1428 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1);
1429 }
1430 }
1431 }
1432
1433 static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex,
1434 uint64_t pte1)
1435 {
1436 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 15;
1437 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1438
1439 if (!spapr->htab) {
1440 /* There should always be a hash table when this is called */
1441 error_report("spapr_hpte_set_c called with no hash table !");
1442 return;
1443 }
1444
1445 /* The HW performs a non-atomic byte update */
1446 stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80);
1447 }
1448
1449 static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex,
1450 uint64_t pte1)
1451 {
1452 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 14;
1453 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1454
1455 if (!spapr->htab) {
1456 /* There should always be a hash table when this is called */
1457 error_report("spapr_hpte_set_r called with no hash table !");
1458 return;
1459 }
1460
1461 /* The HW performs a non-atomic byte update */
1462 stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01);
1463 }
1464
1465 int spapr_hpt_shift_for_ramsize(uint64_t ramsize)
1466 {
1467 int shift;
1468
1469 /* We aim for a hash table of size 1/128 the size of RAM (rounded
1470 * up). The PAPR recommendation is actually 1/64 of RAM size, but
1471 * that's much more than is needed for Linux guests */
1472 shift = ctz64(pow2ceil(ramsize)) - 7;
1473 shift = MAX(shift, 18); /* Minimum architected size */
1474 shift = MIN(shift, 46); /* Maximum architected size */
1475 return shift;
1476 }
1477
1478 void spapr_free_hpt(SpaprMachineState *spapr)
1479 {
1480 g_free(spapr->htab);
1481 spapr->htab = NULL;
1482 spapr->htab_shift = 0;
1483 close_htab_fd(spapr);
1484 }
1485
1486 void spapr_reallocate_hpt(SpaprMachineState *spapr, int shift,
1487 Error **errp)
1488 {
1489 long rc;
1490
1491 /* Clean up any HPT info from a previous boot */
1492 spapr_free_hpt(spapr);
1493
1494 rc = kvmppc_reset_htab(shift);
1495
1496 if (rc == -EOPNOTSUPP) {
1497 error_setg(errp, "HPT not supported in nested guests");
1498 return;
1499 }
1500
1501 if (rc < 0) {
1502 /* kernel-side HPT needed, but couldn't allocate one */
1503 error_setg_errno(errp, errno,
1504 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1505 shift);
1506 /* This is almost certainly fatal, but if the caller really
1507 * wants to carry on with shift == 0, it's welcome to try */
1508 } else if (rc > 0) {
1509 /* kernel-side HPT allocated */
1510 if (rc != shift) {
1511 error_setg(errp,
1512 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1513 shift, rc);
1514 }
1515
1516 spapr->htab_shift = shift;
1517 spapr->htab = NULL;
1518 } else {
1519 /* kernel-side HPT not needed, allocate in userspace instead */
1520 size_t size = 1ULL << shift;
1521 int i;
1522
1523 spapr->htab = qemu_memalign(size, size);
1524 if (!spapr->htab) {
1525 error_setg_errno(errp, errno,
1526 "Could not allocate HPT of order %d", shift);
1527 return;
1528 }
1529
1530 memset(spapr->htab, 0, size);
1531 spapr->htab_shift = shift;
1532
1533 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) {
1534 DIRTY_HPTE(HPTE(spapr->htab, i));
1535 }
1536 }
1537 /* We're setting up a hash table, so that means we're not radix */
1538 spapr->patb_entry = 0;
1539 spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT);
1540 }
1541
1542 void spapr_setup_hpt(SpaprMachineState *spapr)
1543 {
1544 int hpt_shift;
1545
1546 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) {
1547 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size);
1548 } else {
1549 uint64_t current_ram_size;
1550
1551 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size();
1552 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size);
1553 }
1554 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal);
1555
1556 if (kvm_enabled()) {
1557 hwaddr vrma_limit = kvmppc_vrma_limit(spapr->htab_shift);
1558
1559 /* Check our RMA fits in the possible VRMA */
1560 if (vrma_limit < spapr->rma_size) {
1561 error_report("Unable to create %" HWADDR_PRIu
1562 "MiB RMA (VRMA only allows %" HWADDR_PRIu "MiB",
1563 spapr->rma_size / MiB, vrma_limit / MiB);
1564 exit(EXIT_FAILURE);
1565 }
1566 }
1567 }
1568
1569 static int spapr_reset_drcs(Object *child, void *opaque)
1570 {
1571 SpaprDrc *drc =
1572 (SpaprDrc *) object_dynamic_cast(child,
1573 TYPE_SPAPR_DR_CONNECTOR);
1574
1575 if (drc) {
1576 spapr_drc_reset(drc);
1577 }
1578
1579 return 0;
1580 }
1581
1582 static void spapr_machine_reset(MachineState *machine)
1583 {
1584 SpaprMachineState *spapr = SPAPR_MACHINE(machine);
1585 PowerPCCPU *first_ppc_cpu;
1586 hwaddr fdt_addr;
1587 void *fdt;
1588 int rc;
1589
1590 kvmppc_svm_off(&error_fatal);
1591 spapr_caps_apply(spapr);
1592
1593 first_ppc_cpu = POWERPC_CPU(first_cpu);
1594 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() &&
1595 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0,
1596 spapr->max_compat_pvr)) {
1597 /*
1598 * If using KVM with radix mode available, VCPUs can be started
1599 * without a HPT because KVM will start them in radix mode.
1600 * Set the GR bit in PATE so that we know there is no HPT.
1601 */
1602 spapr->patb_entry = PATE1_GR;
1603 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT);
1604 } else {
1605 spapr_setup_hpt(spapr);
1606 }
1607
1608 qemu_devices_reset();
1609
1610 spapr_ovec_cleanup(spapr->ov5_cas);
1611 spapr->ov5_cas = spapr_ovec_new();
1612
1613 ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal);
1614
1615 /*
1616 * This is fixing some of the default configuration of the XIVE
1617 * devices. To be called after the reset of the machine devices.
1618 */
1619 spapr_irq_reset(spapr, &error_fatal);
1620
1621 /*
1622 * There is no CAS under qtest. Simulate one to please the code that
1623 * depends on spapr->ov5_cas. This is especially needed to test device
1624 * unplug, so we do that before resetting the DRCs.
1625 */
1626 if (qtest_enabled()) {
1627 spapr_ovec_cleanup(spapr->ov5_cas);
1628 spapr->ov5_cas = spapr_ovec_clone(spapr->ov5);
1629 }
1630
1631 /* DRC reset may cause a device to be unplugged. This will cause troubles
1632 * if this device is used by another device (eg, a running vhost backend
1633 * will crash QEMU if the DIMM holding the vring goes away). To avoid such
1634 * situations, we reset DRCs after all devices have been reset.
1635 */
1636 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL);
1637
1638 spapr_clear_pending_events(spapr);
1639
1640 /*
1641 * We place the device tree and RTAS just below either the top of the RMA,
1642 * or just below 2GB, whichever is lower, so that it can be
1643 * processed with 32-bit real mode code if necessary
1644 */
1645 fdt_addr = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FDT_MAX_SIZE;
1646
1647 fdt = spapr_build_fdt(spapr, true, FDT_MAX_SIZE);
1648
1649 rc = fdt_pack(fdt);
1650
1651 /* Should only fail if we've built a corrupted tree */
1652 assert(rc == 0);
1653
1654 /* Load the fdt */
1655 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
1656 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
1657 g_free(spapr->fdt_blob);
1658 spapr->fdt_size = fdt_totalsize(fdt);
1659 spapr->fdt_initial_size = spapr->fdt_size;
1660 spapr->fdt_blob = fdt;
1661
1662 /* Set up the entry state */
1663 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, 0, fdt_addr, 0);
1664 first_ppc_cpu->env.gpr[5] = 0;
1665
1666 spapr->fwnmi_system_reset_addr = -1;
1667 spapr->fwnmi_machine_check_addr = -1;
1668 spapr->fwnmi_machine_check_interlock = -1;
1669
1670 /* Signal all vCPUs waiting on this condition */
1671 qemu_cond_broadcast(&spapr->fwnmi_machine_check_interlock_cond);
1672
1673 migrate_del_blocker(spapr->fwnmi_migration_blocker);
1674 }
1675
1676 static void spapr_create_nvram(SpaprMachineState *spapr)
1677 {
1678 DeviceState *dev = qdev_new("spapr-nvram");
1679 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
1680
1681 if (dinfo) {
1682 qdev_prop_set_drive_err(dev, "drive", blk_by_legacy_dinfo(dinfo),
1683 &error_fatal);
1684 }
1685
1686 qdev_realize_and_unref(dev, &spapr->vio_bus->bus, &error_fatal);
1687
1688 spapr->nvram = (struct SpaprNvram *)dev;
1689 }
1690
1691 static void spapr_rtc_create(SpaprMachineState *spapr)
1692 {
1693 object_initialize_child_with_props(OBJECT(spapr), "rtc", &spapr->rtc,
1694 sizeof(spapr->rtc), TYPE_SPAPR_RTC,
1695 &error_fatal, NULL);
1696 qdev_realize(DEVICE(&spapr->rtc), NULL, &error_fatal);
1697 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc),
1698 "date");
1699 }
1700
1701 /* Returns whether we want to use VGA or not */
1702 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp)
1703 {
1704 switch (vga_interface_type) {
1705 case VGA_NONE:
1706 return false;
1707 case VGA_DEVICE:
1708 return true;
1709 case VGA_STD:
1710 case VGA_VIRTIO:
1711 case VGA_CIRRUS:
1712 return pci_vga_init(pci_bus) != NULL;
1713 default:
1714 error_setg(errp,
1715 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1716 return false;
1717 }
1718 }
1719
1720 static int spapr_pre_load(void *opaque)
1721 {
1722 int rc;
1723
1724 rc = spapr_caps_pre_load(opaque);
1725 if (rc) {
1726 return rc;
1727 }
1728
1729 return 0;
1730 }
1731
1732 static int spapr_post_load(void *opaque, int version_id)
1733 {
1734 SpaprMachineState *spapr = (SpaprMachineState *)opaque;
1735 int err = 0;
1736
1737 err = spapr_caps_post_migration(spapr);
1738 if (err) {
1739 return err;
1740 }
1741
1742 /*
1743 * In earlier versions, there was no separate qdev for the PAPR
1744 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1745 * So when migrating from those versions, poke the incoming offset
1746 * value into the RTC device
1747 */
1748 if (version_id < 3) {
1749 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset);
1750 if (err) {
1751 return err;
1752 }
1753 }
1754
1755 if (kvm_enabled() && spapr->patb_entry) {
1756 PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
1757 bool radix = !!(spapr->patb_entry & PATE1_GR);
1758 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE);
1759
1760 /*
1761 * Update LPCR:HR and UPRT as they may not be set properly in
1762 * the stream
1763 */
1764 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0,
1765 LPCR_HR | LPCR_UPRT);
1766
1767 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry);
1768 if (err) {
1769 error_report("Process table config unsupported by the host");
1770 return -EINVAL;
1771 }
1772 }
1773
1774 err = spapr_irq_post_load(spapr, version_id);
1775 if (err) {
1776 return err;
1777 }
1778
1779 return err;
1780 }
1781
1782 static int spapr_pre_save(void *opaque)
1783 {
1784 int rc;
1785
1786 rc = spapr_caps_pre_save(opaque);
1787 if (rc) {
1788 return rc;
1789 }
1790
1791 return 0;
1792 }
1793
1794 static bool version_before_3(void *opaque, int version_id)
1795 {
1796 return version_id < 3;
1797 }
1798
1799 static bool spapr_pending_events_needed(void *opaque)
1800 {
1801 SpaprMachineState *spapr = (SpaprMachineState *)opaque;
1802 return !QTAILQ_EMPTY(&spapr->pending_events);
1803 }
1804
1805 static const VMStateDescription vmstate_spapr_event_entry = {
1806 .name = "spapr_event_log_entry",
1807 .version_id = 1,
1808 .minimum_version_id = 1,
1809 .fields = (VMStateField[]) {
1810 VMSTATE_UINT32(summary, SpaprEventLogEntry),
1811 VMSTATE_UINT32(extended_length, SpaprEventLogEntry),
1812 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0,
1813 NULL, extended_length),
1814 VMSTATE_END_OF_LIST()
1815 },
1816 };
1817
1818 static const VMStateDescription vmstate_spapr_pending_events = {
1819 .name = "spapr_pending_events",
1820 .version_id = 1,
1821 .minimum_version_id = 1,
1822 .needed = spapr_pending_events_needed,
1823 .fields = (VMStateField[]) {
1824 VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1,
1825 vmstate_spapr_event_entry, SpaprEventLogEntry, next),
1826 VMSTATE_END_OF_LIST()
1827 },
1828 };
1829
1830 static bool spapr_ov5_cas_needed(void *opaque)
1831 {
1832 SpaprMachineState *spapr = opaque;
1833 SpaprOptionVector *ov5_mask = spapr_ovec_new();
1834 bool cas_needed;
1835
1836 /* Prior to the introduction of SpaprOptionVector, we had two option
1837 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY.
1838 * Both of these options encode machine topology into the device-tree
1839 * in such a way that the now-booted OS should still be able to interact
1840 * appropriately with QEMU regardless of what options were actually
1841 * negotiatied on the source side.
1842 *
1843 * As such, we can avoid migrating the CAS-negotiated options if these
1844 * are the only options available on the current machine/platform.
1845 * Since these are the only options available for pseries-2.7 and
1846 * earlier, this allows us to maintain old->new/new->old migration
1847 * compatibility.
1848 *
1849 * For QEMU 2.8+, there are additional CAS-negotiatable options available
1850 * via default pseries-2.8 machines and explicit command-line parameters.
1851 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware
1852 * of the actual CAS-negotiated values to continue working properly. For
1853 * example, availability of memory unplug depends on knowing whether
1854 * OV5_HP_EVT was negotiated via CAS.
1855 *
1856 * Thus, for any cases where the set of available CAS-negotiatable
1857 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we
1858 * include the CAS-negotiated options in the migration stream, unless
1859 * if they affect boot time behaviour only.
1860 */
1861 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY);
1862 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY);
1863 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2);
1864
1865 /* We need extra information if we have any bits outside the mask
1866 * defined above */
1867 cas_needed = !spapr_ovec_subset(spapr->ov5, ov5_mask);
1868
1869 spapr_ovec_cleanup(ov5_mask);
1870
1871 return cas_needed;
1872 }
1873
1874 static const VMStateDescription vmstate_spapr_ov5_cas = {
1875 .name = "spapr_option_vector_ov5_cas",
1876 .version_id = 1,
1877 .minimum_version_id = 1,
1878 .needed = spapr_ov5_cas_needed,
1879 .fields = (VMStateField[]) {
1880 VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1,
1881 vmstate_spapr_ovec, SpaprOptionVector),
1882 VMSTATE_END_OF_LIST()
1883 },
1884 };
1885
1886 static bool spapr_patb_entry_needed(void *opaque)
1887 {
1888 SpaprMachineState *spapr = opaque;
1889
1890 return !!spapr->patb_entry;
1891 }
1892
1893 static const VMStateDescription vmstate_spapr_patb_entry = {
1894 .name = "spapr_patb_entry",
1895 .version_id = 1,
1896 .minimum_version_id = 1,
1897 .needed = spapr_patb_entry_needed,
1898 .fields = (VMStateField[]) {
1899 VMSTATE_UINT64(patb_entry, SpaprMachineState),
1900 VMSTATE_END_OF_LIST()
1901 },
1902 };
1903
1904 static bool spapr_irq_map_needed(void *opaque)
1905 {
1906 SpaprMachineState *spapr = opaque;
1907
1908 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr);
1909 }
1910
1911 static const VMStateDescription vmstate_spapr_irq_map = {
1912 .name = "spapr_irq_map",
1913 .version_id = 1,
1914 .minimum_version_id = 1,
1915 .needed = spapr_irq_map_needed,
1916 .fields = (VMStateField[]) {
1917 VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr),
1918 VMSTATE_END_OF_LIST()
1919 },
1920 };
1921
1922 static bool spapr_dtb_needed(void *opaque)
1923 {
1924 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque);
1925
1926 return smc->update_dt_enabled;
1927 }
1928
1929 static int spapr_dtb_pre_load(void *opaque)
1930 {
1931 SpaprMachineState *spapr = (SpaprMachineState *)opaque;
1932
1933 g_free(spapr->fdt_blob);
1934 spapr->fdt_blob = NULL;
1935 spapr->fdt_size = 0;
1936
1937 return 0;
1938 }
1939
1940 static const VMStateDescription vmstate_spapr_dtb = {
1941 .name = "spapr_dtb",
1942 .version_id = 1,
1943 .minimum_version_id = 1,
1944 .needed = spapr_dtb_needed,
1945 .pre_load = spapr_dtb_pre_load,
1946 .fields = (VMStateField[]) {
1947 VMSTATE_UINT32(fdt_initial_size, SpaprMachineState),
1948 VMSTATE_UINT32(fdt_size, SpaprMachineState),
1949 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL,
1950 fdt_size),
1951 VMSTATE_END_OF_LIST()
1952 },
1953 };
1954
1955 static bool spapr_fwnmi_needed(void *opaque)
1956 {
1957 SpaprMachineState *spapr = (SpaprMachineState *)opaque;
1958
1959 return spapr->fwnmi_machine_check_addr != -1;
1960 }
1961
1962 static int spapr_fwnmi_pre_save(void *opaque)
1963 {
1964 SpaprMachineState *spapr = (SpaprMachineState *)opaque;
1965
1966 /*
1967 * Check if machine check handling is in progress and print a
1968 * warning message.
1969 */
1970 if (spapr->fwnmi_machine_check_interlock != -1) {
1971 warn_report("A machine check is being handled during migration. The"
1972 "handler may run and log hardware error on the destination");
1973 }
1974
1975 return 0;
1976 }
1977
1978 static const VMStateDescription vmstate_spapr_fwnmi = {
1979 .name = "spapr_fwnmi",
1980 .version_id = 1,
1981 .minimum_version_id = 1,
1982 .needed = spapr_fwnmi_needed,
1983 .pre_save = spapr_fwnmi_pre_save,
1984 .fields = (VMStateField[]) {
1985 VMSTATE_UINT64(fwnmi_system_reset_addr, SpaprMachineState),
1986 VMSTATE_UINT64(fwnmi_machine_check_addr, SpaprMachineState),
1987 VMSTATE_INT32(fwnmi_machine_check_interlock, SpaprMachineState),
1988 VMSTATE_END_OF_LIST()
1989 },
1990 };
1991
1992 static const VMStateDescription vmstate_spapr = {
1993 .name = "spapr",
1994 .version_id = 3,
1995 .minimum_version_id = 1,
1996 .pre_load = spapr_pre_load,
1997 .post_load = spapr_post_load,
1998 .pre_save = spapr_pre_save,
1999 .fields = (VMStateField[]) {
2000 /* used to be @next_irq */
2001 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4),
2002
2003 /* RTC offset */
2004 VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3),
2005
2006 VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2),
2007 VMSTATE_END_OF_LIST()
2008 },
2009 .subsections = (const VMStateDescription*[]) {
2010 &vmstate_spapr_ov5_cas,
2011 &vmstate_spapr_patb_entry,
2012 &vmstate_spapr_pending_events,
2013 &vmstate_spapr_cap_htm,
2014 &vmstate_spapr_cap_vsx,
2015 &vmstate_spapr_cap_dfp,
2016 &vmstate_spapr_cap_cfpc,
2017 &vmstate_spapr_cap_sbbc,
2018 &vmstate_spapr_cap_ibs,
2019 &vmstate_spapr_cap_hpt_maxpagesize,
2020 &vmstate_spapr_irq_map,
2021 &vmstate_spapr_cap_nested_kvm_hv,
2022 &vmstate_spapr_dtb,
2023 &vmstate_spapr_cap_large_decr,
2024 &vmstate_spapr_cap_ccf_assist,
2025 &vmstate_spapr_cap_fwnmi,
2026 &vmstate_spapr_fwnmi,
2027 NULL
2028 }
2029 };
2030
2031 static int htab_save_setup(QEMUFile *f, void *opaque)
2032 {
2033 SpaprMachineState *spapr = opaque;
2034
2035 /* "Iteration" header */
2036 if (!spapr->htab_shift) {
2037 qemu_put_be32(f, -1);
2038 } else {
2039 qemu_put_be32(f, spapr->htab_shift);
2040 }
2041
2042 if (spapr->htab) {
2043 spapr->htab_save_index = 0;
2044 spapr->htab_first_pass = true;
2045 } else {
2046 if (spapr->htab_shift) {
2047 assert(kvm_enabled());
2048 }
2049 }
2050
2051
2052 return 0;
2053 }
2054
2055 static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr,
2056 int chunkstart, int n_valid, int n_invalid)
2057 {
2058 qemu_put_be32(f, chunkstart);
2059 qemu_put_be16(f, n_valid);
2060 qemu_put_be16(f, n_invalid);
2061 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
2062 HASH_PTE_SIZE_64 * n_valid);
2063 }
2064
2065 static void htab_save_end_marker(QEMUFile *f)
2066 {
2067 qemu_put_be32(f, 0);
2068 qemu_put_be16(f, 0);
2069 qemu_put_be16(f, 0);
2070 }
2071
2072 static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr,
2073 int64_t max_ns)
2074 {
2075 bool has_timeout = max_ns != -1;
2076 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
2077 int index = spapr->htab_save_index;
2078 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
2079
2080 assert(spapr->htab_first_pass);
2081
2082 do {
2083 int chunkstart;
2084
2085 /* Consume invalid HPTEs */
2086 while ((index < htabslots)
2087 && !HPTE_VALID(HPTE(spapr->htab, index))) {
2088 CLEAN_HPTE(HPTE(spapr->htab, index));
2089 index++;
2090 }
2091
2092 /* Consume valid HPTEs */
2093 chunkstart = index;
2094 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
2095 && HPTE_VALID(HPTE(spapr->htab, index))) {
2096 CLEAN_HPTE(HPTE(spapr->htab, index));
2097 index++;
2098 }
2099
2100 if (index > chunkstart) {
2101 int n_valid = index - chunkstart;
2102
2103 htab_save_chunk(f, spapr, chunkstart, n_valid, 0);
2104
2105 if (has_timeout &&
2106 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
2107 break;
2108 }
2109 }
2110 } while ((index < htabslots) && !qemu_file_rate_limit(f));
2111
2112 if (index >= htabslots) {
2113 assert(index == htabslots);
2114 index = 0;
2115 spapr->htab_first_pass = false;
2116 }
2117 spapr->htab_save_index = index;
2118 }
2119
2120 static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr,
2121 int64_t max_ns)
2122 {
2123 bool final = max_ns < 0;
2124 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
2125 int examined = 0, sent = 0;
2126 int index = spapr->htab_save_index;
2127 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
2128
2129 assert(!spapr->htab_first_pass);
2130
2131 do {
2132 int chunkstart, invalidstart;
2133
2134 /* Consume non-dirty HPTEs */
2135 while ((index < htabslots)
2136 && !HPTE_DIRTY(HPTE(spapr->htab, index))) {
2137 index++;
2138 examined++;
2139 }
2140
2141 chunkstart = index;
2142 /* Consume valid dirty HPTEs */
2143 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
2144 && HPTE_DIRTY(HPTE(spapr->htab, index))
2145 && HPTE_VALID(HPTE(spapr->htab, index))) {
2146 CLEAN_HPTE(HPTE(spapr->htab, index));
2147 index++;
2148 examined++;
2149 }
2150
2151 invalidstart = index;
2152 /* Consume invalid dirty HPTEs */
2153 while ((index < htabslots) && (index - invalidstart < USHRT_MAX)
2154 && HPTE_DIRTY(HPTE(spapr->htab, index))
2155 && !HPTE_VALID(HPTE(spapr->htab, index))) {
2156 CLEAN_HPTE(HPTE(spapr->htab, index));
2157 index++;
2158 examined++;
2159 }
2160
2161 if (index > chunkstart) {
2162 int n_valid = invalidstart - chunkstart;
2163 int n_invalid = index - invalidstart;
2164
2165 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid);
2166 sent += index - chunkstart;
2167
2168 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
2169 break;
2170 }
2171 }
2172
2173 if (examined >= htabslots) {
2174 break;
2175 }
2176
2177 if (index >= htabslots) {
2178 assert(index == htabslots);
2179 index = 0;
2180 }
2181 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final));
2182
2183 if (index >= htabslots) {
2184 assert(index == htabslots);
2185 index = 0;
2186 }
2187
2188 spapr->htab_save_index = index;
2189
2190 return (examined >= htabslots) && (sent == 0) ? 1 : 0;
2191 }
2192
2193 #define MAX_ITERATION_NS 5000000 /* 5 ms */
2194 #define MAX_KVM_BUF_SIZE 2048
2195
2196 static int htab_save_iterate(QEMUFile *f, void *opaque)
2197 {
2198 SpaprMachineState *spapr = opaque;
2199 int fd;
2200 int rc = 0;
2201
2202 /* Iteration header */
2203 if (!spapr->htab_shift) {
2204 qemu_put_be32(f, -1);
2205 return 1;
2206 } else {
2207 qemu_put_be32(f, 0);
2208 }
2209
2210 if (!spapr->htab) {
2211 assert(kvm_enabled());
2212
2213 fd = get_htab_fd(spapr);
2214 if (fd < 0) {
2215 return fd;
2216 }
2217
2218 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS);
2219 if (rc < 0) {
2220 return rc;
2221 }
2222 } else if (spapr->htab_first_pass) {
2223 htab_save_first_pass(f, spapr, MAX_ITERATION_NS);
2224 } else {
2225 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS);
2226 }
2227
2228 htab_save_end_marker(f);
2229
2230 return rc;
2231 }
2232
2233 static int htab_save_complete(QEMUFile *f, void *opaque)
2234 {
2235 SpaprMachineState *spapr = opaque;
2236 int fd;
2237
2238 /* Iteration header */
2239 if (!spapr->htab_shift) {
2240 qemu_put_be32(f, -1);
2241 return 0;
2242 } else {
2243 qemu_put_be32(f, 0);
2244 }
2245
2246 if (!spapr->htab) {
2247 int rc;
2248
2249 assert(kvm_enabled());
2250
2251 fd = get_htab_fd(spapr);
2252 if (fd < 0) {
2253 return fd;
2254 }
2255
2256 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1);
2257 if (rc < 0) {
2258 return rc;
2259 }
2260 } else {
2261 if (spapr->htab_first_pass) {
2262 htab_save_first_pass(f, spapr, -1);
2263 }
2264 htab_save_later_pass(f, spapr, -1);
2265 }
2266
2267 /* End marker */
2268 htab_save_end_marker(f);
2269
2270 return 0;
2271 }
2272
2273 static int htab_load(QEMUFile *f, void *opaque, int version_id)
2274 {
2275 SpaprMachineState *spapr = opaque;
2276 uint32_t section_hdr;
2277 int fd = -1;
2278 Error *local_err = NULL;
2279
2280 if (version_id < 1 || version_id > 1) {
2281 error_report("htab_load() bad version");
2282 return -EINVAL;
2283 }
2284
2285 section_hdr = qemu_get_be32(f);
2286
2287 if (section_hdr == -1) {
2288 spapr_free_hpt(spapr);
2289 return 0;
2290 }
2291
2292 if (section_hdr) {
2293 /* First section gives the htab size */
2294 spapr_reallocate_hpt(spapr, section_hdr, &local_err);
2295 if (local_err) {
2296 error_report_err(local_err);
2297 return -EINVAL;
2298 }
2299 return 0;
2300 }
2301
2302 if (!spapr->htab) {
2303 assert(kvm_enabled());
2304
2305 fd = kvmppc_get_htab_fd(true, 0, &local_err);
2306 if (fd < 0) {
2307 error_report_err(local_err);
2308 return fd;
2309 }
2310 }
2311
2312 while (true) {
2313 uint32_t index;
2314 uint16_t n_valid, n_invalid;
2315
2316 index = qemu_get_be32(f);
2317 n_valid = qemu_get_be16(f);
2318 n_invalid = qemu_get_be16(f);
2319
2320 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) {
2321 /* End of Stream */
2322 break;
2323 }
2324
2325 if ((index + n_valid + n_invalid) >
2326 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) {
2327 /* Bad index in stream */
2328 error_report(
2329 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
2330 index, n_valid, n_invalid, spapr->htab_shift);
2331 return -EINVAL;
2332 }
2333
2334 if (spapr->htab) {
2335 if (n_valid) {
2336 qemu_get_buffer(f, HPTE(spapr->htab, index),
2337 HASH_PTE_SIZE_64 * n_valid);
2338 }
2339 if (n_invalid) {
2340 memset(HPTE(spapr->htab, index + n_valid), 0,
2341 HASH_PTE_SIZE_64 * n_invalid);
2342 }
2343 } else {
2344 int rc;
2345
2346 assert(fd >= 0);
2347
2348 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid);
2349 if (rc < 0) {
2350 return rc;
2351 }
2352 }
2353 }
2354
2355 if (!spapr->htab) {
2356 assert(fd >= 0);
2357 close(fd);
2358 }
2359
2360 return 0;
2361 }
2362
2363 static void htab_save_cleanup(void *opaque)
2364 {
2365 SpaprMachineState *spapr = opaque;
2366
2367 close_htab_fd(spapr);
2368 }
2369
2370 static SaveVMHandlers savevm_htab_handlers = {
2371 .save_setup = htab_save_setup,
2372 .save_live_iterate = htab_save_iterate,
2373 .save_live_complete_precopy = htab_save_complete,
2374 .save_cleanup = htab_save_cleanup,
2375 .load_state = htab_load,
2376 };
2377
2378 static void spapr_boot_set(void *opaque, const char *boot_device,
2379 Error **errp)
2380 {
2381 MachineState *machine = MACHINE(opaque);
2382 machine->boot_order = g_strdup(boot_device);
2383 }
2384
2385 static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr)
2386 {
2387 MachineState *machine = MACHINE(spapr);
2388 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
2389 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size;
2390 int i;
2391
2392 for (i = 0; i < nr_lmbs; i++) {
2393 uint64_t addr;
2394
2395 addr = i * lmb_size + machine->device_memory->base;
2396 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB,
2397 addr / lmb_size);
2398 }
2399 }
2400
2401 /*
2402 * If RAM size, maxmem size and individual node mem sizes aren't aligned
2403 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
2404 * since we can't support such unaligned sizes with DRCONF_MEMORY.
2405 */
2406 static void spapr_validate_node_memory(MachineState *machine, Error **errp)
2407 {
2408 int i;
2409
2410 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) {
2411 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT
2412 " is not aligned to %" PRIu64 " MiB",
2413 machine->ram_size,
2414 SPAPR_MEMORY_BLOCK_SIZE / MiB);
2415 return;
2416 }
2417
2418 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) {
2419 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT
2420 " is not aligned to %" PRIu64 " MiB",
2421 machine->ram_size,
2422 SPAPR_MEMORY_BLOCK_SIZE / MiB);
2423 return;
2424 }
2425
2426 for (i = 0; i < machine->numa_state->num_nodes; i++) {
2427 if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) {
2428 error_setg(errp,
2429 "Node %d memory size 0x%" PRIx64
2430 " is not aligned to %" PRIu64 " MiB",
2431 i, machine->numa_state->nodes[i].node_mem,
2432 SPAPR_MEMORY_BLOCK_SIZE / MiB);
2433 return;
2434 }
2435 }
2436 }
2437
2438 /* find cpu slot in machine->possible_cpus by core_id */
2439 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
2440 {
2441 int index = id / ms->smp.threads;
2442
2443 if (index >= ms->possible_cpus->len) {
2444 return NULL;
2445 }
2446 if (idx) {
2447 *idx = index;
2448 }
2449 return &ms->possible_cpus->cpus[index];
2450 }
2451
2452 static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp)
2453 {
2454 MachineState *ms = MACHINE(spapr);
2455 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
2456 Error *local_err = NULL;
2457 bool vsmt_user = !!spapr->vsmt;
2458 int kvm_smt = kvmppc_smt_threads();
2459 int ret;
2460 unsigned int smp_threads = ms->smp.threads;
2461
2462 if (!kvm_enabled() && (smp_threads > 1)) {
2463 error_setg(errp, "TCG cannot support more than 1 thread/core "
2464 "on a pseries machine");
2465 return;
2466 }
2467 if (!is_power_of_2(smp_threads)) {
2468 error_setg(errp, "Cannot support %d threads/core on a pseries "
2469 "machine because it must be a power of 2", smp_threads);
2470 return;
2471 }
2472
2473 /* Detemine the VSMT mode to use: */
2474 if (vsmt_user) {
2475 if (spapr->vsmt < smp_threads) {
2476 error_setg(errp, "Cannot support VSMT mode %d"
2477 " because it must be >= threads/core (%d)",
2478 spapr->vsmt, smp_threads);
2479 return;
2480 }
2481 /* In this case, spapr->vsmt has been set by the command line */
2482 } else if (!smc->smp_threads_vsmt) {
2483 /*
2484 * Default VSMT value is tricky, because we need it to be as
2485 * consistent as possible (for migration), but this requires
2486 * changing it for at least some existing cases. We pick 8 as
2487 * the value that we'd get with KVM on POWER8, the
2488 * overwhelmingly common case in production systems.
2489 */
2490 spapr->vsmt = MAX(8, smp_threads);
2491 } else {
2492 spapr->vsmt = smp_threads;
2493 }
2494
2495 /* KVM: If necessary, set the SMT mode: */
2496 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) {
2497 ret = kvmppc_set_smt_threads(spapr->vsmt);
2498 if (ret) {
2499 /* Looks like KVM isn't able to change VSMT mode */
2500 error_setg(&local_err,
2501 "Failed to set KVM's VSMT mode to %d (errno %d)",
2502 spapr->vsmt, ret);
2503 /* We can live with that if the default one is big enough
2504 * for the number of threads, and a submultiple of the one
2505 * we want. In this case we'll waste some vcpu ids, but
2506 * behaviour will be correct */
2507 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) {
2508 warn_report_err(local_err);
2509 } else {
2510 if (!vsmt_user) {
2511 error_append_hint(&local_err,
2512 "On PPC, a VM with %d threads/core"
2513 " on a host with %d threads/core"
2514 " requires the use of VSMT mode %d.\n",
2515 smp_threads, kvm_smt, spapr->vsmt);
2516 }
2517 kvmppc_error_append_smt_possible_hint(&local_err);
2518 error_propagate(errp, local_err);
2519 }
2520 }
2521 }
2522 /* else TCG: nothing to do currently */
2523 }
2524
2525 static void spapr_init_cpus(SpaprMachineState *spapr)
2526 {
2527 MachineState *machine = MACHINE(spapr);
2528 MachineClass *mc = MACHINE_GET_CLASS(machine);
2529 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
2530 const char *type = spapr_get_cpu_core_type(machine->cpu_type);
2531 const CPUArchIdList *possible_cpus;
2532 unsigned int smp_cpus = machine->smp.cpus;
2533 unsigned int smp_threads = machine->smp.threads;
2534 unsigned int max_cpus = machine->smp.max_cpus;
2535 int boot_cores_nr = smp_cpus / smp_threads;
2536 int i;
2537
2538 possible_cpus = mc->possible_cpu_arch_ids(machine);
2539 if (mc->has_hotpluggable_cpus) {
2540 if (smp_cpus % smp_threads) {
2541 error_report("smp_cpus (%u) must be multiple of threads (%u)",
2542 smp_cpus, smp_threads);
2543 exit(1);
2544 }
2545 if (max_cpus % smp_threads) {
2546 error_report("max_cpus (%u) must be multiple of threads (%u)",
2547 max_cpus, smp_threads);
2548 exit(1);
2549 }
2550 } else {
2551 if (max_cpus != smp_cpus) {
2552 error_report("This machine version does not support CPU hotplug");
2553 exit(1);
2554 }
2555 boot_cores_nr = possible_cpus->len;
2556 }
2557
2558 if (smc->pre_2_10_has_unused_icps) {
2559 int i;
2560
2561 for (i = 0; i < spapr_max_server_number(spapr); i++) {
2562 /* Dummy entries get deregistered when real ICPState objects
2563 * are registered during CPU core hotplug.
2564 */
2565 pre_2_10_vmstate_register_dummy_icp(i);
2566 }
2567 }
2568
2569 for (i = 0; i < possible_cpus->len; i++) {
2570 int core_id = i * smp_threads;
2571
2572 if (mc->has_hotpluggable_cpus) {
2573 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU,
2574 spapr_vcpu_id(spapr, core_id));
2575 }
2576
2577 if (i < boot_cores_nr) {
2578 Object *core = object_new(type);
2579 int nr_threads = smp_threads;
2580
2581 /* Handle the partially filled core for older machine types */
2582 if ((i + 1) * smp_threads >= smp_cpus) {
2583 nr_threads = smp_cpus - i * smp_threads;
2584 }
2585
2586 object_property_set_int(core, "nr-threads", nr_threads,
2587 &error_fatal);
2588 object_property_set_int(core, CPU_CORE_PROP_CORE_ID, core_id,
2589 &error_fatal);
2590 qdev_realize(DEVICE(core), NULL, &error_fatal);
2591
2592 object_unref(core);
2593 }
2594 }
2595 }
2596
2597 static PCIHostState *spapr_create_default_phb(void)
2598 {
2599 DeviceState *dev;
2600
2601 dev = qdev_new(TYPE_SPAPR_PCI_HOST_BRIDGE);
2602 qdev_prop_set_uint32(dev, "index", 0);
2603 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
2604
2605 return PCI_HOST_BRIDGE(dev);
2606 }
2607
2608 static hwaddr spapr_rma_size(SpaprMachineState *spapr, Error **errp)
2609 {
2610 MachineState *machine = MACHINE(spapr);
2611 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
2612 hwaddr rma_size = machine->ram_size;
2613 hwaddr node0_size = spapr_node0_size(machine);
2614
2615 /* RMA has to fit in the first NUMA node */
2616 rma_size = MIN(rma_size, node0_size);
2617
2618 /*
2619 * VRMA access is via a special 1TiB SLB mapping, so the RMA can
2620 * never exceed that
2621 */
2622 rma_size = MIN(rma_size, 1 * TiB);
2623
2624 /*
2625 * Clamp the RMA size based on machine type. This is for
2626 * migration compatibility with older qemu versions, which limited
2627 * the RMA size for complicated and mostly bad reasons.
2628 */
2629 if (smc->rma_limit) {
2630 rma_size = MIN(rma_size, smc->rma_limit);
2631 }
2632
2633 if (rma_size < MIN_RMA_SLOF) {
2634 error_setg(errp,
2635 "pSeries SLOF firmware requires >= %" HWADDR_PRIx
2636 "ldMiB guest RMA (Real Mode Area memory)",
2637 MIN_RMA_SLOF / MiB);
2638 return 0;
2639 }
2640
2641 return rma_size;
2642 }
2643
2644 /* pSeries LPAR / sPAPR hardware init */
2645 static void spapr_machine_init(MachineState *machine)
2646 {
2647 SpaprMachineState *spapr = SPAPR_MACHINE(machine);
2648 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
2649 MachineClass *mc = MACHINE_GET_CLASS(machine);
2650 const char *kernel_filename = machine->kernel_filename;
2651 const char *initrd_filename = machine->initrd_filename;
2652 PCIHostState *phb;
2653 int i;
2654 MemoryRegion *sysmem = get_system_memory();
2655 long load_limit, fw_size;
2656 char *filename;
2657 Error *resize_hpt_err = NULL;
2658
2659 msi_nonbroken = true;
2660
2661 QLIST_INIT(&spapr->phbs);
2662 QTAILQ_INIT(&spapr->pending_dimm_unplugs);
2663
2664 /* Determine capabilities to run with */
2665 spapr_caps_init(spapr);
2666
2667 kvmppc_check_papr_resize_hpt(&resize_hpt_err);
2668 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) {
2669 /*
2670 * If the user explicitly requested a mode we should either
2671 * supply it, or fail completely (which we do below). But if
2672 * it's not set explicitly, we reset our mode to something
2673 * that works
2674 */
2675 if (resize_hpt_err) {
2676 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED;
2677 error_free(resize_hpt_err);
2678 resize_hpt_err = NULL;
2679 } else {
2680 spapr->resize_hpt = smc->resize_hpt_default;
2681 }
2682 }
2683
2684 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT);
2685
2686 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) {
2687 /*
2688 * User requested HPT resize, but this host can't supply it. Bail out
2689 */
2690 error_report_err(resize_hpt_err);
2691 exit(1);
2692 }
2693 error_free(resize_hpt_err);
2694
2695 spapr->rma_size = spapr_rma_size(spapr, &error_fatal);
2696
2697 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
2698 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD;
2699
2700 /*
2701 * VSMT must be set in order to be able to compute VCPU ids, ie to
2702 * call spapr_max_server_number() or spapr_vcpu_id().
2703 */
2704 spapr_set_vsmt_mode(spapr, &error_fatal);
2705
2706 /* Set up Interrupt Controller before we create the VCPUs */
2707 spapr_irq_init(spapr, &error_fatal);
2708
2709 /* Set up containers for ibm,client-architecture-support negotiated options
2710 */
2711 spapr->ov5 = spapr_ovec_new();
2712 spapr->ov5_cas = spapr_ovec_new();
2713
2714 if (smc->dr_lmb_enabled) {
2715 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY);
2716 spapr_validate_node_memory(machine, &error_fatal);
2717 }
2718
2719 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY);
2720
2721 /* advertise support for dedicated HP event source to guests */
2722 if (spapr->use_hotplug_event_source) {
2723 spapr_ovec_set(spapr->ov5, OV5_HP_EVT);
2724 }
2725
2726 /* advertise support for HPT resizing */
2727 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) {
2728 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE);
2729 }
2730
2731 /* advertise support for ibm,dyamic-memory-v2 */
2732 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2);
2733
2734 /* advertise XIVE on POWER9 machines */
2735 if (spapr->irq->xive) {
2736 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT);
2737 }
2738
2739 /* init CPUs */
2740 spapr_init_cpus(spapr);
2741
2742 /*
2743 * check we don't have a memory-less/cpu-less NUMA node
2744 * Firmware relies on the existing memory/cpu topology to provide the
2745 * NUMA topology to the kernel.
2746 * And the linux kernel needs to know the NUMA topology at start
2747 * to be able to hotplug CPUs later.
2748 */
2749 if (machine->numa_state->num_nodes) {
2750 for (i = 0; i < machine->numa_state->num_nodes; ++i) {
2751 /* check for memory-less node */
2752 if (machine->numa_state->nodes[i].node_mem == 0) {
2753 CPUState *cs;
2754 int found = 0;
2755 /* check for cpu-less node */
2756 CPU_FOREACH(cs) {
2757 PowerPCCPU *cpu = POWERPC_CPU(cs);
2758 if (cpu->node_id == i) {
2759 found = 1;
2760 break;
2761 }
2762 }
2763 /* memory-less and cpu-less node */
2764 if (!found) {
2765 error_report(
2766 "Memory-less/cpu-less nodes are not supported (node %d)",
2767 i);
2768 exit(1);
2769 }
2770 }
2771 }
2772
2773 }
2774
2775 /*
2776 * NVLink2-connected GPU RAM needs to be placed on a separate NUMA node.
2777 * We assign a new numa ID per GPU in spapr_pci_collect_nvgpu() which is
2778 * called from vPHB reset handler so we initialize the counter here.
2779 * If no NUMA is configured from the QEMU side, we start from 1 as GPU RAM
2780 * must be equally distant from any other node.
2781 * The final value of spapr->gpu_numa_id is going to be written to
2782 * max-associativity-domains in spapr_build_fdt().
2783 */
2784 spapr->gpu_numa_id = MAX(1, machine->numa_state->num_nodes);
2785
2786 /* Init numa_assoc_array */
2787 spapr_numa_associativity_init(spapr, machine);
2788
2789 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) &&
2790 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0,
2791 spapr->max_compat_pvr)) {
2792 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_300);
2793 /* KVM and TCG always allow GTSE with radix... */
2794 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE);
2795 }
2796 /* ... but not with hash (currently). */
2797
2798 if (kvm_enabled()) {
2799 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
2800 kvmppc_enable_logical_ci_hcalls();
2801 kvmppc_enable_set_mode_hcall();
2802
2803 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */
2804 kvmppc_enable_clear_ref_mod_hcalls();
2805
2806 /* Enable H_PAGE_INIT */
2807 kvmppc_enable_h_page_init();
2808 }
2809
2810 /* map RAM */
2811 memory_region_add_subregion(sysmem, 0, machine->ram);
2812
2813 /* always allocate the device memory information */
2814 machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
2815
2816 /* initialize hotplug memory address space */
2817 if (machine->ram_size < machine->maxram_size) {
2818 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size;
2819 /*
2820 * Limit the number of hotpluggable memory slots to half the number
2821 * slots that KVM supports, leaving the other half for PCI and other
2822 * devices. However ensure that number of slots doesn't drop below 32.
2823 */
2824 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 :
2825 SPAPR_MAX_RAM_SLOTS;
2826
2827 if (max_memslots < SPAPR_MAX_RAM_SLOTS) {
2828 max_memslots = SPAPR_MAX_RAM_SLOTS;
2829 }
2830 if (machine->ram_slots > max_memslots) {
2831 error_report("Specified number of memory slots %"
2832 PRIu64" exceeds max supported %d",
2833 machine->ram_slots, max_memslots);
2834 exit(1);
2835 }
2836
2837 machine->device_memory->base = ROUND_UP(machine->ram_size,
2838 SPAPR_DEVICE_MEM_ALIGN);
2839 memory_region_init(&machine->device_memory->mr, OBJECT(spapr),
2840 "device-memory", device_mem_size);
2841 memory_region_add_subregion(sysmem, machine->device_memory->base,
2842 &machine->device_memory->mr);
2843 }
2844
2845 if (smc->dr_lmb_enabled) {
2846 spapr_create_lmb_dr_connectors(spapr);
2847 }
2848
2849 if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI) == SPAPR_CAP_ON) {
2850 /* Create the error string for live migration blocker */
2851 error_setg(&spapr->fwnmi_migration_blocker,
2852 "A machine check is being handled during migration. The handler"
2853 "may run and log hardware error on the destination");
2854 }
2855
2856 if (mc->nvdimm_supported) {
2857 spapr_create_nvdimm_dr_connectors(spapr);
2858 }
2859
2860 /* Set up RTAS event infrastructure */
2861 spapr_events_init(spapr);
2862
2863 /* Set up the RTC RTAS interfaces */
2864 spapr_rtc_create(spapr);
2865
2866 /* Set up VIO bus */
2867 spapr->vio_bus = spapr_vio_bus_init();
2868
2869 for (i = 0; i < serial_max_hds(); i++) {
2870 if (serial_hd(i)) {
2871 spapr_vty_create(spapr->vio_bus, serial_hd(i));
2872 }
2873 }
2874
2875 /* We always have at least the nvram device on VIO */
2876 spapr_create_nvram(spapr);
2877
2878 /*
2879 * Setup hotplug / dynamic-reconfiguration connectors. top-level
2880 * connectors (described in root DT node's "ibm,drc-types" property)
2881 * are pre-initialized here. additional child connectors (such as
2882 * connectors for a PHBs PCI slots) are added as needed during their
2883 * parent's realization.
2884 */
2885 if (smc->dr_phb_enabled) {
2886 for (i = 0; i < SPAPR_MAX_PHBS; i++) {
2887 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i);
2888 }
2889 }
2890
2891 /* Set up PCI */
2892 spapr_pci_rtas_init();
2893
2894 phb = spapr_create_default_phb();
2895
2896 for (i = 0; i < nb_nics; i++) {
2897 NICInfo *nd = &nd_table[i];
2898
2899 if (!nd->model) {
2900 nd->model = g_strdup("spapr-vlan");
2901 }
2902
2903 if (g_str_equal(nd->model, "spapr-vlan") ||
2904 g_str_equal(nd->model, "ibmveth")) {
2905 spapr_vlan_create(spapr->vio_bus, nd);
2906 } else {
2907 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL);
2908 }
2909 }
2910
2911 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
2912 spapr_vscsi_create(spapr->vio_bus);
2913 }
2914
2915 /* Graphics */
2916 if (spapr_vga_init(phb->bus, &error_fatal)) {
2917 spapr->has_graphics = true;
2918 machine->usb |= defaults_enabled() && !machine->usb_disabled;
2919 }
2920
2921 if (machine->usb) {
2922 if (smc->use_ohci_by_default) {
2923 pci_create_simple(phb->bus, -1, "pci-ohci");
2924 } else {
2925 pci_create_simple(phb->bus, -1, "nec-usb-xhci");
2926 }
2927
2928 if (spapr->has_graphics) {
2929 USBBus *usb_bus = usb_bus_find(-1);
2930
2931 usb_create_simple(usb_bus, "usb-kbd");
2932 usb_create_simple(usb_bus, "usb-mouse");
2933 }
2934 }
2935
2936 if (kernel_filename) {
2937 spapr->kernel_size = load_elf(kernel_filename, NULL,
2938 translate_kernel_address, spapr,
2939 NULL, NULL, NULL, NULL, 1,
2940 PPC_ELF_MACHINE, 0, 0);
2941 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) {
2942 spapr->kernel_size = load_elf(kernel_filename, NULL,
2943 translate_kernel_address, spapr,
2944 NULL, NULL, NULL, NULL, 0,
2945 PPC_ELF_MACHINE, 0, 0);
2946 spapr->kernel_le = spapr->kernel_size > 0;
2947 }
2948 if (spapr->kernel_size < 0) {
2949 error_report("error loading %s: %s", kernel_filename,
2950 load_elf_strerror(spapr->kernel_size));
2951 exit(1);
2952 }
2953
2954 /* load initrd */
2955 if (initrd_filename) {
2956 /* Try to locate the initrd in the gap between the kernel
2957 * and the firmware. Add a bit of space just in case
2958 */
2959 spapr->initrd_base = (spapr->kernel_addr + spapr->kernel_size
2960 + 0x1ffff) & ~0xffff;
2961 spapr->initrd_size = load_image_targphys(initrd_filename,
2962 spapr->initrd_base,
2963 load_limit
2964 - spapr->initrd_base);
2965 if (spapr->initrd_size < 0) {
2966 error_report("could not load initial ram disk '%s'",
2967 initrd_filename);
2968 exit(1);
2969 }
2970 }
2971 }
2972
2973 if (bios_name == NULL) {
2974 bios_name = FW_FILE_NAME;
2975 }
2976 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
2977 if (!filename) {
2978 error_report("Could not find LPAR firmware '%s'", bios_name);
2979 exit(1);
2980 }
2981 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
2982 if (fw_size <= 0) {
2983 error_report("Could not load LPAR firmware '%s'", filename);
2984 exit(1);
2985 }
2986 g_free(filename);
2987
2988 /* FIXME: Should register things through the MachineState's qdev
2989 * interface, this is a legacy from the sPAPREnvironment structure
2990 * which predated MachineState but had a similar function */
2991 vmstate_register(NULL, 0, &vmstate_spapr, spapr);
2992 register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY, 1,
2993 &savevm_htab_handlers, spapr);
2994
2995 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine));
2996
2997 qemu_register_boot_set(spapr_boot_set, spapr);
2998
2999 /*
3000 * Nothing needs to be done to resume a suspended guest because
3001 * suspending does not change the machine state, so no need for
3002 * a ->wakeup method.
3003 */
3004 qemu_register_wakeup_support();
3005
3006 if (kvm_enabled()) {
3007 /* to stop and start vmclock */
3008 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change,
3009 &spapr->tb);
3010
3011 kvmppc_spapr_enable_inkernel_multitce();
3012 }
3013
3014 qemu_cond_init(&spapr->fwnmi_machine_check_interlock_cond);
3015 }
3016
3017 static int spapr_kvm_type(MachineState *machine, const char *vm_type)
3018 {
3019 if (!vm_type) {
3020 return 0;
3021 }
3022
3023 if (!strcmp(vm_type, "HV")) {
3024 return 1;
3025 }
3026
3027 if (!strcmp(vm_type, "PR")) {
3028 return 2;
3029 }
3030
3031 error_report("Unknown kvm-type specified '%s'", vm_type);
3032 exit(1);
3033 }
3034
3035 /*
3036 * Implementation of an interface to adjust firmware path
3037 * for the bootindex property handling.
3038 */
3039 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus,
3040 DeviceState *dev)
3041 {
3042 #define CAST(type, obj, name) \
3043 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
3044 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE);
3045 SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE);
3046 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON);
3047
3048 if (d) {
3049 void *spapr = CAST(void, bus->parent, "spapr-vscsi");
3050 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI);
3051 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE);
3052
3053 if (spapr) {
3054 /*
3055 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
3056 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form
3057 * 0x8000 | (target << 8) | (bus << 5) | lun
3058 * (see the "Logical unit addressing format" table in SAM5)
3059 */
3060 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun;
3061 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
3062 (uint64_t)id << 48);
3063 } else if (virtio) {
3064 /*
3065 * We use SRP luns of the form 01000000 | (target << 8) | lun
3066 * in the top 32 bits of the 64-bit LUN
3067 * Note: the quote above is from SLOF and it is wrong,
3068 * the actual binding is:
3069 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
3070 */
3071 unsigned id = 0x1000000 | (d->id << 16) | d->lun;
3072 if (d->lun >= 256) {
3073 /* Use the LUN "flat space addressing method" */
3074 id |= 0x4000;
3075 }
3076 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
3077 (uint64_t)id << 32);
3078 } else if (usb) {
3079 /*
3080 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
3081 * in the top 32 bits of the 64-bit LUN
3082 */
3083 unsigned usb_port = atoi(usb->port->path);
3084 unsigned id = 0x1000000 | (usb_port << 16) | d->lun;
3085 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
3086 (uint64_t)id << 32);
3087 }
3088 }
3089
3090 /*
3091 * SLOF probes the USB devices, and if it recognizes that the device is a
3092 * storage device, it changes its name to "storage" instead of "usb-host",
3093 * and additionally adds a child node for the SCSI LUN, so the correct
3094 * boot path in SLOF is something like .../storage@1/disk@xxx" instead.
3095 */
3096 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) {
3097 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE);
3098 if (usb_host_dev_is_scsi_storage(usbdev)) {
3099 return g_strdup_printf("storage@%s/disk", usbdev->port->path);
3100 }
3101 }
3102
3103 if (phb) {
3104 /* Replace "pci" with "pci@800000020000000" */
3105 return g_strdup_printf("pci@%"PRIX64, phb->buid);
3106 }
3107
3108 if (vsc) {
3109 /* Same logic as virtio above */
3110 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun;
3111 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32);
3112 }
3113
3114 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) {
3115 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */
3116 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE);
3117 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn));
3118 }
3119
3120 return NULL;
3121 }
3122
3123 static char *spapr_get_kvm_type(Object *obj, Error **errp)
3124 {
3125 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3126
3127 return g_strdup(spapr->kvm_type);
3128 }
3129
3130 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp)
3131 {
3132 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3133
3134 g_free(spapr->kvm_type);
3135 spapr->kvm_type = g_strdup(value);
3136 }
3137
3138 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp)
3139 {
3140 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3141
3142 return spapr->use_hotplug_event_source;
3143 }
3144
3145 static void spapr_set_modern_hotplug_events(Object *obj, bool value,
3146 Error **errp)
3147 {
3148 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3149
3150 spapr->use_hotplug_event_source = value;
3151 }
3152
3153 static bool spapr_get_msix_emulation(Object *obj, Error **errp)
3154 {
3155 return true;
3156 }
3157
3158 static char *spapr_get_resize_hpt(Object *obj, Error **errp)
3159 {
3160 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3161
3162 switch (spapr->resize_hpt) {
3163 case SPAPR_RESIZE_HPT_DEFAULT:
3164 return g_strdup("default");
3165 case SPAPR_RESIZE_HPT_DISABLED:
3166 return g_strdup("disabled");
3167 case SPAPR_RESIZE_HPT_ENABLED:
3168 return g_strdup("enabled");
3169 case SPAPR_RESIZE_HPT_REQUIRED:
3170 return g_strdup("required");
3171 }
3172 g_assert_not_reached();
3173 }
3174
3175 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp)
3176 {
3177 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3178
3179 if (strcmp(value, "default") == 0) {
3180 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT;
3181 } else if (strcmp(value, "disabled") == 0) {
3182 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED;
3183 } else if (strcmp(value, "enabled") == 0) {
3184 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED;
3185 } else if (strcmp(value, "required") == 0) {
3186 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED;
3187 } else {
3188 error_setg(errp, "Bad value for \"resize-hpt\" property");
3189 }
3190 }
3191
3192 static char *spapr_get_ic_mode(Object *obj, Error **errp)
3193 {
3194 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3195
3196 if (spapr->irq == &spapr_irq_xics_legacy) {
3197 return g_strdup("legacy");
3198 } else if (spapr->irq == &spapr_irq_xics) {
3199 return g_strdup("xics");
3200 } else if (spapr->irq == &spapr_irq_xive) {
3201 return g_strdup("xive");
3202 } else if (spapr->irq == &spapr_irq_dual) {
3203 return g_strdup("dual");
3204 }
3205 g_assert_not_reached();
3206 }
3207
3208 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp)
3209 {
3210 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3211
3212 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) {
3213 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode");
3214 return;
3215 }
3216
3217 /* The legacy IRQ backend can not be set */
3218 if (strcmp(value, "xics") == 0) {
3219 spapr->irq = &spapr_irq_xics;
3220 } else if (strcmp(value, "xive") == 0) {
3221 spapr->irq = &spapr_irq_xive;
3222 } else if (strcmp(value, "dual") == 0) {
3223 spapr->irq = &spapr_irq_dual;
3224 } else {
3225 error_setg(errp, "Bad value for \"ic-mode\" property");
3226 }
3227 }
3228
3229 static char *spapr_get_host_model(Object *obj, Error **errp)
3230 {
3231 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3232
3233 return g_strdup(spapr->host_model);
3234 }
3235
3236 static void spapr_set_host_model(Object *obj, const char *value, Error **errp)
3237 {
3238 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3239
3240 g_free(spapr->host_model);
3241 spapr->host_model = g_strdup(value);
3242 }
3243
3244 static char *spapr_get_host_serial(Object *obj, Error **errp)
3245 {
3246 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3247
3248 return g_strdup(spapr->host_serial);
3249 }
3250
3251 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp)
3252 {
3253 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3254
3255 g_free(spapr->host_serial);
3256 spapr->host_serial = g_strdup(value);
3257 }
3258
3259 static void spapr_instance_init(Object *obj)
3260 {
3261 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3262 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
3263
3264 spapr->htab_fd = -1;
3265 spapr->use_hotplug_event_source = true;
3266 object_property_add_str(obj, "kvm-type",
3267 spapr_get_kvm_type, spapr_set_kvm_type);
3268 object_property_set_description(obj, "kvm-type",
3269 "Specifies the KVM virtualization mode (HV, PR)");
3270 object_property_add_bool(obj, "modern-hotplug-events",
3271 spapr_get_modern_hotplug_events,
3272 spapr_set_modern_hotplug_events);
3273 object_property_set_description(obj, "modern-hotplug-events",
3274 "Use dedicated hotplug event mechanism in"
3275 " place of standard EPOW events when possible"
3276 " (required for memory hot-unplug support)");
3277 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr,
3278 "Maximum permitted CPU compatibility mode");
3279
3280 object_property_add_str(obj, "resize-hpt",
3281 spapr_get_resize_hpt, spapr_set_resize_hpt);
3282 object_property_set_description(obj, "resize-hpt",
3283 "Resizing of the Hash Page Table (enabled, disabled, required)");
3284 object_property_add_uint32_ptr(obj, "vsmt",
3285 &spapr->vsmt, OBJ_PROP_FLAG_READWRITE);
3286 object_property_set_description(obj, "vsmt",
3287 "Virtual SMT: KVM behaves as if this were"
3288 " the host's SMT mode");
3289
3290 object_property_add_bool(obj, "vfio-no-msix-emulation",
3291 spapr_get_msix_emulation, NULL);
3292
3293 object_property_add_uint64_ptr(obj, "kernel-addr",
3294 &spapr->kernel_addr, OBJ_PROP_FLAG_READWRITE);
3295 object_property_set_description(obj, "kernel-addr",
3296 stringify(KERNEL_LOAD_ADDR)
3297 " for -kernel is the default");
3298 spapr->kernel_addr = KERNEL_LOAD_ADDR;
3299 /* The machine class defines the default interrupt controller mode */
3300 spapr->irq = smc->irq;
3301 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode,
3302 spapr_set_ic_mode);
3303 object_property_set_description(obj, "ic-mode",
3304 "Specifies the interrupt controller mode (xics, xive, dual)");
3305
3306 object_property_add_str(obj, "host-model",
3307 spapr_get_host_model, spapr_set_host_model);
3308 object_property_set_description(obj, "host-model",
3309 "Host model to advertise in guest device tree");
3310 object_property_add_str(obj, "host-serial",
3311 spapr_get_host_serial, spapr_set_host_serial);
3312 object_property_set_description(obj, "host-serial",
3313 "Host serial number to advertise in guest device tree");
3314 }
3315
3316 static void spapr_machine_finalizefn(Object *obj)
3317 {
3318 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3319
3320 g_free(spapr->kvm_type);
3321 }
3322
3323 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data ar