ppc: add host-serial and host-model machine attributes (CVE-2019-8934)
[qemu.git] / hw / ppc / spapr.c
1 /*
2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
3 *
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 *
26 */
27 #include "qemu/osdep.h"
28 #include "qapi/error.h"
29 #include "qapi/visitor.h"
30 #include "sysemu/sysemu.h"
31 #include "sysemu/numa.h"
32 #include "hw/hw.h"
33 #include "qemu/log.h"
34 #include "hw/fw-path-provider.h"
35 #include "elf.h"
36 #include "net/net.h"
37 #include "sysemu/device_tree.h"
38 #include "sysemu/cpus.h"
39 #include "sysemu/hw_accel.h"
40 #include "kvm_ppc.h"
41 #include "migration/misc.h"
42 #include "migration/global_state.h"
43 #include "migration/register.h"
44 #include "mmu-hash64.h"
45 #include "mmu-book3s-v3.h"
46 #include "cpu-models.h"
47 #include "qom/cpu.h"
48
49 #include "hw/boards.h"
50 #include "hw/ppc/ppc.h"
51 #include "hw/loader.h"
52
53 #include "hw/ppc/fdt.h"
54 #include "hw/ppc/spapr.h"
55 #include "hw/ppc/spapr_vio.h"
56 #include "hw/pci-host/spapr.h"
57 #include "hw/pci/msi.h"
58
59 #include "hw/pci/pci.h"
60 #include "hw/scsi/scsi.h"
61 #include "hw/virtio/virtio-scsi.h"
62 #include "hw/virtio/vhost-scsi-common.h"
63
64 #include "exec/address-spaces.h"
65 #include "exec/ram_addr.h"
66 #include "hw/usb.h"
67 #include "qemu/config-file.h"
68 #include "qemu/error-report.h"
69 #include "trace.h"
70 #include "hw/nmi.h"
71 #include "hw/intc/intc.h"
72
73 #include "qemu/cutils.h"
74 #include "hw/ppc/spapr_cpu_core.h"
75 #include "hw/mem/memory-device.h"
76
77 #include <libfdt.h>
78
79 /* SLOF memory layout:
80 *
81 * SLOF raw image loaded at 0, copies its romfs right below the flat
82 * device-tree, then position SLOF itself 31M below that
83 *
84 * So we set FW_OVERHEAD to 40MB which should account for all of that
85 * and more
86 *
87 * We load our kernel at 4M, leaving space for SLOF initial image
88 */
89 #define FDT_MAX_SIZE 0x100000
90 #define RTAS_MAX_SIZE 0x10000
91 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */
92 #define FW_MAX_SIZE 0x400000
93 #define FW_FILE_NAME "slof.bin"
94 #define FW_OVERHEAD 0x2800000
95 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
96
97 #define MIN_RMA_SLOF 128UL
98
99 #define PHANDLE_INTC 0x00001111
100
101 /* These two functions implement the VCPU id numbering: one to compute them
102 * all and one to identify thread 0 of a VCORE. Any change to the first one
103 * is likely to have an impact on the second one, so let's keep them close.
104 */
105 static int spapr_vcpu_id(sPAPRMachineState *spapr, int cpu_index)
106 {
107 assert(spapr->vsmt);
108 return
109 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads;
110 }
111 static bool spapr_is_thread0_in_vcore(sPAPRMachineState *spapr,
112 PowerPCCPU *cpu)
113 {
114 assert(spapr->vsmt);
115 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0;
116 }
117
118 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque)
119 {
120 /* Dummy entries correspond to unused ICPState objects in older QEMUs,
121 * and newer QEMUs don't even have them. In both cases, we don't want
122 * to send anything on the wire.
123 */
124 return false;
125 }
126
127 static const VMStateDescription pre_2_10_vmstate_dummy_icp = {
128 .name = "icp/server",
129 .version_id = 1,
130 .minimum_version_id = 1,
131 .needed = pre_2_10_vmstate_dummy_icp_needed,
132 .fields = (VMStateField[]) {
133 VMSTATE_UNUSED(4), /* uint32_t xirr */
134 VMSTATE_UNUSED(1), /* uint8_t pending_priority */
135 VMSTATE_UNUSED(1), /* uint8_t mfrr */
136 VMSTATE_END_OF_LIST()
137 },
138 };
139
140 static void pre_2_10_vmstate_register_dummy_icp(int i)
141 {
142 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp,
143 (void *)(uintptr_t) i);
144 }
145
146 static void pre_2_10_vmstate_unregister_dummy_icp(int i)
147 {
148 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp,
149 (void *)(uintptr_t) i);
150 }
151
152 int spapr_max_server_number(sPAPRMachineState *spapr)
153 {
154 assert(spapr->vsmt);
155 return DIV_ROUND_UP(max_cpus * spapr->vsmt, smp_threads);
156 }
157
158 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
159 int smt_threads)
160 {
161 int i, ret = 0;
162 uint32_t servers_prop[smt_threads];
163 uint32_t gservers_prop[smt_threads * 2];
164 int index = spapr_get_vcpu_id(cpu);
165
166 if (cpu->compat_pvr) {
167 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr);
168 if (ret < 0) {
169 return ret;
170 }
171 }
172
173 /* Build interrupt servers and gservers properties */
174 for (i = 0; i < smt_threads; i++) {
175 servers_prop[i] = cpu_to_be32(index + i);
176 /* Hack, direct the group queues back to cpu 0 */
177 gservers_prop[i*2] = cpu_to_be32(index + i);
178 gservers_prop[i*2 + 1] = 0;
179 }
180 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
181 servers_prop, sizeof(servers_prop));
182 if (ret < 0) {
183 return ret;
184 }
185 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s",
186 gservers_prop, sizeof(gservers_prop));
187
188 return ret;
189 }
190
191 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu)
192 {
193 int index = spapr_get_vcpu_id(cpu);
194 uint32_t associativity[] = {cpu_to_be32(0x5),
195 cpu_to_be32(0x0),
196 cpu_to_be32(0x0),
197 cpu_to_be32(0x0),
198 cpu_to_be32(cpu->node_id),
199 cpu_to_be32(index)};
200
201 /* Advertise NUMA via ibm,associativity */
202 return fdt_setprop(fdt, offset, "ibm,associativity", associativity,
203 sizeof(associativity));
204 }
205
206 /* Populate the "ibm,pa-features" property */
207 static void spapr_populate_pa_features(sPAPRMachineState *spapr,
208 PowerPCCPU *cpu,
209 void *fdt, int offset,
210 bool legacy_guest)
211 {
212 uint8_t pa_features_206[] = { 6, 0,
213 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
214 uint8_t pa_features_207[] = { 24, 0,
215 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
216 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
217 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
218 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
219 uint8_t pa_features_300[] = { 66, 0,
220 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
221 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */
222 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */
223 /* 6: DS207 */
224 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
225 /* 16: Vector */
226 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
227 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */
228 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
229 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
230 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
231 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */
232 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
233 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */
234 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */
235 /* 42: PM, 44: PC RA, 46: SC vec'd */
236 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
237 /* 48: SIMD, 50: QP BFP, 52: String */
238 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
239 /* 54: DecFP, 56: DecI, 58: SHA */
240 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
241 /* 60: NM atomic, 62: RNG */
242 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
243 };
244 uint8_t *pa_features = NULL;
245 size_t pa_size;
246
247 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) {
248 pa_features = pa_features_206;
249 pa_size = sizeof(pa_features_206);
250 }
251 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) {
252 pa_features = pa_features_207;
253 pa_size = sizeof(pa_features_207);
254 }
255 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) {
256 pa_features = pa_features_300;
257 pa_size = sizeof(pa_features_300);
258 }
259 if (!pa_features) {
260 return;
261 }
262
263 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) {
264 /*
265 * Note: we keep CI large pages off by default because a 64K capable
266 * guest provisioned with large pages might otherwise try to map a qemu
267 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
268 * even if that qemu runs on a 4k host.
269 * We dd this bit back here if we are confident this is not an issue
270 */
271 pa_features[3] |= 0x20;
272 }
273 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) {
274 pa_features[24] |= 0x80; /* Transactional memory support */
275 }
276 if (legacy_guest && pa_size > 40) {
277 /* Workaround for broken kernels that attempt (guest) radix
278 * mode when they can't handle it, if they see the radix bit set
279 * in pa-features. So hide it from them. */
280 pa_features[40 + 2] &= ~0x80; /* Radix MMU */
281 }
282
283 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size)));
284 }
285
286 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr)
287 {
288 int ret = 0, offset, cpus_offset;
289 CPUState *cs;
290 char cpu_model[32];
291 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
292
293 CPU_FOREACH(cs) {
294 PowerPCCPU *cpu = POWERPC_CPU(cs);
295 DeviceClass *dc = DEVICE_GET_CLASS(cs);
296 int index = spapr_get_vcpu_id(cpu);
297 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu));
298
299 if (!spapr_is_thread0_in_vcore(spapr, cpu)) {
300 continue;
301 }
302
303 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index);
304
305 cpus_offset = fdt_path_offset(fdt, "/cpus");
306 if (cpus_offset < 0) {
307 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
308 if (cpus_offset < 0) {
309 return cpus_offset;
310 }
311 }
312 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model);
313 if (offset < 0) {
314 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model);
315 if (offset < 0) {
316 return offset;
317 }
318 }
319
320 ret = fdt_setprop(fdt, offset, "ibm,pft-size",
321 pft_size_prop, sizeof(pft_size_prop));
322 if (ret < 0) {
323 return ret;
324 }
325
326 if (nb_numa_nodes > 1) {
327 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cpu);
328 if (ret < 0) {
329 return ret;
330 }
331 }
332
333 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt);
334 if (ret < 0) {
335 return ret;
336 }
337
338 spapr_populate_pa_features(spapr, cpu, fdt, offset,
339 spapr->cas_legacy_guest_workaround);
340 }
341 return ret;
342 }
343
344 static hwaddr spapr_node0_size(MachineState *machine)
345 {
346 if (nb_numa_nodes) {
347 int i;
348 for (i = 0; i < nb_numa_nodes; ++i) {
349 if (numa_info[i].node_mem) {
350 return MIN(pow2floor(numa_info[i].node_mem),
351 machine->ram_size);
352 }
353 }
354 }
355 return machine->ram_size;
356 }
357
358 static void add_str(GString *s, const gchar *s1)
359 {
360 g_string_append_len(s, s1, strlen(s1) + 1);
361 }
362
363 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start,
364 hwaddr size)
365 {
366 uint32_t associativity[] = {
367 cpu_to_be32(0x4), /* length */
368 cpu_to_be32(0x0), cpu_to_be32(0x0),
369 cpu_to_be32(0x0), cpu_to_be32(nodeid)
370 };
371 char mem_name[32];
372 uint64_t mem_reg_property[2];
373 int off;
374
375 mem_reg_property[0] = cpu_to_be64(start);
376 mem_reg_property[1] = cpu_to_be64(size);
377
378 sprintf(mem_name, "memory@" TARGET_FMT_lx, start);
379 off = fdt_add_subnode(fdt, 0, mem_name);
380 _FDT(off);
381 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
382 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
383 sizeof(mem_reg_property))));
384 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
385 sizeof(associativity))));
386 return off;
387 }
388
389 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt)
390 {
391 MachineState *machine = MACHINE(spapr);
392 hwaddr mem_start, node_size;
393 int i, nb_nodes = nb_numa_nodes;
394 NodeInfo *nodes = numa_info;
395 NodeInfo ramnode;
396
397 /* No NUMA nodes, assume there is just one node with whole RAM */
398 if (!nb_numa_nodes) {
399 nb_nodes = 1;
400 ramnode.node_mem = machine->ram_size;
401 nodes = &ramnode;
402 }
403
404 for (i = 0, mem_start = 0; i < nb_nodes; ++i) {
405 if (!nodes[i].node_mem) {
406 continue;
407 }
408 if (mem_start >= machine->ram_size) {
409 node_size = 0;
410 } else {
411 node_size = nodes[i].node_mem;
412 if (node_size > machine->ram_size - mem_start) {
413 node_size = machine->ram_size - mem_start;
414 }
415 }
416 if (!mem_start) {
417 /* spapr_machine_init() checks for rma_size <= node0_size
418 * already */
419 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size);
420 mem_start += spapr->rma_size;
421 node_size -= spapr->rma_size;
422 }
423 for ( ; node_size; ) {
424 hwaddr sizetmp = pow2floor(node_size);
425
426 /* mem_start != 0 here */
427 if (ctzl(mem_start) < ctzl(sizetmp)) {
428 sizetmp = 1ULL << ctzl(mem_start);
429 }
430
431 spapr_populate_memory_node(fdt, i, mem_start, sizetmp);
432 node_size -= sizetmp;
433 mem_start += sizetmp;
434 }
435 }
436
437 return 0;
438 }
439
440 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
441 sPAPRMachineState *spapr)
442 {
443 PowerPCCPU *cpu = POWERPC_CPU(cs);
444 CPUPPCState *env = &cpu->env;
445 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
446 int index = spapr_get_vcpu_id(cpu);
447 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
448 0xffffffff, 0xffffffff};
449 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq()
450 : SPAPR_TIMEBASE_FREQ;
451 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
452 uint32_t page_sizes_prop[64];
453 size_t page_sizes_prop_size;
454 uint32_t vcpus_per_socket = smp_threads * smp_cores;
455 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
456 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu));
457 sPAPRDRConnector *drc;
458 int drc_index;
459 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ];
460 int i;
461
462 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index);
463 if (drc) {
464 drc_index = spapr_drc_index(drc);
465 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)));
466 }
467
468 _FDT((fdt_setprop_cell(fdt, offset, "reg", index)));
469 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
470
471 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
472 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
473 env->dcache_line_size)));
474 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
475 env->dcache_line_size)));
476 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
477 env->icache_line_size)));
478 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
479 env->icache_line_size)));
480
481 if (pcc->l1_dcache_size) {
482 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
483 pcc->l1_dcache_size)));
484 } else {
485 warn_report("Unknown L1 dcache size for cpu");
486 }
487 if (pcc->l1_icache_size) {
488 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
489 pcc->l1_icache_size)));
490 } else {
491 warn_report("Unknown L1 icache size for cpu");
492 }
493
494 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
495 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
496 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size)));
497 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size)));
498 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
499 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
500
501 if (env->spr_cb[SPR_PURR].oea_read) {
502 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
503 }
504
505 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) {
506 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
507 segs, sizeof(segs))));
508 }
509
510 /* Advertise VSX (vector extensions) if available
511 * 1 == VMX / Altivec available
512 * 2 == VSX available
513 *
514 * Only CPUs for which we create core types in spapr_cpu_core.c
515 * are possible, and all of those have VMX */
516 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) {
517 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2)));
518 } else {
519 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1)));
520 }
521
522 /* Advertise DFP (Decimal Floating Point) if available
523 * 0 / no property == no DFP
524 * 1 == DFP available */
525 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) {
526 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
527 }
528
529 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop,
530 sizeof(page_sizes_prop));
531 if (page_sizes_prop_size) {
532 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
533 page_sizes_prop, page_sizes_prop_size)));
534 }
535
536 spapr_populate_pa_features(spapr, cpu, fdt, offset, false);
537
538 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
539 cs->cpu_index / vcpus_per_socket)));
540
541 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size",
542 pft_size_prop, sizeof(pft_size_prop))));
543
544 if (nb_numa_nodes > 1) {
545 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu));
546 }
547
548 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt));
549
550 if (pcc->radix_page_info) {
551 for (i = 0; i < pcc->radix_page_info->count; i++) {
552 radix_AP_encodings[i] =
553 cpu_to_be32(pcc->radix_page_info->entries[i]);
554 }
555 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings",
556 radix_AP_encodings,
557 pcc->radix_page_info->count *
558 sizeof(radix_AP_encodings[0]))));
559 }
560 }
561
562 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr)
563 {
564 CPUState **rev;
565 CPUState *cs;
566 int n_cpus;
567 int cpus_offset;
568 char *nodename;
569 int i;
570
571 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
572 _FDT(cpus_offset);
573 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
574 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
575
576 /*
577 * We walk the CPUs in reverse order to ensure that CPU DT nodes
578 * created by fdt_add_subnode() end up in the right order in FDT
579 * for the guest kernel the enumerate the CPUs correctly.
580 *
581 * The CPU list cannot be traversed in reverse order, so we need
582 * to do extra work.
583 */
584 n_cpus = 0;
585 rev = NULL;
586 CPU_FOREACH(cs) {
587 rev = g_renew(CPUState *, rev, n_cpus + 1);
588 rev[n_cpus++] = cs;
589 }
590
591 for (i = n_cpus - 1; i >= 0; i--) {
592 CPUState *cs = rev[i];
593 PowerPCCPU *cpu = POWERPC_CPU(cs);
594 int index = spapr_get_vcpu_id(cpu);
595 DeviceClass *dc = DEVICE_GET_CLASS(cs);
596 int offset;
597
598 if (!spapr_is_thread0_in_vcore(spapr, cpu)) {
599 continue;
600 }
601
602 nodename = g_strdup_printf("%s@%x", dc->fw_name, index);
603 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
604 g_free(nodename);
605 _FDT(offset);
606 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
607 }
608
609 g_free(rev);
610 }
611
612 static int spapr_rng_populate_dt(void *fdt)
613 {
614 int node;
615 int ret;
616
617 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities");
618 if (node <= 0) {
619 return -1;
620 }
621 ret = fdt_setprop_string(fdt, node, "device_type",
622 "ibm,platform-facilities");
623 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1);
624 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0);
625
626 node = fdt_add_subnode(fdt, node, "ibm,random-v1");
627 if (node <= 0) {
628 return -1;
629 }
630 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random");
631
632 return ret ? -1 : 0;
633 }
634
635 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr)
636 {
637 MemoryDeviceInfoList *info;
638
639 for (info = list; info; info = info->next) {
640 MemoryDeviceInfo *value = info->value;
641
642 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) {
643 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data;
644
645 if (addr >= pcdimm_info->addr &&
646 addr < (pcdimm_info->addr + pcdimm_info->size)) {
647 return pcdimm_info->node;
648 }
649 }
650 }
651
652 return -1;
653 }
654
655 struct sPAPRDrconfCellV2 {
656 uint32_t seq_lmbs;
657 uint64_t base_addr;
658 uint32_t drc_index;
659 uint32_t aa_index;
660 uint32_t flags;
661 } QEMU_PACKED;
662
663 typedef struct DrconfCellQueue {
664 struct sPAPRDrconfCellV2 cell;
665 QSIMPLEQ_ENTRY(DrconfCellQueue) entry;
666 } DrconfCellQueue;
667
668 static DrconfCellQueue *
669 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr,
670 uint32_t drc_index, uint32_t aa_index,
671 uint32_t flags)
672 {
673 DrconfCellQueue *elem;
674
675 elem = g_malloc0(sizeof(*elem));
676 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs);
677 elem->cell.base_addr = cpu_to_be64(base_addr);
678 elem->cell.drc_index = cpu_to_be32(drc_index);
679 elem->cell.aa_index = cpu_to_be32(aa_index);
680 elem->cell.flags = cpu_to_be32(flags);
681
682 return elem;
683 }
684
685 /* ibm,dynamic-memory-v2 */
686 static int spapr_populate_drmem_v2(sPAPRMachineState *spapr, void *fdt,
687 int offset, MemoryDeviceInfoList *dimms)
688 {
689 MachineState *machine = MACHINE(spapr);
690 uint8_t *int_buf, *cur_index;
691 int ret;
692 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
693 uint64_t addr, cur_addr, size;
694 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size);
695 uint64_t mem_end = machine->device_memory->base +
696 memory_region_size(&machine->device_memory->mr);
697 uint32_t node, buf_len, nr_entries = 0;
698 sPAPRDRConnector *drc;
699 DrconfCellQueue *elem, *next;
700 MemoryDeviceInfoList *info;
701 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue
702 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue);
703
704 /* Entry to cover RAM and the gap area */
705 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1,
706 SPAPR_LMB_FLAGS_RESERVED |
707 SPAPR_LMB_FLAGS_DRC_INVALID);
708 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
709 nr_entries++;
710
711 cur_addr = machine->device_memory->base;
712 for (info = dimms; info; info = info->next) {
713 PCDIMMDeviceInfo *di = info->value->u.dimm.data;
714
715 addr = di->addr;
716 size = di->size;
717 node = di->node;
718
719 /* Entry for hot-pluggable area */
720 if (cur_addr < addr) {
721 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size);
722 g_assert(drc);
723 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size,
724 cur_addr, spapr_drc_index(drc), -1, 0);
725 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
726 nr_entries++;
727 }
728
729 /* Entry for DIMM */
730 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size);
731 g_assert(drc);
732 elem = spapr_get_drconf_cell(size / lmb_size, addr,
733 spapr_drc_index(drc), node,
734 SPAPR_LMB_FLAGS_ASSIGNED);
735 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
736 nr_entries++;
737 cur_addr = addr + size;
738 }
739
740 /* Entry for remaining hotpluggable area */
741 if (cur_addr < mem_end) {
742 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size);
743 g_assert(drc);
744 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size,
745 cur_addr, spapr_drc_index(drc), -1, 0);
746 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
747 nr_entries++;
748 }
749
750 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t);
751 int_buf = cur_index = g_malloc0(buf_len);
752 *(uint32_t *)int_buf = cpu_to_be32(nr_entries);
753 cur_index += sizeof(nr_entries);
754
755 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) {
756 memcpy(cur_index, &elem->cell, sizeof(elem->cell));
757 cur_index += sizeof(elem->cell);
758 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry);
759 g_free(elem);
760 }
761
762 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len);
763 g_free(int_buf);
764 if (ret < 0) {
765 return -1;
766 }
767 return 0;
768 }
769
770 /* ibm,dynamic-memory */
771 static int spapr_populate_drmem_v1(sPAPRMachineState *spapr, void *fdt,
772 int offset, MemoryDeviceInfoList *dimms)
773 {
774 MachineState *machine = MACHINE(spapr);
775 int i, ret;
776 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
777 uint32_t device_lmb_start = machine->device_memory->base / lmb_size;
778 uint32_t nr_lmbs = (machine->device_memory->base +
779 memory_region_size(&machine->device_memory->mr)) /
780 lmb_size;
781 uint32_t *int_buf, *cur_index, buf_len;
782
783 /*
784 * Allocate enough buffer size to fit in ibm,dynamic-memory
785 */
786 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t);
787 cur_index = int_buf = g_malloc0(buf_len);
788 int_buf[0] = cpu_to_be32(nr_lmbs);
789 cur_index++;
790 for (i = 0; i < nr_lmbs; i++) {
791 uint64_t addr = i * lmb_size;
792 uint32_t *dynamic_memory = cur_index;
793
794 if (i >= device_lmb_start) {
795 sPAPRDRConnector *drc;
796
797 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i);
798 g_assert(drc);
799
800 dynamic_memory[0] = cpu_to_be32(addr >> 32);
801 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
802 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc));
803 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
804 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr));
805 if (memory_region_present(get_system_memory(), addr)) {
806 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED);
807 } else {
808 dynamic_memory[5] = cpu_to_be32(0);
809 }
810 } else {
811 /*
812 * LMB information for RMA, boot time RAM and gap b/n RAM and
813 * device memory region -- all these are marked as reserved
814 * and as having no valid DRC.
815 */
816 dynamic_memory[0] = cpu_to_be32(addr >> 32);
817 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
818 dynamic_memory[2] = cpu_to_be32(0);
819 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
820 dynamic_memory[4] = cpu_to_be32(-1);
821 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED |
822 SPAPR_LMB_FLAGS_DRC_INVALID);
823 }
824
825 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE;
826 }
827 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len);
828 g_free(int_buf);
829 if (ret < 0) {
830 return -1;
831 }
832 return 0;
833 }
834
835 /*
836 * Adds ibm,dynamic-reconfiguration-memory node.
837 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
838 * of this device tree node.
839 */
840 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt)
841 {
842 MachineState *machine = MACHINE(spapr);
843 int ret, i, offset;
844 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
845 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)};
846 uint32_t *int_buf, *cur_index, buf_len;
847 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1;
848 MemoryDeviceInfoList *dimms = NULL;
849
850 /*
851 * Don't create the node if there is no device memory
852 */
853 if (machine->ram_size == machine->maxram_size) {
854 return 0;
855 }
856
857 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory");
858
859 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size,
860 sizeof(prop_lmb_size));
861 if (ret < 0) {
862 return ret;
863 }
864
865 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff);
866 if (ret < 0) {
867 return ret;
868 }
869
870 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0);
871 if (ret < 0) {
872 return ret;
873 }
874
875 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */
876 dimms = qmp_memory_device_list();
877 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) {
878 ret = spapr_populate_drmem_v2(spapr, fdt, offset, dimms);
879 } else {
880 ret = spapr_populate_drmem_v1(spapr, fdt, offset, dimms);
881 }
882 qapi_free_MemoryDeviceInfoList(dimms);
883
884 if (ret < 0) {
885 return ret;
886 }
887
888 /* ibm,associativity-lookup-arrays */
889 buf_len = (nr_nodes * 4 + 2) * sizeof(uint32_t);
890 cur_index = int_buf = g_malloc0(buf_len);
891 int_buf[0] = cpu_to_be32(nr_nodes);
892 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */
893 cur_index += 2;
894 for (i = 0; i < nr_nodes; i++) {
895 uint32_t associativity[] = {
896 cpu_to_be32(0x0),
897 cpu_to_be32(0x0),
898 cpu_to_be32(0x0),
899 cpu_to_be32(i)
900 };
901 memcpy(cur_index, associativity, sizeof(associativity));
902 cur_index += 4;
903 }
904 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf,
905 (cur_index - int_buf) * sizeof(uint32_t));
906 g_free(int_buf);
907
908 return ret;
909 }
910
911 static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt,
912 sPAPROptionVector *ov5_updates)
913 {
914 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
915 int ret = 0, offset;
916
917 /* Generate ibm,dynamic-reconfiguration-memory node if required */
918 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) {
919 g_assert(smc->dr_lmb_enabled);
920 ret = spapr_populate_drconf_memory(spapr, fdt);
921 if (ret) {
922 goto out;
923 }
924 }
925
926 offset = fdt_path_offset(fdt, "/chosen");
927 if (offset < 0) {
928 offset = fdt_add_subnode(fdt, 0, "chosen");
929 if (offset < 0) {
930 return offset;
931 }
932 }
933 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas,
934 "ibm,architecture-vec-5");
935
936 out:
937 return ret;
938 }
939
940 static bool spapr_hotplugged_dev_before_cas(void)
941 {
942 Object *drc_container, *obj;
943 ObjectProperty *prop;
944 ObjectPropertyIterator iter;
945
946 drc_container = container_get(object_get_root(), "/dr-connector");
947 object_property_iter_init(&iter, drc_container);
948 while ((prop = object_property_iter_next(&iter))) {
949 if (!strstart(prop->type, "link<", NULL)) {
950 continue;
951 }
952 obj = object_property_get_link(drc_container, prop->name, NULL);
953 if (spapr_drc_needed(obj)) {
954 return true;
955 }
956 }
957 return false;
958 }
959
960 int spapr_h_cas_compose_response(sPAPRMachineState *spapr,
961 target_ulong addr, target_ulong size,
962 sPAPROptionVector *ov5_updates)
963 {
964 void *fdt, *fdt_skel;
965 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 };
966
967 if (spapr_hotplugged_dev_before_cas()) {
968 return 1;
969 }
970
971 if (size < sizeof(hdr) || size > FW_MAX_SIZE) {
972 error_report("SLOF provided an unexpected CAS buffer size "
973 TARGET_FMT_lu " (min: %zu, max: %u)",
974 size, sizeof(hdr), FW_MAX_SIZE);
975 exit(EXIT_FAILURE);
976 }
977
978 size -= sizeof(hdr);
979
980 /* Create skeleton */
981 fdt_skel = g_malloc0(size);
982 _FDT((fdt_create(fdt_skel, size)));
983 _FDT((fdt_finish_reservemap(fdt_skel)));
984 _FDT((fdt_begin_node(fdt_skel, "")));
985 _FDT((fdt_end_node(fdt_skel)));
986 _FDT((fdt_finish(fdt_skel)));
987 fdt = g_malloc0(size);
988 _FDT((fdt_open_into(fdt_skel, fdt, size)));
989 g_free(fdt_skel);
990
991 /* Fixup cpu nodes */
992 _FDT((spapr_fixup_cpu_dt(fdt, spapr)));
993
994 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) {
995 return -1;
996 }
997
998 /* Pack resulting tree */
999 _FDT((fdt_pack(fdt)));
1000
1001 if (fdt_totalsize(fdt) + sizeof(hdr) > size) {
1002 trace_spapr_cas_failed(size);
1003 return -1;
1004 }
1005
1006 cpu_physical_memory_write(addr, &hdr, sizeof(hdr));
1007 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt));
1008 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr));
1009 g_free(fdt);
1010
1011 return 0;
1012 }
1013
1014 static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt)
1015 {
1016 int rtas;
1017 GString *hypertas = g_string_sized_new(256);
1018 GString *qemu_hypertas = g_string_sized_new(256);
1019 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) };
1020 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base +
1021 memory_region_size(&MACHINE(spapr)->device_memory->mr);
1022 uint32_t lrdr_capacity[] = {
1023 cpu_to_be32(max_device_addr >> 32),
1024 cpu_to_be32(max_device_addr & 0xffffffff),
1025 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE),
1026 cpu_to_be32(max_cpus / smp_threads),
1027 };
1028 uint32_t maxdomains[] = {
1029 cpu_to_be32(4),
1030 cpu_to_be32(0),
1031 cpu_to_be32(0),
1032 cpu_to_be32(0),
1033 cpu_to_be32(nb_numa_nodes ? nb_numa_nodes : 1),
1034 };
1035
1036 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas"));
1037
1038 /* hypertas */
1039 add_str(hypertas, "hcall-pft");
1040 add_str(hypertas, "hcall-term");
1041 add_str(hypertas, "hcall-dabr");
1042 add_str(hypertas, "hcall-interrupt");
1043 add_str(hypertas, "hcall-tce");
1044 add_str(hypertas, "hcall-vio");
1045 add_str(hypertas, "hcall-splpar");
1046 add_str(hypertas, "hcall-bulk");
1047 add_str(hypertas, "hcall-set-mode");
1048 add_str(hypertas, "hcall-sprg0");
1049 add_str(hypertas, "hcall-copy");
1050 add_str(hypertas, "hcall-debug");
1051 add_str(hypertas, "hcall-vphn");
1052 add_str(qemu_hypertas, "hcall-memop1");
1053
1054 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
1055 add_str(hypertas, "hcall-multi-tce");
1056 }
1057
1058 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) {
1059 add_str(hypertas, "hcall-hpt-resize");
1060 }
1061
1062 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions",
1063 hypertas->str, hypertas->len));
1064 g_string_free(hypertas, TRUE);
1065 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions",
1066 qemu_hypertas->str, qemu_hypertas->len));
1067 g_string_free(qemu_hypertas, TRUE);
1068
1069 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points",
1070 refpoints, sizeof(refpoints)));
1071
1072 _FDT(fdt_setprop(fdt, rtas, "ibm,max-associativity-domains",
1073 maxdomains, sizeof(maxdomains)));
1074
1075 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max",
1076 RTAS_ERROR_LOG_MAX));
1077 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate",
1078 RTAS_EVENT_SCAN_RATE));
1079
1080 g_assert(msi_nonbroken);
1081 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0));
1082
1083 /*
1084 * According to PAPR, rtas ibm,os-term does not guarantee a return
1085 * back to the guest cpu.
1086 *
1087 * While an additional ibm,extended-os-term property indicates
1088 * that rtas call return will always occur. Set this property.
1089 */
1090 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0));
1091
1092 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity",
1093 lrdr_capacity, sizeof(lrdr_capacity)));
1094
1095 spapr_dt_rtas_tokens(fdt, rtas);
1096 }
1097
1098 /*
1099 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU
1100 * and the XIVE features that the guest may request and thus the valid
1101 * values for bytes 23..26 of option vector 5:
1102 */
1103 static void spapr_dt_ov5_platform_support(sPAPRMachineState *spapr, void *fdt,
1104 int chosen)
1105 {
1106 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu);
1107
1108 char val[2 * 4] = {
1109 23, spapr->irq->ov5, /* Xive mode. */
1110 24, 0x00, /* Hash/Radix, filled in below. */
1111 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */
1112 26, 0x40, /* Radix options: GTSE == yes. */
1113 };
1114
1115 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0,
1116 first_ppc_cpu->compat_pvr)) {
1117 /*
1118 * If we're in a pre POWER9 compat mode then the guest should
1119 * do hash and use the legacy interrupt mode
1120 */
1121 val[1] = 0x00; /* XICS */
1122 val[3] = 0x00; /* Hash */
1123 } else if (kvm_enabled()) {
1124 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) {
1125 val[3] = 0x80; /* OV5_MMU_BOTH */
1126 } else if (kvmppc_has_cap_mmu_radix()) {
1127 val[3] = 0x40; /* OV5_MMU_RADIX_300 */
1128 } else {
1129 val[3] = 0x00; /* Hash */
1130 }
1131 } else {
1132 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */
1133 val[3] = 0xC0;
1134 }
1135 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support",
1136 val, sizeof(val)));
1137 }
1138
1139 static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt)
1140 {
1141 MachineState *machine = MACHINE(spapr);
1142 int chosen;
1143 const char *boot_device = machine->boot_order;
1144 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus);
1145 size_t cb = 0;
1146 char *bootlist = get_boot_devices_list(&cb);
1147
1148 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen"));
1149
1150 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline));
1151 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start",
1152 spapr->initrd_base));
1153 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end",
1154 spapr->initrd_base + spapr->initrd_size));
1155
1156 if (spapr->kernel_size) {
1157 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR),
1158 cpu_to_be64(spapr->kernel_size) };
1159
1160 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel",
1161 &kprop, sizeof(kprop)));
1162 if (spapr->kernel_le) {
1163 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0));
1164 }
1165 }
1166 if (boot_menu) {
1167 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu)));
1168 }
1169 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width));
1170 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height));
1171 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth));
1172
1173 if (cb && bootlist) {
1174 int i;
1175
1176 for (i = 0; i < cb; i++) {
1177 if (bootlist[i] == '\n') {
1178 bootlist[i] = ' ';
1179 }
1180 }
1181 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist));
1182 }
1183
1184 if (boot_device && strlen(boot_device)) {
1185 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device));
1186 }
1187
1188 if (!spapr->has_graphics && stdout_path) {
1189 /*
1190 * "linux,stdout-path" and "stdout" properties are deprecated by linux
1191 * kernel. New platforms should only use the "stdout-path" property. Set
1192 * the new property and continue using older property to remain
1193 * compatible with the existing firmware.
1194 */
1195 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path));
1196 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path));
1197 }
1198
1199 spapr_dt_ov5_platform_support(spapr, fdt, chosen);
1200
1201 g_free(stdout_path);
1202 g_free(bootlist);
1203 }
1204
1205 static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt)
1206 {
1207 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR
1208 * KVM to work under pHyp with some guest co-operation */
1209 int hypervisor;
1210 uint8_t hypercall[16];
1211
1212 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor"));
1213 /* indicate KVM hypercall interface */
1214 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm"));
1215 if (kvmppc_has_cap_fixup_hcalls()) {
1216 /*
1217 * Older KVM versions with older guest kernels were broken
1218 * with the magic page, don't allow the guest to map it.
1219 */
1220 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall,
1221 sizeof(hypercall))) {
1222 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions",
1223 hypercall, sizeof(hypercall)));
1224 }
1225 }
1226 }
1227
1228 static void *spapr_build_fdt(sPAPRMachineState *spapr)
1229 {
1230 MachineState *machine = MACHINE(spapr);
1231 MachineClass *mc = MACHINE_GET_CLASS(machine);
1232 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
1233 int ret;
1234 void *fdt;
1235 sPAPRPHBState *phb;
1236 char *buf;
1237
1238 fdt = g_malloc0(FDT_MAX_SIZE);
1239 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
1240
1241 /* Root node */
1242 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp"));
1243 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)"));
1244 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries"));
1245
1246 /*
1247 * Add info to guest to indentify which host is it being run on
1248 * and what is the uuid of the guest
1249 */
1250 if (spapr->host_model && !g_str_equal(spapr->host_model, "none")) {
1251 if (g_str_equal(spapr->host_model, "passthrough")) {
1252 /* -M host-model=passthrough */
1253 if (kvmppc_get_host_model(&buf)) {
1254 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf));
1255 g_free(buf);
1256 }
1257 } else {
1258 /* -M host-model=<user-string> */
1259 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model));
1260 }
1261 }
1262
1263 if (spapr->host_serial && !g_str_equal(spapr->host_serial, "none")) {
1264 if (g_str_equal(spapr->host_serial, "passthrough")) {
1265 /* -M host-serial=passthrough */
1266 if (kvmppc_get_host_serial(&buf)) {
1267 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf));
1268 g_free(buf);
1269 }
1270 } else {
1271 /* -M host-serial=<user-string> */
1272 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial));
1273 }
1274 }
1275
1276 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
1277
1278 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf));
1279 if (qemu_uuid_set) {
1280 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf));
1281 }
1282 g_free(buf);
1283
1284 if (qemu_get_vm_name()) {
1285 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name",
1286 qemu_get_vm_name()));
1287 }
1288
1289 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2));
1290 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2));
1291
1292 /* /interrupt controller */
1293 spapr->irq->dt_populate(spapr, spapr_max_server_number(spapr), fdt,
1294 PHANDLE_INTC);
1295
1296 ret = spapr_populate_memory(spapr, fdt);
1297 if (ret < 0) {
1298 error_report("couldn't setup memory nodes in fdt");
1299 exit(1);
1300 }
1301
1302 /* /vdevice */
1303 spapr_dt_vdevice(spapr->vio_bus, fdt);
1304
1305 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) {
1306 ret = spapr_rng_populate_dt(fdt);
1307 if (ret < 0) {
1308 error_report("could not set up rng device in the fdt");
1309 exit(1);
1310 }
1311 }
1312
1313 QLIST_FOREACH(phb, &spapr->phbs, list) {
1314 ret = spapr_populate_pci_dt(phb, PHANDLE_INTC, fdt,
1315 spapr->irq->nr_msis);
1316 if (ret < 0) {
1317 error_report("couldn't setup PCI devices in fdt");
1318 exit(1);
1319 }
1320 }
1321
1322 /* cpus */
1323 spapr_populate_cpus_dt_node(fdt, spapr);
1324
1325 if (smc->dr_lmb_enabled) {
1326 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB));
1327 }
1328
1329 if (mc->has_hotpluggable_cpus) {
1330 int offset = fdt_path_offset(fdt, "/cpus");
1331 ret = spapr_drc_populate_dt(fdt, offset, NULL,
1332 SPAPR_DR_CONNECTOR_TYPE_CPU);
1333 if (ret < 0) {
1334 error_report("Couldn't set up CPU DR device tree properties");
1335 exit(1);
1336 }
1337 }
1338
1339 /* /event-sources */
1340 spapr_dt_events(spapr, fdt);
1341
1342 /* /rtas */
1343 spapr_dt_rtas(spapr, fdt);
1344
1345 /* /chosen */
1346 spapr_dt_chosen(spapr, fdt);
1347
1348 /* /hypervisor */
1349 if (kvm_enabled()) {
1350 spapr_dt_hypervisor(spapr, fdt);
1351 }
1352
1353 /* Build memory reserve map */
1354 if (spapr->kernel_size) {
1355 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size)));
1356 }
1357 if (spapr->initrd_size) {
1358 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size)));
1359 }
1360
1361 /* ibm,client-architecture-support updates */
1362 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas);
1363 if (ret < 0) {
1364 error_report("couldn't setup CAS properties fdt");
1365 exit(1);
1366 }
1367
1368 return fdt;
1369 }
1370
1371 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
1372 {
1373 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
1374 }
1375
1376 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp,
1377 PowerPCCPU *cpu)
1378 {
1379 CPUPPCState *env = &cpu->env;
1380
1381 /* The TCG path should also be holding the BQL at this point */
1382 g_assert(qemu_mutex_iothread_locked());
1383
1384 if (msr_pr) {
1385 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1386 env->gpr[3] = H_PRIVILEGE;
1387 } else {
1388 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]);
1389 }
1390 }
1391
1392 static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp)
1393 {
1394 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1395
1396 return spapr->patb_entry;
1397 }
1398
1399 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1400 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1401 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1402 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1403 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1404
1405 /*
1406 * Get the fd to access the kernel htab, re-opening it if necessary
1407 */
1408 static int get_htab_fd(sPAPRMachineState *spapr)
1409 {
1410 Error *local_err = NULL;
1411
1412 if (spapr->htab_fd >= 0) {
1413 return spapr->htab_fd;
1414 }
1415
1416 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err);
1417 if (spapr->htab_fd < 0) {
1418 error_report_err(local_err);
1419 }
1420
1421 return spapr->htab_fd;
1422 }
1423
1424 void close_htab_fd(sPAPRMachineState *spapr)
1425 {
1426 if (spapr->htab_fd >= 0) {
1427 close(spapr->htab_fd);
1428 }
1429 spapr->htab_fd = -1;
1430 }
1431
1432 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp)
1433 {
1434 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1435
1436 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1;
1437 }
1438
1439 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp)
1440 {
1441 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1442
1443 assert(kvm_enabled());
1444
1445 if (!spapr->htab) {
1446 return 0;
1447 }
1448
1449 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18);
1450 }
1451
1452 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp,
1453 hwaddr ptex, int n)
1454 {
1455 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1456 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64;
1457
1458 if (!spapr->htab) {
1459 /*
1460 * HTAB is controlled by KVM. Fetch into temporary buffer
1461 */
1462 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64);
1463 kvmppc_read_hptes(hptes, ptex, n);
1464 return hptes;
1465 }
1466
1467 /*
1468 * HTAB is controlled by QEMU. Just point to the internally
1469 * accessible PTEG.
1470 */
1471 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset);
1472 }
1473
1474 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp,
1475 const ppc_hash_pte64_t *hptes,
1476 hwaddr ptex, int n)
1477 {
1478 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1479
1480 if (!spapr->htab) {
1481 g_free((void *)hptes);
1482 }
1483
1484 /* Nothing to do for qemu managed HPT */
1485 }
1486
1487 static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex,
1488 uint64_t pte0, uint64_t pte1)
1489 {
1490 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1491 hwaddr offset = ptex * HASH_PTE_SIZE_64;
1492
1493 if (!spapr->htab) {
1494 kvmppc_write_hpte(ptex, pte0, pte1);
1495 } else {
1496 stq_p(spapr->htab + offset, pte0);
1497 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1);
1498 }
1499 }
1500
1501 int spapr_hpt_shift_for_ramsize(uint64_t ramsize)
1502 {
1503 int shift;
1504
1505 /* We aim for a hash table of size 1/128 the size of RAM (rounded
1506 * up). The PAPR recommendation is actually 1/64 of RAM size, but
1507 * that's much more than is needed for Linux guests */
1508 shift = ctz64(pow2ceil(ramsize)) - 7;
1509 shift = MAX(shift, 18); /* Minimum architected size */
1510 shift = MIN(shift, 46); /* Maximum architected size */
1511 return shift;
1512 }
1513
1514 void spapr_free_hpt(sPAPRMachineState *spapr)
1515 {
1516 g_free(spapr->htab);
1517 spapr->htab = NULL;
1518 spapr->htab_shift = 0;
1519 close_htab_fd(spapr);
1520 }
1521
1522 void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift,
1523 Error **errp)
1524 {
1525 long rc;
1526
1527 /* Clean up any HPT info from a previous boot */
1528 spapr_free_hpt(spapr);
1529
1530 rc = kvmppc_reset_htab(shift);
1531 if (rc < 0) {
1532 /* kernel-side HPT needed, but couldn't allocate one */
1533 error_setg_errno(errp, errno,
1534 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1535 shift);
1536 /* This is almost certainly fatal, but if the caller really
1537 * wants to carry on with shift == 0, it's welcome to try */
1538 } else if (rc > 0) {
1539 /* kernel-side HPT allocated */
1540 if (rc != shift) {
1541 error_setg(errp,
1542 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1543 shift, rc);
1544 }
1545
1546 spapr->htab_shift = shift;
1547 spapr->htab = NULL;
1548 } else {
1549 /* kernel-side HPT not needed, allocate in userspace instead */
1550 size_t size = 1ULL << shift;
1551 int i;
1552
1553 spapr->htab = qemu_memalign(size, size);
1554 if (!spapr->htab) {
1555 error_setg_errno(errp, errno,
1556 "Could not allocate HPT of order %d", shift);
1557 return;
1558 }
1559
1560 memset(spapr->htab, 0, size);
1561 spapr->htab_shift = shift;
1562
1563 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) {
1564 DIRTY_HPTE(HPTE(spapr->htab, i));
1565 }
1566 }
1567 /* We're setting up a hash table, so that means we're not radix */
1568 spapr->patb_entry = 0;
1569 }
1570
1571 void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr)
1572 {
1573 int hpt_shift;
1574
1575 if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED)
1576 || (spapr->cas_reboot
1577 && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) {
1578 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size);
1579 } else {
1580 uint64_t current_ram_size;
1581
1582 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size();
1583 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size);
1584 }
1585 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal);
1586
1587 if (spapr->vrma_adjust) {
1588 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(MACHINE(spapr)),
1589 spapr->htab_shift);
1590 }
1591 }
1592
1593 static int spapr_reset_drcs(Object *child, void *opaque)
1594 {
1595 sPAPRDRConnector *drc =
1596 (sPAPRDRConnector *) object_dynamic_cast(child,
1597 TYPE_SPAPR_DR_CONNECTOR);
1598
1599 if (drc) {
1600 spapr_drc_reset(drc);
1601 }
1602
1603 return 0;
1604 }
1605
1606 static void spapr_machine_reset(void)
1607 {
1608 MachineState *machine = MACHINE(qdev_get_machine());
1609 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
1610 PowerPCCPU *first_ppc_cpu;
1611 uint32_t rtas_limit;
1612 hwaddr rtas_addr, fdt_addr;
1613 void *fdt;
1614 int rc;
1615
1616 spapr_caps_apply(spapr);
1617
1618 first_ppc_cpu = POWERPC_CPU(first_cpu);
1619 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() &&
1620 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0,
1621 spapr->max_compat_pvr)) {
1622 /* If using KVM with radix mode available, VCPUs can be started
1623 * without a HPT because KVM will start them in radix mode.
1624 * Set the GR bit in PATB so that we know there is no HPT. */
1625 spapr->patb_entry = PATBE1_GR;
1626 } else {
1627 spapr_setup_hpt_and_vrma(spapr);
1628 }
1629
1630 /* if this reset wasn't generated by CAS, we should reset our
1631 * negotiated options and start from scratch */
1632 if (!spapr->cas_reboot) {
1633 spapr_ovec_cleanup(spapr->ov5_cas);
1634 spapr->ov5_cas = spapr_ovec_new();
1635
1636 ppc_set_compat(first_ppc_cpu, spapr->max_compat_pvr, &error_fatal);
1637 }
1638
1639 if (!SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) {
1640 spapr_irq_msi_reset(spapr);
1641 }
1642
1643 qemu_devices_reset();
1644
1645 /*
1646 * This is fixing some of the default configuration of the XIVE
1647 * devices. To be called after the reset of the machine devices.
1648 */
1649 spapr_irq_reset(spapr, &error_fatal);
1650
1651 /* DRC reset may cause a device to be unplugged. This will cause troubles
1652 * if this device is used by another device (eg, a running vhost backend
1653 * will crash QEMU if the DIMM holding the vring goes away). To avoid such
1654 * situations, we reset DRCs after all devices have been reset.
1655 */
1656 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL);
1657
1658 spapr_clear_pending_events(spapr);
1659
1660 /*
1661 * We place the device tree and RTAS just below either the top of the RMA,
1662 * or just below 2GB, whichever is lower, so that it can be
1663 * processed with 32-bit real mode code if necessary
1664 */
1665 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR);
1666 rtas_addr = rtas_limit - RTAS_MAX_SIZE;
1667 fdt_addr = rtas_addr - FDT_MAX_SIZE;
1668
1669 fdt = spapr_build_fdt(spapr);
1670
1671 spapr_load_rtas(spapr, fdt, rtas_addr);
1672
1673 rc = fdt_pack(fdt);
1674
1675 /* Should only fail if we've built a corrupted tree */
1676 assert(rc == 0);
1677
1678 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) {
1679 error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
1680 fdt_totalsize(fdt), FDT_MAX_SIZE);
1681 exit(1);
1682 }
1683
1684 /* Load the fdt */
1685 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
1686 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
1687 g_free(spapr->fdt_blob);
1688 spapr->fdt_size = fdt_totalsize(fdt);
1689 spapr->fdt_initial_size = spapr->fdt_size;
1690 spapr->fdt_blob = fdt;
1691
1692 /* Set up the entry state */
1693 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, fdt_addr);
1694 first_ppc_cpu->env.gpr[5] = 0;
1695
1696 spapr->cas_reboot = false;
1697 }
1698
1699 static void spapr_create_nvram(sPAPRMachineState *spapr)
1700 {
1701 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram");
1702 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
1703
1704 if (dinfo) {
1705 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
1706 &error_fatal);
1707 }
1708
1709 qdev_init_nofail(dev);
1710
1711 spapr->nvram = (struct sPAPRNVRAM *)dev;
1712 }
1713
1714 static void spapr_rtc_create(sPAPRMachineState *spapr)
1715 {
1716 object_initialize(&spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC);
1717 object_property_add_child(OBJECT(spapr), "rtc", OBJECT(&spapr->rtc),
1718 &error_fatal);
1719 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized",
1720 &error_fatal);
1721 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc),
1722 "date", &error_fatal);
1723 }
1724
1725 /* Returns whether we want to use VGA or not */
1726 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp)
1727 {
1728 switch (vga_interface_type) {
1729 case VGA_NONE:
1730 return false;
1731 case VGA_DEVICE:
1732 return true;
1733 case VGA_STD:
1734 case VGA_VIRTIO:
1735 case VGA_CIRRUS:
1736 return pci_vga_init(pci_bus) != NULL;
1737 default:
1738 error_setg(errp,
1739 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1740 return false;
1741 }
1742 }
1743
1744 static int spapr_pre_load(void *opaque)
1745 {
1746 int rc;
1747
1748 rc = spapr_caps_pre_load(opaque);
1749 if (rc) {
1750 return rc;
1751 }
1752
1753 return 0;
1754 }
1755
1756 static int spapr_post_load(void *opaque, int version_id)
1757 {
1758 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque;
1759 int err = 0;
1760
1761 err = spapr_caps_post_migration(spapr);
1762 if (err) {
1763 return err;
1764 }
1765
1766 /*
1767 * In earlier versions, there was no separate qdev for the PAPR
1768 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1769 * So when migrating from those versions, poke the incoming offset
1770 * value into the RTC device
1771 */
1772 if (version_id < 3) {
1773 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset);
1774 if (err) {
1775 return err;
1776 }
1777 }
1778
1779 if (kvm_enabled() && spapr->patb_entry) {
1780 PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
1781 bool radix = !!(spapr->patb_entry & PATBE1_GR);
1782 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE);
1783
1784 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry);
1785 if (err) {
1786 error_report("Process table config unsupported by the host");
1787 return -EINVAL;
1788 }
1789 }
1790
1791 err = spapr_irq_post_load(spapr, version_id);
1792 if (err) {
1793 return err;
1794 }
1795
1796 return err;
1797 }
1798
1799 static int spapr_pre_save(void *opaque)
1800 {
1801 int rc;
1802
1803 rc = spapr_caps_pre_save(opaque);
1804 if (rc) {
1805 return rc;
1806 }
1807
1808 return 0;
1809 }
1810
1811 static bool version_before_3(void *opaque, int version_id)
1812 {
1813 return version_id < 3;
1814 }
1815
1816 static bool spapr_pending_events_needed(void *opaque)
1817 {
1818 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque;
1819 return !QTAILQ_EMPTY(&spapr->pending_events);
1820 }
1821
1822 static const VMStateDescription vmstate_spapr_event_entry = {
1823 .name = "spapr_event_log_entry",
1824 .version_id = 1,
1825 .minimum_version_id = 1,
1826 .fields = (VMStateField[]) {
1827 VMSTATE_UINT32(summary, sPAPREventLogEntry),
1828 VMSTATE_UINT32(extended_length, sPAPREventLogEntry),
1829 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, sPAPREventLogEntry, 0,
1830 NULL, extended_length),
1831 VMSTATE_END_OF_LIST()
1832 },
1833 };
1834
1835 static const VMStateDescription vmstate_spapr_pending_events = {
1836 .name = "spapr_pending_events",
1837 .version_id = 1,
1838 .minimum_version_id = 1,
1839 .needed = spapr_pending_events_needed,
1840 .fields = (VMStateField[]) {
1841 VMSTATE_QTAILQ_V(pending_events, sPAPRMachineState, 1,
1842 vmstate_spapr_event_entry, sPAPREventLogEntry, next),
1843 VMSTATE_END_OF_LIST()
1844 },
1845 };
1846
1847 static bool spapr_ov5_cas_needed(void *opaque)
1848 {
1849 sPAPRMachineState *spapr = opaque;
1850 sPAPROptionVector *ov5_mask = spapr_ovec_new();
1851 sPAPROptionVector *ov5_legacy = spapr_ovec_new();
1852 sPAPROptionVector *ov5_removed = spapr_ovec_new();
1853 bool cas_needed;
1854
1855 /* Prior to the introduction of sPAPROptionVector, we had two option
1856 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY.
1857 * Both of these options encode machine topology into the device-tree
1858 * in such a way that the now-booted OS should still be able to interact
1859 * appropriately with QEMU regardless of what options were actually
1860 * negotiatied on the source side.
1861 *
1862 * As such, we can avoid migrating the CAS-negotiated options if these
1863 * are the only options available on the current machine/platform.
1864 * Since these are the only options available for pseries-2.7 and
1865 * earlier, this allows us to maintain old->new/new->old migration
1866 * compatibility.
1867 *
1868 * For QEMU 2.8+, there are additional CAS-negotiatable options available
1869 * via default pseries-2.8 machines and explicit command-line parameters.
1870 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware
1871 * of the actual CAS-negotiated values to continue working properly. For
1872 * example, availability of memory unplug depends on knowing whether
1873 * OV5_HP_EVT was negotiated via CAS.
1874 *
1875 * Thus, for any cases where the set of available CAS-negotiatable
1876 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we
1877 * include the CAS-negotiated options in the migration stream, unless
1878 * if they affect boot time behaviour only.
1879 */
1880 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY);
1881 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY);
1882 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2);
1883
1884 /* spapr_ovec_diff returns true if bits were removed. we avoid using
1885 * the mask itself since in the future it's possible "legacy" bits may be
1886 * removed via machine options, which could generate a false positive
1887 * that breaks migration.
1888 */
1889 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask);
1890 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy);
1891
1892 spapr_ovec_cleanup(ov5_mask);
1893 spapr_ovec_cleanup(ov5_legacy);
1894 spapr_ovec_cleanup(ov5_removed);
1895
1896 return cas_needed;
1897 }
1898
1899 static const VMStateDescription vmstate_spapr_ov5_cas = {
1900 .name = "spapr_option_vector_ov5_cas",
1901 .version_id = 1,
1902 .minimum_version_id = 1,
1903 .needed = spapr_ov5_cas_needed,
1904 .fields = (VMStateField[]) {
1905 VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1,
1906 vmstate_spapr_ovec, sPAPROptionVector),
1907 VMSTATE_END_OF_LIST()
1908 },
1909 };
1910
1911 static bool spapr_patb_entry_needed(void *opaque)
1912 {
1913 sPAPRMachineState *spapr = opaque;
1914
1915 return !!spapr->patb_entry;
1916 }
1917
1918 static const VMStateDescription vmstate_spapr_patb_entry = {
1919 .name = "spapr_patb_entry",
1920 .version_id = 1,
1921 .minimum_version_id = 1,
1922 .needed = spapr_patb_entry_needed,
1923 .fields = (VMStateField[]) {
1924 VMSTATE_UINT64(patb_entry, sPAPRMachineState),
1925 VMSTATE_END_OF_LIST()
1926 },
1927 };
1928
1929 static bool spapr_irq_map_needed(void *opaque)
1930 {
1931 sPAPRMachineState *spapr = opaque;
1932
1933 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr);
1934 }
1935
1936 static const VMStateDescription vmstate_spapr_irq_map = {
1937 .name = "spapr_irq_map",
1938 .version_id = 1,
1939 .minimum_version_id = 1,
1940 .needed = spapr_irq_map_needed,
1941 .fields = (VMStateField[]) {
1942 VMSTATE_BITMAP(irq_map, sPAPRMachineState, 0, irq_map_nr),
1943 VMSTATE_END_OF_LIST()
1944 },
1945 };
1946
1947 static bool spapr_dtb_needed(void *opaque)
1948 {
1949 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque);
1950
1951 return smc->update_dt_enabled;
1952 }
1953
1954 static int spapr_dtb_pre_load(void *opaque)
1955 {
1956 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque;
1957
1958 g_free(spapr->fdt_blob);
1959 spapr->fdt_blob = NULL;
1960 spapr->fdt_size = 0;
1961
1962 return 0;
1963 }
1964
1965 static const VMStateDescription vmstate_spapr_dtb = {
1966 .name = "spapr_dtb",
1967 .version_id = 1,
1968 .minimum_version_id = 1,
1969 .needed = spapr_dtb_needed,
1970 .pre_load = spapr_dtb_pre_load,
1971 .fields = (VMStateField[]) {
1972 VMSTATE_UINT32(fdt_initial_size, sPAPRMachineState),
1973 VMSTATE_UINT32(fdt_size, sPAPRMachineState),
1974 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, sPAPRMachineState, 0, NULL,
1975 fdt_size),
1976 VMSTATE_END_OF_LIST()
1977 },
1978 };
1979
1980 static const VMStateDescription vmstate_spapr = {
1981 .name = "spapr",
1982 .version_id = 3,
1983 .minimum_version_id = 1,
1984 .pre_load = spapr_pre_load,
1985 .post_load = spapr_post_load,
1986 .pre_save = spapr_pre_save,
1987 .fields = (VMStateField[]) {
1988 /* used to be @next_irq */
1989 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4),
1990
1991 /* RTC offset */
1992 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3),
1993
1994 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2),
1995 VMSTATE_END_OF_LIST()
1996 },
1997 .subsections = (const VMStateDescription*[]) {
1998 &vmstate_spapr_ov5_cas,
1999 &vmstate_spapr_patb_entry,
2000 &vmstate_spapr_pending_events,
2001 &vmstate_spapr_cap_htm,
2002 &vmstate_spapr_cap_vsx,
2003 &vmstate_spapr_cap_dfp,
2004 &vmstate_spapr_cap_cfpc,
2005 &vmstate_spapr_cap_sbbc,
2006 &vmstate_spapr_cap_ibs,
2007 &vmstate_spapr_irq_map,
2008 &vmstate_spapr_cap_nested_kvm_hv,
2009 &vmstate_spapr_dtb,
2010 NULL
2011 }
2012 };
2013
2014 static int htab_save_setup(QEMUFile *f, void *opaque)
2015 {
2016 sPAPRMachineState *spapr = opaque;
2017
2018 /* "Iteration" header */
2019 if (!spapr->htab_shift) {
2020 qemu_put_be32(f, -1);
2021 } else {
2022 qemu_put_be32(f, spapr->htab_shift);
2023 }
2024
2025 if (spapr->htab) {
2026 spapr->htab_save_index = 0;
2027 spapr->htab_first_pass = true;
2028 } else {
2029 if (spapr->htab_shift) {
2030 assert(kvm_enabled());
2031 }
2032 }
2033
2034
2035 return 0;
2036 }
2037
2038 static void htab_save_chunk(QEMUFile *f, sPAPRMachineState *spapr,
2039 int chunkstart, int n_valid, int n_invalid)
2040 {
2041 qemu_put_be32(f, chunkstart);
2042 qemu_put_be16(f, n_valid);
2043 qemu_put_be16(f, n_invalid);
2044 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
2045 HASH_PTE_SIZE_64 * n_valid);
2046 }
2047
2048 static void htab_save_end_marker(QEMUFile *f)
2049 {
2050 qemu_put_be32(f, 0);
2051 qemu_put_be16(f, 0);
2052 qemu_put_be16(f, 0);
2053 }
2054
2055 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr,
2056 int64_t max_ns)
2057 {
2058 bool has_timeout = max_ns != -1;
2059 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
2060 int index = spapr->htab_save_index;
2061 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
2062
2063 assert(spapr->htab_first_pass);
2064
2065 do {
2066 int chunkstart;
2067
2068 /* Consume invalid HPTEs */
2069 while ((index < htabslots)
2070 && !HPTE_VALID(HPTE(spapr->htab, index))) {
2071 CLEAN_HPTE(HPTE(spapr->htab, index));
2072 index++;
2073 }
2074
2075 /* Consume valid HPTEs */
2076 chunkstart = index;
2077 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
2078 && HPTE_VALID(HPTE(spapr->htab, index))) {
2079 CLEAN_HPTE(HPTE(spapr->htab, index));
2080 index++;
2081 }
2082
2083 if (index > chunkstart) {
2084 int n_valid = index - chunkstart;
2085
2086 htab_save_chunk(f, spapr, chunkstart, n_valid, 0);
2087
2088 if (has_timeout &&
2089 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
2090 break;
2091 }
2092 }
2093 } while ((index < htabslots) && !qemu_file_rate_limit(f));
2094
2095 if (index >= htabslots) {
2096 assert(index == htabslots);
2097 index = 0;
2098 spapr->htab_first_pass = false;
2099 }
2100 spapr->htab_save_index = index;
2101 }
2102
2103 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr,
2104 int64_t max_ns)
2105 {
2106 bool final = max_ns < 0;
2107 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
2108 int examined = 0, sent = 0;
2109 int index = spapr->htab_save_index;
2110 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
2111
2112 assert(!spapr->htab_first_pass);
2113
2114 do {
2115 int chunkstart, invalidstart;
2116
2117 /* Consume non-dirty HPTEs */
2118 while ((index < htabslots)
2119 && !HPTE_DIRTY(HPTE(spapr->htab, index))) {
2120 index++;
2121 examined++;
2122 }
2123
2124 chunkstart = index;
2125 /* Consume valid dirty HPTEs */
2126 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
2127 && HPTE_DIRTY(HPTE(spapr->htab, index))
2128 && HPTE_VALID(HPTE(spapr->htab, index))) {
2129 CLEAN_HPTE(HPTE(spapr->htab, index));
2130 index++;
2131 examined++;
2132 }
2133
2134 invalidstart = index;
2135 /* Consume invalid dirty HPTEs */
2136 while ((index < htabslots) && (index - invalidstart < USHRT_MAX)
2137 && HPTE_DIRTY(HPTE(spapr->htab, index))
2138 && !HPTE_VALID(HPTE(spapr->htab, index))) {
2139 CLEAN_HPTE(HPTE(spapr->htab, index));
2140 index++;
2141 examined++;
2142 }
2143
2144 if (index > chunkstart) {
2145 int n_valid = invalidstart - chunkstart;
2146 int n_invalid = index - invalidstart;
2147
2148 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid);
2149 sent += index - chunkstart;
2150
2151 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
2152 break;
2153 }
2154 }
2155
2156 if (examined >= htabslots) {
2157 break;
2158 }
2159
2160 if (index >= htabslots) {
2161 assert(index == htabslots);
2162 index = 0;
2163 }
2164 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final));
2165
2166 if (index >= htabslots) {
2167 assert(index == htabslots);
2168 index = 0;
2169 }
2170
2171 spapr->htab_save_index = index;
2172
2173 return (examined >= htabslots) && (sent == 0) ? 1 : 0;
2174 }
2175
2176 #define MAX_ITERATION_NS 5000000 /* 5 ms */
2177 #define MAX_KVM_BUF_SIZE 2048
2178
2179 static int htab_save_iterate(QEMUFile *f, void *opaque)
2180 {
2181 sPAPRMachineState *spapr = opaque;
2182 int fd;
2183 int rc = 0;
2184
2185 /* Iteration header */
2186 if (!spapr->htab_shift) {
2187 qemu_put_be32(f, -1);
2188 return 1;
2189 } else {
2190 qemu_put_be32(f, 0);
2191 }
2192
2193 if (!spapr->htab) {
2194 assert(kvm_enabled());
2195
2196 fd = get_htab_fd(spapr);
2197 if (fd < 0) {
2198 return fd;
2199 }
2200
2201 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS);
2202 if (rc < 0) {
2203 return rc;
2204 }
2205 } else if (spapr->htab_first_pass) {
2206 htab_save_first_pass(f, spapr, MAX_ITERATION_NS);
2207 } else {
2208 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS);
2209 }
2210
2211 htab_save_end_marker(f);
2212
2213 return rc;
2214 }
2215
2216 static int htab_save_complete(QEMUFile *f, void *opaque)
2217 {
2218 sPAPRMachineState *spapr = opaque;
2219 int fd;
2220
2221 /* Iteration header */
2222 if (!spapr->htab_shift) {
2223 qemu_put_be32(f, -1);
2224 return 0;
2225 } else {
2226 qemu_put_be32(f, 0);
2227 }
2228
2229 if (!spapr->htab) {
2230 int rc;
2231
2232 assert(kvm_enabled());
2233
2234 fd = get_htab_fd(spapr);
2235 if (fd < 0) {
2236 return fd;
2237 }
2238
2239 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1);
2240 if (rc < 0) {
2241 return rc;
2242 }
2243 } else {
2244 if (spapr->htab_first_pass) {
2245 htab_save_first_pass(f, spapr, -1);
2246 }
2247 htab_save_later_pass(f, spapr, -1);
2248 }
2249
2250 /* End marker */
2251 htab_save_end_marker(f);
2252
2253 return 0;
2254 }
2255
2256 static int htab_load(QEMUFile *f, void *opaque, int version_id)
2257 {
2258 sPAPRMachineState *spapr = opaque;
2259 uint32_t section_hdr;
2260 int fd = -1;
2261 Error *local_err = NULL;
2262
2263 if (version_id < 1 || version_id > 1) {
2264 error_report("htab_load() bad version");
2265 return -EINVAL;
2266 }
2267
2268 section_hdr = qemu_get_be32(f);
2269
2270 if (section_hdr == -1) {
2271 spapr_free_hpt(spapr);
2272 return 0;
2273 }
2274
2275 if (section_hdr) {
2276 /* First section gives the htab size */
2277 spapr_reallocate_hpt(spapr, section_hdr, &local_err);
2278 if (local_err) {
2279 error_report_err(local_err);
2280 return -EINVAL;
2281 }
2282 return 0;
2283 }
2284
2285 if (!spapr->htab) {
2286 assert(kvm_enabled());
2287
2288 fd = kvmppc_get_htab_fd(true, 0, &local_err);
2289 if (fd < 0) {
2290 error_report_err(local_err);
2291 return fd;
2292 }
2293 }
2294
2295 while (true) {
2296 uint32_t index;
2297 uint16_t n_valid, n_invalid;
2298
2299 index = qemu_get_be32(f);
2300 n_valid = qemu_get_be16(f);
2301 n_invalid = qemu_get_be16(f);
2302
2303 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) {
2304 /* End of Stream */
2305 break;
2306 }
2307
2308 if ((index + n_valid + n_invalid) >
2309 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) {
2310 /* Bad index in stream */
2311 error_report(
2312 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
2313 index, n_valid, n_invalid, spapr->htab_shift);
2314 return -EINVAL;
2315 }
2316
2317 if (spapr->htab) {
2318 if (n_valid) {
2319 qemu_get_buffer(f, HPTE(spapr->htab, index),
2320 HASH_PTE_SIZE_64 * n_valid);
2321 }
2322 if (n_invalid) {
2323 memset(HPTE(spapr->htab, index + n_valid), 0,
2324 HASH_PTE_SIZE_64 * n_invalid);
2325 }
2326 } else {
2327 int rc;
2328
2329 assert(fd >= 0);
2330
2331 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid);
2332 if (rc < 0) {
2333 return rc;
2334 }
2335 }
2336 }
2337
2338 if (!spapr->htab) {
2339 assert(fd >= 0);
2340 close(fd);
2341 }
2342
2343 return 0;
2344 }
2345
2346 static void htab_save_cleanup(void *opaque)
2347 {
2348 sPAPRMachineState *spapr = opaque;
2349
2350 close_htab_fd(spapr);
2351 }
2352
2353 static SaveVMHandlers savevm_htab_handlers = {
2354 .save_setup = htab_save_setup,
2355 .save_live_iterate = htab_save_iterate,
2356 .save_live_complete_precopy = htab_save_complete,
2357 .save_cleanup = htab_save_cleanup,
2358 .load_state = htab_load,
2359 };
2360
2361 static void spapr_boot_set(void *opaque, const char *boot_device,
2362 Error **errp)
2363 {
2364 MachineState *machine = MACHINE(opaque);
2365 machine->boot_order = g_strdup(boot_device);
2366 }
2367
2368 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr)
2369 {
2370 MachineState *machine = MACHINE(spapr);
2371 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
2372 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size;
2373 int i;
2374
2375 for (i = 0; i < nr_lmbs; i++) {
2376 uint64_t addr;
2377
2378 addr = i * lmb_size + machine->device_memory->base;
2379 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB,
2380 addr / lmb_size);
2381 }
2382 }
2383
2384 /*
2385 * If RAM size, maxmem size and individual node mem sizes aren't aligned
2386 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
2387 * since we can't support such unaligned sizes with DRCONF_MEMORY.
2388 */
2389 static void spapr_validate_node_memory(MachineState *machine, Error **errp)
2390 {
2391 int i;
2392
2393 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) {
2394 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT
2395 " is not aligned to %" PRIu64 " MiB",
2396 machine->ram_size,
2397 SPAPR_MEMORY_BLOCK_SIZE / MiB);
2398 return;
2399 }
2400
2401 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) {
2402 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT
2403 " is not aligned to %" PRIu64 " MiB",
2404 machine->ram_size,
2405 SPAPR_MEMORY_BLOCK_SIZE / MiB);
2406 return;
2407 }
2408
2409 for (i = 0; i < nb_numa_nodes; i++) {
2410 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) {
2411 error_setg(errp,
2412 "Node %d memory size 0x%" PRIx64
2413 " is not aligned to %" PRIu64 " MiB",
2414 i, numa_info[i].node_mem,
2415 SPAPR_MEMORY_BLOCK_SIZE / MiB);
2416 return;
2417 }
2418 }
2419 }
2420
2421 /* find cpu slot in machine->possible_cpus by core_id */
2422 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
2423 {
2424 int index = id / smp_threads;
2425
2426 if (index >= ms->possible_cpus->len) {
2427 return NULL;
2428 }
2429 if (idx) {
2430 *idx = index;
2431 }
2432 return &ms->possible_cpus->cpus[index];
2433 }
2434
2435 static void spapr_set_vsmt_mode(sPAPRMachineState *spapr, Error **errp)
2436 {
2437 Error *local_err = NULL;
2438 bool vsmt_user = !!spapr->vsmt;
2439 int kvm_smt = kvmppc_smt_threads();
2440 int ret;
2441
2442 if (!kvm_enabled() && (smp_threads > 1)) {
2443 error_setg(&local_err, "TCG cannot support more than 1 thread/core "
2444 "on a pseries machine");
2445 goto out;
2446 }
2447 if (!is_power_of_2(smp_threads)) {
2448 error_setg(&local_err, "Cannot support %d threads/core on a pseries "
2449 "machine because it must be a power of 2", smp_threads);
2450 goto out;
2451 }
2452
2453 /* Detemine the VSMT mode to use: */
2454 if (vsmt_user) {
2455 if (spapr->vsmt < smp_threads) {
2456 error_setg(&local_err, "Cannot support VSMT mode %d"
2457 " because it must be >= threads/core (%d)",
2458 spapr->vsmt, smp_threads);
2459 goto out;
2460 }
2461 /* In this case, spapr->vsmt has been set by the command line */
2462 } else {
2463 /*
2464 * Default VSMT value is tricky, because we need it to be as
2465 * consistent as possible (for migration), but this requires
2466 * changing it for at least some existing cases. We pick 8 as
2467 * the value that we'd get with KVM on POWER8, the
2468 * overwhelmingly common case in production systems.
2469 */
2470 spapr->vsmt = MAX(8, smp_threads);
2471 }
2472
2473 /* KVM: If necessary, set the SMT mode: */
2474 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) {
2475 ret = kvmppc_set_smt_threads(spapr->vsmt);
2476 if (ret) {
2477 /* Looks like KVM isn't able to change VSMT mode */
2478 error_setg(&local_err,
2479 "Failed to set KVM's VSMT mode to %d (errno %d)",
2480 spapr->vsmt, ret);
2481 /* We can live with that if the default one is big enough
2482 * for the number of threads, and a submultiple of the one
2483 * we want. In this case we'll waste some vcpu ids, but
2484 * behaviour will be correct */
2485 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) {
2486 warn_report_err(local_err);
2487 local_err = NULL;
2488 goto out;
2489 } else {
2490 if (!vsmt_user) {
2491 error_append_hint(&local_err,
2492 "On PPC, a VM with %d threads/core"
2493 " on a host with %d threads/core"
2494 " requires the use of VSMT mode %d.\n",
2495 smp_threads, kvm_smt, spapr->vsmt);
2496 }
2497 kvmppc_hint_smt_possible(&local_err);
2498 goto out;
2499 }
2500 }
2501 }
2502 /* else TCG: nothing to do currently */
2503 out:
2504 error_propagate(errp, local_err);
2505 }
2506
2507 static void spapr_init_cpus(sPAPRMachineState *spapr)
2508 {
2509 MachineState *machine = MACHINE(spapr);
2510 MachineClass *mc = MACHINE_GET_CLASS(machine);
2511 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
2512 const char *type = spapr_get_cpu_core_type(machine->cpu_type);
2513 const CPUArchIdList *possible_cpus;
2514 int boot_cores_nr = smp_cpus / smp_threads;
2515 int i;
2516
2517 possible_cpus = mc->possible_cpu_arch_ids(machine);
2518 if (mc->has_hotpluggable_cpus) {
2519 if (smp_cpus % smp_threads) {
2520 error_report("smp_cpus (%u) must be multiple of threads (%u)",
2521 smp_cpus, smp_threads);
2522 exit(1);
2523 }
2524 if (max_cpus % smp_threads) {
2525 error_report("max_cpus (%u) must be multiple of threads (%u)",
2526 max_cpus, smp_threads);
2527 exit(1);
2528 }
2529 } else {
2530 if (max_cpus != smp_cpus) {
2531 error_report("This machine version does not support CPU hotplug");
2532 exit(1);
2533 }
2534 boot_cores_nr = possible_cpus->len;
2535 }
2536
2537 if (smc->pre_2_10_has_unused_icps) {
2538 int i;
2539
2540 for (i = 0; i < spapr_max_server_number(spapr); i++) {
2541 /* Dummy entries get deregistered when real ICPState objects
2542 * are registered during CPU core hotplug.
2543 */
2544 pre_2_10_vmstate_register_dummy_icp(i);
2545 }
2546 }
2547
2548 for (i = 0; i < possible_cpus->len; i++) {
2549 int core_id = i * smp_threads;
2550
2551 if (mc->has_hotpluggable_cpus) {
2552 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU,
2553 spapr_vcpu_id(spapr, core_id));
2554 }
2555
2556 if (i < boot_cores_nr) {
2557 Object *core = object_new(type);
2558 int nr_threads = smp_threads;
2559
2560 /* Handle the partially filled core for older machine types */
2561 if ((i + 1) * smp_threads >= smp_cpus) {
2562 nr_threads = smp_cpus - i * smp_threads;
2563 }
2564
2565 object_property_set_int(core, nr_threads, "nr-threads",
2566 &error_fatal);
2567 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID,
2568 &error_fatal);
2569 object_property_set_bool(core, true, "realized", &error_fatal);
2570
2571 object_unref(core);
2572 }
2573 }
2574 }
2575
2576 static PCIHostState *spapr_create_default_phb(void)
2577 {
2578 DeviceState *dev;
2579
2580 dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE);
2581 qdev_prop_set_uint32(dev, "index", 0);
2582 qdev_init_nofail(dev);
2583
2584 return PCI_HOST_BRIDGE(dev);
2585 }
2586
2587 /* pSeries LPAR / sPAPR hardware init */
2588 static void spapr_machine_init(MachineState *machine)
2589 {
2590 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
2591 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
2592 const char *kernel_filename = machine->kernel_filename;
2593 const char *initrd_filename = machine->initrd_filename;
2594 PCIHostState *phb;
2595 int i;
2596 MemoryRegion *sysmem = get_system_memory();
2597 MemoryRegion *ram = g_new(MemoryRegion, 1);
2598 hwaddr node0_size = spapr_node0_size(machine);
2599 long load_limit, fw_size;
2600 char *filename;
2601 Error *resize_hpt_err = NULL;
2602
2603 msi_nonbroken = true;
2604
2605 QLIST_INIT(&spapr->phbs);
2606 QTAILQ_INIT(&spapr->pending_dimm_unplugs);
2607
2608 /* Determine capabilities to run with */
2609 spapr_caps_init(spapr);
2610
2611 kvmppc_check_papr_resize_hpt(&resize_hpt_err);
2612 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) {
2613 /*
2614 * If the user explicitly requested a mode we should either
2615 * supply it, or fail completely (which we do below). But if
2616 * it's not set explicitly, we reset our mode to something
2617 * that works
2618 */
2619 if (resize_hpt_err) {
2620 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED;
2621 error_free(resize_hpt_err);
2622 resize_hpt_err = NULL;
2623 } else {
2624 spapr->resize_hpt = smc->resize_hpt_default;
2625 }
2626 }
2627
2628 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT);
2629
2630 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) {
2631 /*
2632 * User requested HPT resize, but this host can't supply it. Bail out
2633 */
2634 error_report_err(resize_hpt_err);
2635 exit(1);
2636 }
2637
2638 spapr->rma_size = node0_size;
2639
2640 /* With KVM, we don't actually know whether KVM supports an
2641 * unbounded RMA (PR KVM) or is limited by the hash table size
2642 * (HV KVM using VRMA), so we always assume the latter
2643 *
2644 * In that case, we also limit the initial allocations for RTAS
2645 * etc... to 256M since we have no way to know what the VRMA size
2646 * is going to be as it depends on the size of the hash table
2647 * which isn't determined yet.
2648 */
2649 if (kvm_enabled()) {
2650 spapr->vrma_adjust = 1;
2651 spapr->rma_size = MIN(spapr->rma_size, 0x10000000);
2652 }
2653
2654 /* Actually we don't support unbounded RMA anymore since we added
2655 * proper emulation of HV mode. The max we can get is 16G which
2656 * also happens to be what we configure for PAPR mode so make sure
2657 * we don't do anything bigger than that
2658 */
2659 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull);
2660
2661 if (spapr->rma_size > node0_size) {
2662 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")",
2663 spapr->rma_size);
2664 exit(1);
2665 }
2666
2667 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
2668 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD;
2669
2670 /*
2671 * VSMT must be set in order to be able to compute VCPU ids, ie to
2672 * call spapr_max_server_number() or spapr_vcpu_id().
2673 */
2674 spapr_set_vsmt_mode(spapr, &error_fatal);
2675
2676 /* Set up Interrupt Controller before we create the VCPUs */
2677 spapr_irq_init(spapr, &error_fatal);
2678
2679 /* Set up containers for ibm,client-architecture-support negotiated options
2680 */
2681 spapr->ov5 = spapr_ovec_new();
2682 spapr->ov5_cas = spapr_ovec_new();
2683
2684 if (smc->dr_lmb_enabled) {
2685 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY);
2686 spapr_validate_node_memory(machine, &error_fatal);
2687 }
2688
2689 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY);
2690
2691 /* advertise support for dedicated HP event source to guests */
2692 if (spapr->use_hotplug_event_source) {
2693 spapr_ovec_set(spapr->ov5, OV5_HP_EVT);
2694 }
2695
2696 /* advertise support for HPT resizing */
2697 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) {
2698 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE);
2699 }
2700
2701 /* advertise support for ibm,dyamic-memory-v2 */
2702 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2);
2703
2704 /* advertise XIVE on POWER9 machines */
2705 if (spapr->irq->ov5 & (SPAPR_OV5_XIVE_EXPLOIT | SPAPR_OV5_XIVE_BOTH)) {
2706 if (ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00,
2707 0, spapr->max_compat_pvr)) {
2708 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT);
2709 } else if (spapr->irq->ov5 & SPAPR_OV5_XIVE_EXPLOIT) {
2710 error_report("XIVE-only machines require a POWER9 CPU");
2711 exit(1);
2712 }
2713 }
2714
2715 /* init CPUs */
2716 spapr_init_cpus(spapr);
2717
2718 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) &&
2719 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0,
2720 spapr->max_compat_pvr)) {
2721 /* KVM and TCG always allow GTSE with radix... */
2722 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE);
2723 }
2724 /* ... but not with hash (currently). */
2725
2726 if (kvm_enabled()) {
2727 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
2728 kvmppc_enable_logical_ci_hcalls();
2729 kvmppc_enable_set_mode_hcall();
2730
2731 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */
2732 kvmppc_enable_clear_ref_mod_hcalls();
2733 }
2734
2735 /* allocate RAM */
2736 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram",
2737 machine->ram_size);
2738 memory_region_add_subregion(sysmem, 0, ram);
2739
2740 /* always allocate the device memory information */
2741 machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
2742
2743 /* initialize hotplug memory address space */
2744 if (machine->ram_size < machine->maxram_size) {
2745 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size;
2746 /*
2747 * Limit the number of hotpluggable memory slots to half the number
2748 * slots that KVM supports, leaving the other half for PCI and other
2749 * devices. However ensure that number of slots doesn't drop below 32.
2750 */
2751 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 :
2752 SPAPR_MAX_RAM_SLOTS;
2753
2754 if (max_memslots < SPAPR_MAX_RAM_SLOTS) {
2755 max_memslots = SPAPR_MAX_RAM_SLOTS;
2756 }
2757 if (machine->ram_slots > max_memslots) {
2758 error_report("Specified number of memory slots %"
2759 PRIu64" exceeds max supported %d",
2760 machine->ram_slots, max_memslots);
2761 exit(1);
2762 }
2763
2764 machine->device_memory->base = ROUND_UP(machine->ram_size,
2765 SPAPR_DEVICE_MEM_ALIGN);
2766 memory_region_init(&machine->device_memory->mr, OBJECT(spapr),
2767 "device-memory", device_mem_size);
2768 memory_region_add_subregion(sysmem, machine->device_memory->base,
2769 &machine->device_memory->mr);
2770 }
2771
2772 if (smc->dr_lmb_enabled) {
2773 spapr_create_lmb_dr_connectors(spapr);
2774 }
2775
2776 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
2777 if (!filename) {
2778 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin");
2779 exit(1);
2780 }
2781 spapr->rtas_size = get_image_size(filename);
2782 if (spapr->rtas_size < 0) {
2783 error_report("Could not get size of LPAR rtas '%s'", filename);
2784 exit(1);
2785 }
2786 spapr->rtas_blob = g_malloc(spapr->rtas_size);
2787 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) {
2788 error_report("Could not load LPAR rtas '%s'", filename);
2789 exit(1);
2790 }
2791 if (spapr->rtas_size > RTAS_MAX_SIZE) {
2792 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)",
2793 (size_t)spapr->rtas_size, RTAS_MAX_SIZE);
2794 exit(1);
2795 }
2796 g_free(filename);
2797
2798 /* Set up RTAS event infrastructure */
2799 spapr_events_init(spapr);
2800
2801 /* Set up the RTC RTAS interfaces */
2802 spapr_rtc_create(spapr);
2803
2804 /* Set up VIO bus */
2805 spapr->vio_bus = spapr_vio_bus_init();
2806
2807 for (i = 0; i < serial_max_hds(); i++) {
2808 if (serial_hd(i)) {
2809 spapr_vty_create(spapr->vio_bus, serial_hd(i));
2810 }
2811 }
2812
2813 /* We always have at least the nvram device on VIO */
2814 spapr_create_nvram(spapr);
2815
2816 /* Set up PCI */
2817 spapr_pci_rtas_init();
2818
2819 phb = spapr_create_default_phb();
2820
2821 for (i = 0; i < nb_nics; i++) {
2822 NICInfo *nd = &nd_table[i];
2823
2824 if (!nd->model) {
2825 nd->model = g_strdup("spapr-vlan");
2826 }
2827
2828 if (g_str_equal(nd->model, "spapr-vlan") ||
2829 g_str_equal(nd->model, "ibmveth")) {
2830 spapr_vlan_create(spapr->vio_bus, nd);
2831 } else {
2832 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL);
2833 }
2834 }
2835
2836 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
2837 spapr_vscsi_create(spapr->vio_bus);
2838 }
2839
2840 /* Graphics */
2841 if (spapr_vga_init(phb->bus, &error_fatal)) {
2842 spapr->has_graphics = true;
2843 machine->usb |= defaults_enabled() && !machine->usb_disabled;
2844 }
2845
2846 if (machine->usb) {
2847 if (smc->use_ohci_by_default) {
2848 pci_create_simple(phb->bus, -1, "pci-ohci");
2849 } else {
2850 pci_create_simple(phb->bus, -1, "nec-usb-xhci");
2851 }
2852
2853 if (spapr->has_graphics) {
2854 USBBus *usb_bus = usb_bus_find(-1);
2855
2856 usb_create_simple(usb_bus, "usb-kbd");
2857 usb_create_simple(usb_bus, "usb-mouse");
2858 }
2859 }
2860
2861 if (spapr->rma_size < (MIN_RMA_SLOF * MiB)) {
2862 error_report(
2863 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
2864 MIN_RMA_SLOF);
2865 exit(1);
2866 }
2867
2868 if (kernel_filename) {
2869 uint64_t lowaddr = 0;
2870
2871 spapr->kernel_size = load_elf(kernel_filename, NULL,
2872 translate_kernel_address, NULL,
2873 NULL, &lowaddr, NULL, 1,
2874 PPC_ELF_MACHINE, 0, 0);
2875 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) {
2876 spapr->kernel_size = load_elf(kernel_filename, NULL,
2877 translate_kernel_address, NULL, NULL,
2878 &lowaddr, NULL, 0, PPC_ELF_MACHINE,
2879 0, 0);
2880 spapr->kernel_le = spapr->kernel_size > 0;
2881 }
2882 if (spapr->kernel_size < 0) {
2883 error_report("error loading %s: %s", kernel_filename,
2884 load_elf_strerror(spapr->kernel_size));
2885 exit(1);
2886 }
2887
2888 /* load initrd */
2889 if (initrd_filename) {
2890 /* Try to locate the initrd in the gap between the kernel
2891 * and the firmware. Add a bit of space just in case
2892 */
2893 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size
2894 + 0x1ffff) & ~0xffff;
2895 spapr->initrd_size = load_image_targphys(initrd_filename,
2896 spapr->initrd_base,
2897 load_limit
2898 - spapr->initrd_base);
2899 if (spapr->initrd_size < 0) {
2900 error_report("could not load initial ram disk '%s'",
2901 initrd_filename);
2902 exit(1);
2903 }
2904 }
2905 }
2906
2907 if (bios_name == NULL) {
2908 bios_name = FW_FILE_NAME;
2909 }
2910 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
2911 if (!filename) {
2912 error_report("Could not find LPAR firmware '%s'", bios_name);
2913 exit(1);
2914 }
2915 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
2916 if (fw_size <= 0) {
2917 error_report("Could not load LPAR firmware '%s'", filename);
2918 exit(1);
2919 }
2920 g_free(filename);
2921
2922 /* FIXME: Should register things through the MachineState's qdev
2923 * interface, this is a legacy from the sPAPREnvironment structure
2924 * which predated MachineState but had a similar function */
2925 vmstate_register(NULL, 0, &vmstate_spapr, spapr);
2926 register_savevm_live(NULL, "spapr/htab", -1, 1,
2927 &savevm_htab_handlers, spapr);
2928
2929 qemu_register_boot_set(spapr_boot_set, spapr);
2930
2931 if (kvm_enabled()) {
2932 /* to stop and start vmclock */
2933 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change,
2934 &spapr->tb);
2935
2936 kvmppc_spapr_enable_inkernel_multitce();
2937 }
2938 }
2939
2940 static int spapr_kvm_type(const char *vm_type)
2941 {
2942 if (!vm_type) {
2943 return 0;
2944 }
2945
2946 if (!strcmp(vm_type, "HV")) {
2947 return 1;
2948 }
2949
2950 if (!strcmp(vm_type, "PR")) {
2951 return 2;
2952 }
2953
2954 error_report("Unknown kvm-type specified '%s'", vm_type);
2955 exit(1);
2956 }
2957
2958 /*
2959 * Implementation of an interface to adjust firmware path
2960 * for the bootindex property handling.
2961 */
2962 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus,
2963 DeviceState *dev)
2964 {
2965 #define CAST(type, obj, name) \
2966 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
2967 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE);
2968 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE);
2969 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON);
2970
2971 if (d) {
2972 void *spapr = CAST(void, bus->parent, "spapr-vscsi");
2973 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI);
2974 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE);
2975
2976 if (spapr) {
2977 /*
2978 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
2979 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form
2980 * 0x8000 | (target << 8) | (bus << 5) | lun
2981 * (see the "Logical unit addressing format" table in SAM5)
2982 */
2983 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun;
2984 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2985 (uint64_t)id << 48);
2986 } else if (virtio) {
2987 /*
2988 * We use SRP luns of the form 01000000 | (target << 8) | lun
2989 * in the top 32 bits of the 64-bit LUN
2990 * Note: the quote above is from SLOF and it is wrong,
2991 * the actual binding is:
2992 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
2993 */
2994 unsigned id = 0x1000000 | (d->id << 16) | d->lun;
2995 if (d->lun >= 256) {
2996 /* Use the LUN "flat space addressing method" */
2997 id |= 0x4000;
2998 }
2999 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
3000 (uint64_t)id << 32);
3001 } else if (usb) {
3002 /*
3003 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
3004 * in the top 32 bits of the 64-bit LUN
3005 */
3006 unsigned usb_port = atoi(usb->port->path);
3007 unsigned id = 0x1000000 | (usb_port << 16) | d->lun;
3008 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
3009 (uint64_t)id << 32);
3010 }
3011 }
3012
3013 /*
3014 * SLOF probes the USB devices, and if it recognizes that the device is a
3015 * storage device, it changes its name to "storage" instead of "usb-host",
3016 * and additionally adds a child node for the SCSI LUN, so the correct
3017 * boot path in SLOF is something like .../storage@1/disk@xxx" instead.
3018 */
3019 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) {
3020 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE);
3021 if (usb_host_dev_is_scsi_storage(usbdev)) {
3022 return g_strdup_printf("storage@%s/disk", usbdev->port->path);
3023 }
3024 }
3025
3026 if (phb) {
3027 /* Replace "pci" with "pci@800000020000000" */
3028 return g_strdup_printf("pci@%"PRIX64, phb->buid);
3029 }
3030
3031 if (vsc) {
3032 /* Same logic as virtio above */
3033 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun;
3034 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32);
3035 }
3036
3037 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) {
3038 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */
3039 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE);
3040 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn));
3041 }
3042
3043 return NULL;
3044 }
3045
3046 static char *spapr_get_kvm_type(Object *obj, Error **errp)
3047 {
3048 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
3049
3050 return g_strdup(spapr->kvm_type);
3051 }
3052
3053 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp)
3054 {
3055 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
3056
3057 g_free(spapr->kvm_type);
3058 spapr->kvm_type = g_strdup(value);
3059 }
3060
3061 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp)
3062 {
3063 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
3064
3065 return spapr->use_hotplug_event_source;
3066 }
3067
3068 static void spapr_set_modern_hotplug_events(Object *obj, bool value,
3069 Error **errp)
3070 {
3071 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
3072
3073 spapr->use_hotplug_event_source = value;
3074 }
3075
3076 static bool spapr_get_msix_emulation(Object *obj, Error **errp)
3077 {
3078 return true;
3079 }
3080
3081 static char *spapr_get_resize_hpt(Object *obj, Error **errp)
3082 {
3083 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
3084
3085 switch (spapr->resize_hpt) {
3086 case SPAPR_RESIZE_HPT_DEFAULT:
3087 return g_strdup("default");
3088 case SPAPR_RESIZE_HPT_DISABLED:
3089 return g_strdup("disabled");
3090 case SPAPR_RESIZE_HPT_ENABLED:
3091 return g_strdup("enabled");
3092 case SPAPR_RESIZE_HPT_REQUIRED:
3093 return g_strdup("required");
3094 }
3095 g_assert_not_reached();
3096 }
3097
3098 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp)
3099 {
3100 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
3101
3102 if (strcmp(value, "default") == 0) {
3103 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT;
3104 } else if (strcmp(value, "disabled") == 0) {
3105 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED;
3106 } else if (strcmp(value, "enabled") == 0) {
3107 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED;
3108 } else if (strcmp(value, "required") == 0) {
3109 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED;
3110 } else {
3111 error_setg(errp, "Bad value for \"resize-hpt\" property");
3112 }
3113 }
3114
3115 static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name,
3116 void *opaque, Error **errp)
3117 {
3118 visit_type_uint32(v, name, (uint32_t *)opaque, errp);
3119 }
3120
3121 static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name,
3122 void *opaque, Error **errp)
3123 {
3124 visit_type_uint32(v, name, (uint32_t *)opaque, errp);
3125 }
3126
3127 static char *spapr_get_ic_mode(Object *obj, Error **errp)
3128 {
3129 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
3130
3131 if (spapr->irq == &spapr_irq_xics_legacy) {
3132 return g_strdup("legacy");
3133 } else if (spapr->irq == &spapr_irq_xics) {
3134 return g_strdup("xics");
3135 } else if (spapr->irq == &spapr_irq_xive) {
3136 return g_strdup("xive");
3137 } else if (spapr->irq == &spapr_irq_dual) {
3138 return g_strdup("dual");
3139 }
3140 g_assert_not_reached();
3141 }
3142
3143 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp)
3144 {
3145 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
3146
3147 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) {
3148 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode");
3149 return;
3150 }
3151
3152 /* The legacy IRQ backend can not be set */
3153 if (strcmp(value, "xics") == 0) {
3154 spapr->irq = &spapr_irq_xics;
3155 } else if (strcmp(value, "xive") == 0) {
3156 spapr->irq = &spapr_irq_xive;
3157 } else if (strcmp(value, "dual") == 0) {
3158 spapr->irq = &spapr_irq_dual;
3159 } else {
3160 error_setg(errp, "Bad value for \"ic-mode\" property");
3161 }
3162 }
3163
3164 static char *spapr_get_host_model(Object *obj, Error **errp)
3165 {
3166 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
3167
3168 return g_strdup(spapr->host_model);
3169 }
3170
3171 static void spapr_set_host_model(Object *obj, const char *value, Error **errp)
3172 {
3173 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
3174
3175 g_free(spapr->host_model);
3176 spapr->host_model = g_strdup(value);
3177 }
3178
3179 static char *spapr_get_host_serial(Object *obj, Error **errp)
3180 {
3181 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
3182
3183 return g_strdup(spapr->host_serial);
3184 }
3185
3186 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp)
3187 {
3188 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
3189
3190 g_free(spapr->host_serial);
3191 spapr->host_serial = g_strdup(value);
3192 }
3193
3194 static void spapr_instance_init(Object *obj)
3195 {
3196 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
3197 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
3198
3199 spapr->htab_fd = -1;
3200 spapr->use_hotplug_event_source = true;
3201 object_property_add_str(obj, "kvm-type",
3202 spapr_get_kvm_type, spapr_set_kvm_type, NULL);
3203 object_property_set_description(obj, "kvm-type",
3204 "Specifies the KVM virtualization mode (HV, PR)",
3205 NULL);
3206 object_property_add_bool(obj, "modern-hotplug-events",
3207 spapr_get_modern_hotplug_events,
3208 spapr_set_modern_hotplug_events,
3209 NULL);
3210 object_property_set_description(obj, "modern-hotplug-events",
3211 "Use dedicated hotplug event mechanism in"
3212 " place of standard EPOW events when possible"
3213 " (required for memory hot-unplug support)",
3214 NULL);
3215 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr,
3216 "Maximum permitted CPU compatibility mode",
3217 &error_fatal);
3218
3219 object_property_add_str(obj, "resize-hpt",
3220 spapr_get_resize_hpt, spapr_set_resize_hpt, NULL);
3221 object_property_set_description(obj, "resize-hpt",
3222 "Resizing of the Hash Page Table (enabled, disabled, required)",
3223 NULL);
3224 object_property_add(obj, "vsmt", "uint32", spapr_get_vsmt,
3225 spapr_set_vsmt, NULL, &spapr->vsmt, &error_abort);
3226 object_property_set_description(obj, "vsmt",
3227 "Virtual SMT: KVM behaves as if this were"
3228 " the host's SMT mode", &error_abort);
3229 object_property_add_bool(obj, "vfio-no-msix-emulation",
3230 spapr_get_msix_emulation, NULL, NULL);
3231
3232 /* The machine class defines the default interrupt controller mode */
3233 spapr->irq = smc->irq;
3234 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode,
3235 spapr_set_ic_mode, NULL);
3236 object_property_set_description(obj, "ic-mode",
3237 "Specifies the interrupt controller mode (xics, xive, dual)",
3238 NULL);
3239
3240 object_property_add_str(obj, "host-model",
3241 spapr_get_host_model, spapr_set_host_model,
3242 &error_abort);
3243 object_property_set_description(obj, "host-model",
3244 "Set host's model-id to use - none|passthrough|string", &error_abort);
3245 object_property_add_str(obj, "host-serial",
3246 spapr_get_host_serial, spapr_set_host_serial,
3247 &error_abort);
3248 object_property_set_description(obj, "host-serial",
3249 "Set host's system-id to use - none|passthrough|string", &error_abort);
3250 }
3251
3252 static void spapr_machine_finalizefn(Object *obj)
3253 {
3254 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
3255
3256 g_free(spapr->kvm_type);
3257 }
3258
3259 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg)
3260 {
3261 cpu_synchronize_state(cs);
3262 ppc_cpu_do_system_reset(cs);
3263 }
3264
3265 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp)
3266 {
3267 CPUState *cs;
3268
3269 CPU_FOREACH(cs) {
3270 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL);
3271 }
3272 }
3273
3274 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size,
3275 uint32_t node, bool dedicated_hp_event_source,
3276 Error **errp)
3277 {
3278 sPAPRDRConnector *drc;
3279 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE;
3280 int i, fdt_offset, fdt_size;
3281 void *fdt;
3282 uint64_t addr = addr_start;
3283 bool hotplugged = spapr_drc_hotplugged(dev);
3284 Error *local_err = NULL;
3285
3286 for (i = 0; i < nr_lmbs; i++) {
3287 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3288 addr / SPAPR_MEMORY_BLOCK_SIZE);
3289 g_assert(drc);
3290
3291 fdt = create_device_tree(&fdt_size);
3292 fdt_offset = spapr_populate_memory_node(fdt, node, addr,
3293 SPAPR_MEMORY_BLOCK_SIZE);
3294
3295 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err);
3296 if (local_err) {
3297 while (addr > addr_start) {
3298 addr -= SPAPR_MEMORY_BLOCK_SIZE;
3299 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3300 addr / SPAPR_MEMORY_BLOCK_SIZE);
3301 spapr_drc_detach(drc);<