Merge remote-tracking branch 'remotes/armbru/tags/pull-monitor-2019-08-21' into staging
[qemu.git] / hw / ppc / spapr.c
1 /*
2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
3 *
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 */
26
27 #include "qemu/osdep.h"
28 #include "qemu-common.h"
29 #include "qapi/error.h"
30 #include "qapi/visitor.h"
31 #include "sysemu/sysemu.h"
32 #include "sysemu/hostmem.h"
33 #include "sysemu/numa.h"
34 #include "sysemu/qtest.h"
35 #include "sysemu/reset.h"
36 #include "sysemu/runstate.h"
37 #include "qemu/log.h"
38 #include "hw/fw-path-provider.h"
39 #include "elf.h"
40 #include "net/net.h"
41 #include "sysemu/device_tree.h"
42 #include "sysemu/cpus.h"
43 #include "sysemu/hw_accel.h"
44 #include "kvm_ppc.h"
45 #include "migration/misc.h"
46 #include "migration/qemu-file-types.h"
47 #include "migration/global_state.h"
48 #include "migration/register.h"
49 #include "mmu-hash64.h"
50 #include "mmu-book3s-v3.h"
51 #include "cpu-models.h"
52 #include "hw/core/cpu.h"
53
54 #include "hw/boards.h"
55 #include "hw/ppc/ppc.h"
56 #include "hw/loader.h"
57
58 #include "hw/ppc/fdt.h"
59 #include "hw/ppc/spapr.h"
60 #include "hw/ppc/spapr_vio.h"
61 #include "hw/qdev-properties.h"
62 #include "hw/pci-host/spapr.h"
63 #include "hw/pci/msi.h"
64
65 #include "hw/pci/pci.h"
66 #include "hw/scsi/scsi.h"
67 #include "hw/virtio/virtio-scsi.h"
68 #include "hw/virtio/vhost-scsi-common.h"
69
70 #include "exec/address-spaces.h"
71 #include "exec/ram_addr.h"
72 #include "hw/usb.h"
73 #include "qemu/config-file.h"
74 #include "qemu/error-report.h"
75 #include "trace.h"
76 #include "hw/nmi.h"
77 #include "hw/intc/intc.h"
78
79 #include "qemu/cutils.h"
80 #include "hw/ppc/spapr_cpu_core.h"
81 #include "hw/mem/memory-device.h"
82 #include "hw/ppc/spapr_tpm_proxy.h"
83
84 #include <libfdt.h>
85
86 /* SLOF memory layout:
87 *
88 * SLOF raw image loaded at 0, copies its romfs right below the flat
89 * device-tree, then position SLOF itself 31M below that
90 *
91 * So we set FW_OVERHEAD to 40MB which should account for all of that
92 * and more
93 *
94 * We load our kernel at 4M, leaving space for SLOF initial image
95 */
96 #define FDT_MAX_SIZE 0x100000
97 #define RTAS_MAX_SIZE 0x10000
98 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */
99 #define FW_MAX_SIZE 0x400000
100 #define FW_FILE_NAME "slof.bin"
101 #define FW_OVERHEAD 0x2800000
102 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
103
104 #define MIN_RMA_SLOF 128UL
105
106 #define PHANDLE_INTC 0x00001111
107
108 /* These two functions implement the VCPU id numbering: one to compute them
109 * all and one to identify thread 0 of a VCORE. Any change to the first one
110 * is likely to have an impact on the second one, so let's keep them close.
111 */
112 static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index)
113 {
114 MachineState *ms = MACHINE(spapr);
115 unsigned int smp_threads = ms->smp.threads;
116
117 assert(spapr->vsmt);
118 return
119 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads;
120 }
121 static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr,
122 PowerPCCPU *cpu)
123 {
124 assert(spapr->vsmt);
125 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0;
126 }
127
128 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque)
129 {
130 /* Dummy entries correspond to unused ICPState objects in older QEMUs,
131 * and newer QEMUs don't even have them. In both cases, we don't want
132 * to send anything on the wire.
133 */
134 return false;
135 }
136
137 static const VMStateDescription pre_2_10_vmstate_dummy_icp = {
138 .name = "icp/server",
139 .version_id = 1,
140 .minimum_version_id = 1,
141 .needed = pre_2_10_vmstate_dummy_icp_needed,
142 .fields = (VMStateField[]) {
143 VMSTATE_UNUSED(4), /* uint32_t xirr */
144 VMSTATE_UNUSED(1), /* uint8_t pending_priority */
145 VMSTATE_UNUSED(1), /* uint8_t mfrr */
146 VMSTATE_END_OF_LIST()
147 },
148 };
149
150 static void pre_2_10_vmstate_register_dummy_icp(int i)
151 {
152 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp,
153 (void *)(uintptr_t) i);
154 }
155
156 static void pre_2_10_vmstate_unregister_dummy_icp(int i)
157 {
158 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp,
159 (void *)(uintptr_t) i);
160 }
161
162 int spapr_max_server_number(SpaprMachineState *spapr)
163 {
164 MachineState *ms = MACHINE(spapr);
165
166 assert(spapr->vsmt);
167 return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads);
168 }
169
170 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
171 int smt_threads)
172 {
173 int i, ret = 0;
174 uint32_t servers_prop[smt_threads];
175 uint32_t gservers_prop[smt_threads * 2];
176 int index = spapr_get_vcpu_id(cpu);
177
178 if (cpu->compat_pvr) {
179 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr);
180 if (ret < 0) {
181 return ret;
182 }
183 }
184
185 /* Build interrupt servers and gservers properties */
186 for (i = 0; i < smt_threads; i++) {
187 servers_prop[i] = cpu_to_be32(index + i);
188 /* Hack, direct the group queues back to cpu 0 */
189 gservers_prop[i*2] = cpu_to_be32(index + i);
190 gservers_prop[i*2 + 1] = 0;
191 }
192 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
193 servers_prop, sizeof(servers_prop));
194 if (ret < 0) {
195 return ret;
196 }
197 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s",
198 gservers_prop, sizeof(gservers_prop));
199
200 return ret;
201 }
202
203 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu)
204 {
205 int index = spapr_get_vcpu_id(cpu);
206 uint32_t associativity[] = {cpu_to_be32(0x5),
207 cpu_to_be32(0x0),
208 cpu_to_be32(0x0),
209 cpu_to_be32(0x0),
210 cpu_to_be32(cpu->node_id),
211 cpu_to_be32(index)};
212
213 /* Advertise NUMA via ibm,associativity */
214 return fdt_setprop(fdt, offset, "ibm,associativity", associativity,
215 sizeof(associativity));
216 }
217
218 /* Populate the "ibm,pa-features" property */
219 static void spapr_populate_pa_features(SpaprMachineState *spapr,
220 PowerPCCPU *cpu,
221 void *fdt, int offset,
222 bool legacy_guest)
223 {
224 uint8_t pa_features_206[] = { 6, 0,
225 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
226 uint8_t pa_features_207[] = { 24, 0,
227 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
228 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
229 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
230 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
231 uint8_t pa_features_300[] = { 66, 0,
232 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
233 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */
234 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */
235 /* 6: DS207 */
236 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
237 /* 16: Vector */
238 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
239 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */
240 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
241 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
242 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
243 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */
244 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
245 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */
246 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */
247 /* 42: PM, 44: PC RA, 46: SC vec'd */
248 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
249 /* 48: SIMD, 50: QP BFP, 52: String */
250 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
251 /* 54: DecFP, 56: DecI, 58: SHA */
252 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
253 /* 60: NM atomic, 62: RNG */
254 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
255 };
256 uint8_t *pa_features = NULL;
257 size_t pa_size;
258
259 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) {
260 pa_features = pa_features_206;
261 pa_size = sizeof(pa_features_206);
262 }
263 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) {
264 pa_features = pa_features_207;
265 pa_size = sizeof(pa_features_207);
266 }
267 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) {
268 pa_features = pa_features_300;
269 pa_size = sizeof(pa_features_300);
270 }
271 if (!pa_features) {
272 return;
273 }
274
275 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) {
276 /*
277 * Note: we keep CI large pages off by default because a 64K capable
278 * guest provisioned with large pages might otherwise try to map a qemu
279 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
280 * even if that qemu runs on a 4k host.
281 * We dd this bit back here if we are confident this is not an issue
282 */
283 pa_features[3] |= 0x20;
284 }
285 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) {
286 pa_features[24] |= 0x80; /* Transactional memory support */
287 }
288 if (legacy_guest && pa_size > 40) {
289 /* Workaround for broken kernels that attempt (guest) radix
290 * mode when they can't handle it, if they see the radix bit set
291 * in pa-features. So hide it from them. */
292 pa_features[40 + 2] &= ~0x80; /* Radix MMU */
293 }
294
295 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size)));
296 }
297
298 static int spapr_fixup_cpu_dt(void *fdt, SpaprMachineState *spapr)
299 {
300 MachineState *ms = MACHINE(spapr);
301 int ret = 0, offset, cpus_offset;
302 CPUState *cs;
303 char cpu_model[32];
304 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
305
306 CPU_FOREACH(cs) {
307 PowerPCCPU *cpu = POWERPC_CPU(cs);
308 DeviceClass *dc = DEVICE_GET_CLASS(cs);
309 int index = spapr_get_vcpu_id(cpu);
310 int compat_smt = MIN(ms->smp.threads, ppc_compat_max_vthreads(cpu));
311
312 if (!spapr_is_thread0_in_vcore(spapr, cpu)) {
313 continue;
314 }
315
316 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index);
317
318 cpus_offset = fdt_path_offset(fdt, "/cpus");
319 if (cpus_offset < 0) {
320 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
321 if (cpus_offset < 0) {
322 return cpus_offset;
323 }
324 }
325 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model);
326 if (offset < 0) {
327 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model);
328 if (offset < 0) {
329 return offset;
330 }
331 }
332
333 ret = fdt_setprop(fdt, offset, "ibm,pft-size",
334 pft_size_prop, sizeof(pft_size_prop));
335 if (ret < 0) {
336 return ret;
337 }
338
339 if (nb_numa_nodes > 1) {
340 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cpu);
341 if (ret < 0) {
342 return ret;
343 }
344 }
345
346 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt);
347 if (ret < 0) {
348 return ret;
349 }
350
351 spapr_populate_pa_features(spapr, cpu, fdt, offset,
352 spapr->cas_legacy_guest_workaround);
353 }
354 return ret;
355 }
356
357 static hwaddr spapr_node0_size(MachineState *machine)
358 {
359 if (nb_numa_nodes) {
360 int i;
361 for (i = 0; i < nb_numa_nodes; ++i) {
362 if (numa_info[i].node_mem) {
363 return MIN(pow2floor(numa_info[i].node_mem),
364 machine->ram_size);
365 }
366 }
367 }
368 return machine->ram_size;
369 }
370
371 static void add_str(GString *s, const gchar *s1)
372 {
373 g_string_append_len(s, s1, strlen(s1) + 1);
374 }
375
376 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start,
377 hwaddr size)
378 {
379 uint32_t associativity[] = {
380 cpu_to_be32(0x4), /* length */
381 cpu_to_be32(0x0), cpu_to_be32(0x0),
382 cpu_to_be32(0x0), cpu_to_be32(nodeid)
383 };
384 char mem_name[32];
385 uint64_t mem_reg_property[2];
386 int off;
387
388 mem_reg_property[0] = cpu_to_be64(start);
389 mem_reg_property[1] = cpu_to_be64(size);
390
391 sprintf(mem_name, "memory@" TARGET_FMT_lx, start);
392 off = fdt_add_subnode(fdt, 0, mem_name);
393 _FDT(off);
394 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
395 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
396 sizeof(mem_reg_property))));
397 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
398 sizeof(associativity))));
399 return off;
400 }
401
402 static int spapr_populate_memory(SpaprMachineState *spapr, void *fdt)
403 {
404 MachineState *machine = MACHINE(spapr);
405 hwaddr mem_start, node_size;
406 int i, nb_nodes = nb_numa_nodes;
407 NodeInfo *nodes = numa_info;
408 NodeInfo ramnode;
409
410 /* No NUMA nodes, assume there is just one node with whole RAM */
411 if (!nb_numa_nodes) {
412 nb_nodes = 1;
413 ramnode.node_mem = machine->ram_size;
414 nodes = &ramnode;
415 }
416
417 for (i = 0, mem_start = 0; i < nb_nodes; ++i) {
418 if (!nodes[i].node_mem) {
419 continue;
420 }
421 if (mem_start >= machine->ram_size) {
422 node_size = 0;
423 } else {
424 node_size = nodes[i].node_mem;
425 if (node_size > machine->ram_size - mem_start) {
426 node_size = machine->ram_size - mem_start;
427 }
428 }
429 if (!mem_start) {
430 /* spapr_machine_init() checks for rma_size <= node0_size
431 * already */
432 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size);
433 mem_start += spapr->rma_size;
434 node_size -= spapr->rma_size;
435 }
436 for ( ; node_size; ) {
437 hwaddr sizetmp = pow2floor(node_size);
438
439 /* mem_start != 0 here */
440 if (ctzl(mem_start) < ctzl(sizetmp)) {
441 sizetmp = 1ULL << ctzl(mem_start);
442 }
443
444 spapr_populate_memory_node(fdt, i, mem_start, sizetmp);
445 node_size -= sizetmp;
446 mem_start += sizetmp;
447 }
448 }
449
450 return 0;
451 }
452
453 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
454 SpaprMachineState *spapr)
455 {
456 MachineState *ms = MACHINE(spapr);
457 PowerPCCPU *cpu = POWERPC_CPU(cs);
458 CPUPPCState *env = &cpu->env;
459 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
460 int index = spapr_get_vcpu_id(cpu);
461 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
462 0xffffffff, 0xffffffff};
463 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq()
464 : SPAPR_TIMEBASE_FREQ;
465 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
466 uint32_t page_sizes_prop[64];
467 size_t page_sizes_prop_size;
468 unsigned int smp_threads = ms->smp.threads;
469 uint32_t vcpus_per_socket = smp_threads * ms->smp.cores;
470 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
471 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu));
472 SpaprDrc *drc;
473 int drc_index;
474 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ];
475 int i;
476
477 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index);
478 if (drc) {
479 drc_index = spapr_drc_index(drc);
480 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)));
481 }
482
483 _FDT((fdt_setprop_cell(fdt, offset, "reg", index)));
484 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
485
486 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
487 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
488 env->dcache_line_size)));
489 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
490 env->dcache_line_size)));
491 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
492 env->icache_line_size)));
493 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
494 env->icache_line_size)));
495
496 if (pcc->l1_dcache_size) {
497 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
498 pcc->l1_dcache_size)));
499 } else {
500 warn_report("Unknown L1 dcache size for cpu");
501 }
502 if (pcc->l1_icache_size) {
503 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
504 pcc->l1_icache_size)));
505 } else {
506 warn_report("Unknown L1 icache size for cpu");
507 }
508
509 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
510 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
511 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size)));
512 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size)));
513 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
514 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
515
516 if (env->spr_cb[SPR_PURR].oea_read) {
517 _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1)));
518 }
519 if (env->spr_cb[SPR_SPURR].oea_read) {
520 _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1)));
521 }
522
523 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) {
524 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
525 segs, sizeof(segs))));
526 }
527
528 /* Advertise VSX (vector extensions) if available
529 * 1 == VMX / Altivec available
530 * 2 == VSX available
531 *
532 * Only CPUs for which we create core types in spapr_cpu_core.c
533 * are possible, and all of those have VMX */
534 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) {
535 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2)));
536 } else {
537 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1)));
538 }
539
540 /* Advertise DFP (Decimal Floating Point) if available
541 * 0 / no property == no DFP
542 * 1 == DFP available */
543 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) {
544 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
545 }
546
547 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop,
548 sizeof(page_sizes_prop));
549 if (page_sizes_prop_size) {
550 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
551 page_sizes_prop, page_sizes_prop_size)));
552 }
553
554 spapr_populate_pa_features(spapr, cpu, fdt, offset, false);
555
556 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
557 cs->cpu_index / vcpus_per_socket)));
558
559 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size",
560 pft_size_prop, sizeof(pft_size_prop))));
561
562 if (nb_numa_nodes > 1) {
563 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu));
564 }
565
566 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt));
567
568 if (pcc->radix_page_info) {
569 for (i = 0; i < pcc->radix_page_info->count; i++) {
570 radix_AP_encodings[i] =
571 cpu_to_be32(pcc->radix_page_info->entries[i]);
572 }
573 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings",
574 radix_AP_encodings,
575 pcc->radix_page_info->count *
576 sizeof(radix_AP_encodings[0]))));
577 }
578
579 /*
580 * We set this property to let the guest know that it can use the large
581 * decrementer and its width in bits.
582 */
583 if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF)
584 _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits",
585 pcc->lrg_decr_bits)));
586 }
587
588 static void spapr_populate_cpus_dt_node(void *fdt, SpaprMachineState *spapr)
589 {
590 CPUState **rev;
591 CPUState *cs;
592 int n_cpus;
593 int cpus_offset;
594 char *nodename;
595 int i;
596
597 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
598 _FDT(cpus_offset);
599 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
600 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
601
602 /*
603 * We walk the CPUs in reverse order to ensure that CPU DT nodes
604 * created by fdt_add_subnode() end up in the right order in FDT
605 * for the guest kernel the enumerate the CPUs correctly.
606 *
607 * The CPU list cannot be traversed in reverse order, so we need
608 * to do extra work.
609 */
610 n_cpus = 0;
611 rev = NULL;
612 CPU_FOREACH(cs) {
613 rev = g_renew(CPUState *, rev, n_cpus + 1);
614 rev[n_cpus++] = cs;
615 }
616
617 for (i = n_cpus - 1; i >= 0; i--) {
618 CPUState *cs = rev[i];
619 PowerPCCPU *cpu = POWERPC_CPU(cs);
620 int index = spapr_get_vcpu_id(cpu);
621 DeviceClass *dc = DEVICE_GET_CLASS(cs);
622 int offset;
623
624 if (!spapr_is_thread0_in_vcore(spapr, cpu)) {
625 continue;
626 }
627
628 nodename = g_strdup_printf("%s@%x", dc->fw_name, index);
629 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
630 g_free(nodename);
631 _FDT(offset);
632 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
633 }
634
635 g_free(rev);
636 }
637
638 static int spapr_rng_populate_dt(void *fdt)
639 {
640 int node;
641 int ret;
642
643 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities");
644 if (node <= 0) {
645 return -1;
646 }
647 ret = fdt_setprop_string(fdt, node, "device_type",
648 "ibm,platform-facilities");
649 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1);
650 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0);
651
652 node = fdt_add_subnode(fdt, node, "ibm,random-v1");
653 if (node <= 0) {
654 return -1;
655 }
656 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random");
657
658 return ret ? -1 : 0;
659 }
660
661 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr)
662 {
663 MemoryDeviceInfoList *info;
664
665 for (info = list; info; info = info->next) {
666 MemoryDeviceInfo *value = info->value;
667
668 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) {
669 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data;
670
671 if (addr >= pcdimm_info->addr &&
672 addr < (pcdimm_info->addr + pcdimm_info->size)) {
673 return pcdimm_info->node;
674 }
675 }
676 }
677
678 return -1;
679 }
680
681 struct sPAPRDrconfCellV2 {
682 uint32_t seq_lmbs;
683 uint64_t base_addr;
684 uint32_t drc_index;
685 uint32_t aa_index;
686 uint32_t flags;
687 } QEMU_PACKED;
688
689 typedef struct DrconfCellQueue {
690 struct sPAPRDrconfCellV2 cell;
691 QSIMPLEQ_ENTRY(DrconfCellQueue) entry;
692 } DrconfCellQueue;
693
694 static DrconfCellQueue *
695 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr,
696 uint32_t drc_index, uint32_t aa_index,
697 uint32_t flags)
698 {
699 DrconfCellQueue *elem;
700
701 elem = g_malloc0(sizeof(*elem));
702 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs);
703 elem->cell.base_addr = cpu_to_be64(base_addr);
704 elem->cell.drc_index = cpu_to_be32(drc_index);
705 elem->cell.aa_index = cpu_to_be32(aa_index);
706 elem->cell.flags = cpu_to_be32(flags);
707
708 return elem;
709 }
710
711 /* ibm,dynamic-memory-v2 */
712 static int spapr_populate_drmem_v2(SpaprMachineState *spapr, void *fdt,
713 int offset, MemoryDeviceInfoList *dimms)
714 {
715 MachineState *machine = MACHINE(spapr);
716 uint8_t *int_buf, *cur_index;
717 int ret;
718 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
719 uint64_t addr, cur_addr, size;
720 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size);
721 uint64_t mem_end = machine->device_memory->base +
722 memory_region_size(&machine->device_memory->mr);
723 uint32_t node, buf_len, nr_entries = 0;
724 SpaprDrc *drc;
725 DrconfCellQueue *elem, *next;
726 MemoryDeviceInfoList *info;
727 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue
728 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue);
729
730 /* Entry to cover RAM and the gap area */
731 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1,
732 SPAPR_LMB_FLAGS_RESERVED |
733 SPAPR_LMB_FLAGS_DRC_INVALID);
734 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
735 nr_entries++;
736
737 cur_addr = machine->device_memory->base;
738 for (info = dimms; info; info = info->next) {
739 PCDIMMDeviceInfo *di = info->value->u.dimm.data;
740
741 addr = di->addr;
742 size = di->size;
743 node = di->node;
744
745 /* Entry for hot-pluggable area */
746 if (cur_addr < addr) {
747 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size);
748 g_assert(drc);
749 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size,
750 cur_addr, spapr_drc_index(drc), -1, 0);
751 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
752 nr_entries++;
753 }
754
755 /* Entry for DIMM */
756 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size);
757 g_assert(drc);
758 elem = spapr_get_drconf_cell(size / lmb_size, addr,
759 spapr_drc_index(drc), node,
760 SPAPR_LMB_FLAGS_ASSIGNED);
761 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
762 nr_entries++;
763 cur_addr = addr + size;
764 }
765
766 /* Entry for remaining hotpluggable area */
767 if (cur_addr < mem_end) {
768 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size);
769 g_assert(drc);
770 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size,
771 cur_addr, spapr_drc_index(drc), -1, 0);
772 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
773 nr_entries++;
774 }
775
776 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t);
777 int_buf = cur_index = g_malloc0(buf_len);
778 *(uint32_t *)int_buf = cpu_to_be32(nr_entries);
779 cur_index += sizeof(nr_entries);
780
781 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) {
782 memcpy(cur_index, &elem->cell, sizeof(elem->cell));
783 cur_index += sizeof(elem->cell);
784 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry);
785 g_free(elem);
786 }
787
788 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len);
789 g_free(int_buf);
790 if (ret < 0) {
791 return -1;
792 }
793 return 0;
794 }
795
796 /* ibm,dynamic-memory */
797 static int spapr_populate_drmem_v1(SpaprMachineState *spapr, void *fdt,
798 int offset, MemoryDeviceInfoList *dimms)
799 {
800 MachineState *machine = MACHINE(spapr);
801 int i, ret;
802 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
803 uint32_t device_lmb_start = machine->device_memory->base / lmb_size;
804 uint32_t nr_lmbs = (machine->device_memory->base +
805 memory_region_size(&machine->device_memory->mr)) /
806 lmb_size;
807 uint32_t *int_buf, *cur_index, buf_len;
808
809 /*
810 * Allocate enough buffer size to fit in ibm,dynamic-memory
811 */
812 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t);
813 cur_index = int_buf = g_malloc0(buf_len);
814 int_buf[0] = cpu_to_be32(nr_lmbs);
815 cur_index++;
816 for (i = 0; i < nr_lmbs; i++) {
817 uint64_t addr = i * lmb_size;
818 uint32_t *dynamic_memory = cur_index;
819
820 if (i >= device_lmb_start) {
821 SpaprDrc *drc;
822
823 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i);
824 g_assert(drc);
825
826 dynamic_memory[0] = cpu_to_be32(addr >> 32);
827 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
828 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc));
829 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
830 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr));
831 if (memory_region_present(get_system_memory(), addr)) {
832 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED);
833 } else {
834 dynamic_memory[5] = cpu_to_be32(0);
835 }
836 } else {
837 /*
838 * LMB information for RMA, boot time RAM and gap b/n RAM and
839 * device memory region -- all these are marked as reserved
840 * and as having no valid DRC.
841 */
842 dynamic_memory[0] = cpu_to_be32(addr >> 32);
843 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
844 dynamic_memory[2] = cpu_to_be32(0);
845 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
846 dynamic_memory[4] = cpu_to_be32(-1);
847 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED |
848 SPAPR_LMB_FLAGS_DRC_INVALID);
849 }
850
851 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE;
852 }
853 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len);
854 g_free(int_buf);
855 if (ret < 0) {
856 return -1;
857 }
858 return 0;
859 }
860
861 /*
862 * Adds ibm,dynamic-reconfiguration-memory node.
863 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
864 * of this device tree node.
865 */
866 static int spapr_populate_drconf_memory(SpaprMachineState *spapr, void *fdt)
867 {
868 MachineState *machine = MACHINE(spapr);
869 int ret, i, offset;
870 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
871 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)};
872 uint32_t *int_buf, *cur_index, buf_len;
873 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1;
874 MemoryDeviceInfoList *dimms = NULL;
875
876 /*
877 * Don't create the node if there is no device memory
878 */
879 if (machine->ram_size == machine->maxram_size) {
880 return 0;
881 }
882
883 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory");
884
885 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size,
886 sizeof(prop_lmb_size));
887 if (ret < 0) {
888 return ret;
889 }
890
891 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff);
892 if (ret < 0) {
893 return ret;
894 }
895
896 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0);
897 if (ret < 0) {
898 return ret;
899 }
900
901 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */
902 dimms = qmp_memory_device_list();
903 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) {
904 ret = spapr_populate_drmem_v2(spapr, fdt, offset, dimms);
905 } else {
906 ret = spapr_populate_drmem_v1(spapr, fdt, offset, dimms);
907 }
908 qapi_free_MemoryDeviceInfoList(dimms);
909
910 if (ret < 0) {
911 return ret;
912 }
913
914 /* ibm,associativity-lookup-arrays */
915 buf_len = (nr_nodes * 4 + 2) * sizeof(uint32_t);
916 cur_index = int_buf = g_malloc0(buf_len);
917 int_buf[0] = cpu_to_be32(nr_nodes);
918 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */
919 cur_index += 2;
920 for (i = 0; i < nr_nodes; i++) {
921 uint32_t associativity[] = {
922 cpu_to_be32(0x0),
923 cpu_to_be32(0x0),
924 cpu_to_be32(0x0),
925 cpu_to_be32(i)
926 };
927 memcpy(cur_index, associativity, sizeof(associativity));
928 cur_index += 4;
929 }
930 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf,
931 (cur_index - int_buf) * sizeof(uint32_t));
932 g_free(int_buf);
933
934 return ret;
935 }
936
937 static int spapr_dt_cas_updates(SpaprMachineState *spapr, void *fdt,
938 SpaprOptionVector *ov5_updates)
939 {
940 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
941 int ret = 0, offset;
942
943 /* Generate ibm,dynamic-reconfiguration-memory node if required */
944 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) {
945 g_assert(smc->dr_lmb_enabled);
946 ret = spapr_populate_drconf_memory(spapr, fdt);
947 if (ret) {
948 goto out;
949 }
950 }
951
952 offset = fdt_path_offset(fdt, "/chosen");
953 if (offset < 0) {
954 offset = fdt_add_subnode(fdt, 0, "chosen");
955 if (offset < 0) {
956 return offset;
957 }
958 }
959 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas,
960 "ibm,architecture-vec-5");
961
962 out:
963 return ret;
964 }
965
966 static bool spapr_hotplugged_dev_before_cas(void)
967 {
968 Object *drc_container, *obj;
969 ObjectProperty *prop;
970 ObjectPropertyIterator iter;
971
972 drc_container = container_get(object_get_root(), "/dr-connector");
973 object_property_iter_init(&iter, drc_container);
974 while ((prop = object_property_iter_next(&iter))) {
975 if (!strstart(prop->type, "link<", NULL)) {
976 continue;
977 }
978 obj = object_property_get_link(drc_container, prop->name, NULL);
979 if (spapr_drc_needed(obj)) {
980 return true;
981 }
982 }
983 return false;
984 }
985
986 int spapr_h_cas_compose_response(SpaprMachineState *spapr,
987 target_ulong addr, target_ulong size,
988 SpaprOptionVector *ov5_updates)
989 {
990 void *fdt, *fdt_skel;
991 SpaprDeviceTreeUpdateHeader hdr = { .version_id = 1 };
992
993 if (spapr_hotplugged_dev_before_cas()) {
994 return 1;
995 }
996
997 if (size < sizeof(hdr) || size > FW_MAX_SIZE) {
998 error_report("SLOF provided an unexpected CAS buffer size "
999 TARGET_FMT_lu " (min: %zu, max: %u)",
1000 size, sizeof(hdr), FW_MAX_SIZE);
1001 exit(EXIT_FAILURE);
1002 }
1003
1004 size -= sizeof(hdr);
1005
1006 /* Create skeleton */
1007 fdt_skel = g_malloc0(size);
1008 _FDT((fdt_create(fdt_skel, size)));
1009 _FDT((fdt_finish_reservemap(fdt_skel)));
1010 _FDT((fdt_begin_node(fdt_skel, "")));
1011 _FDT((fdt_end_node(fdt_skel)));
1012 _FDT((fdt_finish(fdt_skel)));
1013 fdt = g_malloc0(size);
1014 _FDT((fdt_open_into(fdt_skel, fdt, size)));
1015 g_free(fdt_skel);
1016
1017 /* Fixup cpu nodes */
1018 _FDT((spapr_fixup_cpu_dt(fdt, spapr)));
1019
1020 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) {
1021 return -1;
1022 }
1023
1024 /* Pack resulting tree */
1025 _FDT((fdt_pack(fdt)));
1026
1027 if (fdt_totalsize(fdt) + sizeof(hdr) > size) {
1028 trace_spapr_cas_failed(size);
1029 return -1;
1030 }
1031
1032 cpu_physical_memory_write(addr, &hdr, sizeof(hdr));
1033 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt));
1034 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr));
1035 g_free(fdt);
1036
1037 return 0;
1038 }
1039
1040 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt)
1041 {
1042 MachineState *ms = MACHINE(spapr);
1043 int rtas;
1044 GString *hypertas = g_string_sized_new(256);
1045 GString *qemu_hypertas = g_string_sized_new(256);
1046 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) };
1047 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base +
1048 memory_region_size(&MACHINE(spapr)->device_memory->mr);
1049 uint32_t lrdr_capacity[] = {
1050 cpu_to_be32(max_device_addr >> 32),
1051 cpu_to_be32(max_device_addr & 0xffffffff),
1052 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE),
1053 cpu_to_be32(ms->smp.max_cpus / ms->smp.threads),
1054 };
1055 uint32_t maxdomain = cpu_to_be32(spapr->gpu_numa_id > 1 ? 1 : 0);
1056 uint32_t maxdomains[] = {
1057 cpu_to_be32(4),
1058 maxdomain,
1059 maxdomain,
1060 maxdomain,
1061 cpu_to_be32(spapr->gpu_numa_id),
1062 };
1063
1064 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas"));
1065
1066 /* hypertas */
1067 add_str(hypertas, "hcall-pft");
1068 add_str(hypertas, "hcall-term");
1069 add_str(hypertas, "hcall-dabr");
1070 add_str(hypertas, "hcall-interrupt");
1071 add_str(hypertas, "hcall-tce");
1072 add_str(hypertas, "hcall-vio");
1073 add_str(hypertas, "hcall-splpar");
1074 add_str(hypertas, "hcall-join");
1075 add_str(hypertas, "hcall-bulk");
1076 add_str(hypertas, "hcall-set-mode");
1077 add_str(hypertas, "hcall-sprg0");
1078 add_str(hypertas, "hcall-copy");
1079 add_str(hypertas, "hcall-debug");
1080 add_str(hypertas, "hcall-vphn");
1081 add_str(qemu_hypertas, "hcall-memop1");
1082
1083 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
1084 add_str(hypertas, "hcall-multi-tce");
1085 }
1086
1087 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) {
1088 add_str(hypertas, "hcall-hpt-resize");
1089 }
1090
1091 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions",
1092 hypertas->str, hypertas->len));
1093 g_string_free(hypertas, TRUE);
1094 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions",
1095 qemu_hypertas->str, qemu_hypertas->len));
1096 g_string_free(qemu_hypertas, TRUE);
1097
1098 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points",
1099 refpoints, sizeof(refpoints)));
1100
1101 _FDT(fdt_setprop(fdt, rtas, "ibm,max-associativity-domains",
1102 maxdomains, sizeof(maxdomains)));
1103
1104 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max",
1105 RTAS_ERROR_LOG_MAX));
1106 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate",
1107 RTAS_EVENT_SCAN_RATE));
1108
1109 g_assert(msi_nonbroken);
1110 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0));
1111
1112 /*
1113 * According to PAPR, rtas ibm,os-term does not guarantee a return
1114 * back to the guest cpu.
1115 *
1116 * While an additional ibm,extended-os-term property indicates
1117 * that rtas call return will always occur. Set this property.
1118 */
1119 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0));
1120
1121 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity",
1122 lrdr_capacity, sizeof(lrdr_capacity)));
1123
1124 spapr_dt_rtas_tokens(fdt, rtas);
1125 }
1126
1127 /*
1128 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU
1129 * and the XIVE features that the guest may request and thus the valid
1130 * values for bytes 23..26 of option vector 5:
1131 */
1132 static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt,
1133 int chosen)
1134 {
1135 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu);
1136
1137 char val[2 * 4] = {
1138 23, spapr->irq->ov5, /* Xive mode. */
1139 24, 0x00, /* Hash/Radix, filled in below. */
1140 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */
1141 26, 0x40, /* Radix options: GTSE == yes. */
1142 };
1143
1144 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0,
1145 first_ppc_cpu->compat_pvr)) {
1146 /*
1147 * If we're in a pre POWER9 compat mode then the guest should
1148 * do hash and use the legacy interrupt mode
1149 */
1150 val[1] = 0x00; /* XICS */
1151 val[3] = 0x00; /* Hash */
1152 } else if (kvm_enabled()) {
1153 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) {
1154 val[3] = 0x80; /* OV5_MMU_BOTH */
1155 } else if (kvmppc_has_cap_mmu_radix()) {
1156 val[3] = 0x40; /* OV5_MMU_RADIX_300 */
1157 } else {
1158 val[3] = 0x00; /* Hash */
1159 }
1160 } else {
1161 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */
1162 val[3] = 0xC0;
1163 }
1164 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support",
1165 val, sizeof(val)));
1166 }
1167
1168 static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt)
1169 {
1170 MachineState *machine = MACHINE(spapr);
1171 int chosen;
1172 const char *boot_device = machine->boot_order;
1173 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus);
1174 size_t cb = 0;
1175 char *bootlist = get_boot_devices_list(&cb);
1176
1177 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen"));
1178
1179 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline));
1180 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start",
1181 spapr->initrd_base));
1182 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end",
1183 spapr->initrd_base + spapr->initrd_size));
1184
1185 if (spapr->kernel_size) {
1186 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR),
1187 cpu_to_be64(spapr->kernel_size) };
1188
1189 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel",
1190 &kprop, sizeof(kprop)));
1191 if (spapr->kernel_le) {
1192 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0));
1193 }
1194 }
1195 if (boot_menu) {
1196 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu)));
1197 }
1198 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width));
1199 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height));
1200 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth));
1201
1202 if (cb && bootlist) {
1203 int i;
1204
1205 for (i = 0; i < cb; i++) {
1206 if (bootlist[i] == '\n') {
1207 bootlist[i] = ' ';
1208 }
1209 }
1210 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist));
1211 }
1212
1213 if (boot_device && strlen(boot_device)) {
1214 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device));
1215 }
1216
1217 if (!spapr->has_graphics && stdout_path) {
1218 /*
1219 * "linux,stdout-path" and "stdout" properties are deprecated by linux
1220 * kernel. New platforms should only use the "stdout-path" property. Set
1221 * the new property and continue using older property to remain
1222 * compatible with the existing firmware.
1223 */
1224 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path));
1225 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path));
1226 }
1227
1228 spapr_dt_ov5_platform_support(spapr, fdt, chosen);
1229
1230 g_free(stdout_path);
1231 g_free(bootlist);
1232 }
1233
1234 static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt)
1235 {
1236 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR
1237 * KVM to work under pHyp with some guest co-operation */
1238 int hypervisor;
1239 uint8_t hypercall[16];
1240
1241 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor"));
1242 /* indicate KVM hypercall interface */
1243 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm"));
1244 if (kvmppc_has_cap_fixup_hcalls()) {
1245 /*
1246 * Older KVM versions with older guest kernels were broken
1247 * with the magic page, don't allow the guest to map it.
1248 */
1249 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall,
1250 sizeof(hypercall))) {
1251 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions",
1252 hypercall, sizeof(hypercall)));
1253 }
1254 }
1255 }
1256
1257 static void *spapr_build_fdt(SpaprMachineState *spapr)
1258 {
1259 MachineState *machine = MACHINE(spapr);
1260 MachineClass *mc = MACHINE_GET_CLASS(machine);
1261 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
1262 int ret;
1263 void *fdt;
1264 SpaprPhbState *phb;
1265 char *buf;
1266
1267 fdt = g_malloc0(FDT_MAX_SIZE);
1268 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
1269
1270 /* Root node */
1271 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp"));
1272 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)"));
1273 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries"));
1274
1275 /* Guest UUID & Name*/
1276 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
1277 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf));
1278 if (qemu_uuid_set) {
1279 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf));
1280 }
1281 g_free(buf);
1282
1283 if (qemu_get_vm_name()) {
1284 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name",
1285 qemu_get_vm_name()));
1286 }
1287
1288 /* Host Model & Serial Number */
1289 if (spapr->host_model) {
1290 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model));
1291 } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) {
1292 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf));
1293 g_free(buf);
1294 }
1295
1296 if (spapr->host_serial) {
1297 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial));
1298 } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) {
1299 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf));
1300 g_free(buf);
1301 }
1302
1303 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2));
1304 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2));
1305
1306 /* /interrupt controller */
1307 spapr->irq->dt_populate(spapr, spapr_max_server_number(spapr), fdt,
1308 PHANDLE_INTC);
1309
1310 ret = spapr_populate_memory(spapr, fdt);
1311 if (ret < 0) {
1312 error_report("couldn't setup memory nodes in fdt");
1313 exit(1);
1314 }
1315
1316 /* /vdevice */
1317 spapr_dt_vdevice(spapr->vio_bus, fdt);
1318
1319 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) {
1320 ret = spapr_rng_populate_dt(fdt);
1321 if (ret < 0) {
1322 error_report("could not set up rng device in the fdt");
1323 exit(1);
1324 }
1325 }
1326
1327 QLIST_FOREACH(phb, &spapr->phbs, list) {
1328 ret = spapr_dt_phb(phb, PHANDLE_INTC, fdt, spapr->irq->nr_msis, NULL);
1329 if (ret < 0) {
1330 error_report("couldn't setup PCI devices in fdt");
1331 exit(1);
1332 }
1333 }
1334
1335 /* cpus */
1336 spapr_populate_cpus_dt_node(fdt, spapr);
1337
1338 if (smc->dr_lmb_enabled) {
1339 _FDT(spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB));
1340 }
1341
1342 if (mc->has_hotpluggable_cpus) {
1343 int offset = fdt_path_offset(fdt, "/cpus");
1344 ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU);
1345 if (ret < 0) {
1346 error_report("Couldn't set up CPU DR device tree properties");
1347 exit(1);
1348 }
1349 }
1350
1351 /* /event-sources */
1352 spapr_dt_events(spapr, fdt);
1353
1354 /* /rtas */
1355 spapr_dt_rtas(spapr, fdt);
1356
1357 /* /chosen */
1358 spapr_dt_chosen(spapr, fdt);
1359
1360 /* /hypervisor */
1361 if (kvm_enabled()) {
1362 spapr_dt_hypervisor(spapr, fdt);
1363 }
1364
1365 /* Build memory reserve map */
1366 if (spapr->kernel_size) {
1367 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size)));
1368 }
1369 if (spapr->initrd_size) {
1370 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size)));
1371 }
1372
1373 /* ibm,client-architecture-support updates */
1374 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas);
1375 if (ret < 0) {
1376 error_report("couldn't setup CAS properties fdt");
1377 exit(1);
1378 }
1379
1380 if (smc->dr_phb_enabled) {
1381 ret = spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_PHB);
1382 if (ret < 0) {
1383 error_report("Couldn't set up PHB DR device tree properties");
1384 exit(1);
1385 }
1386 }
1387
1388 return fdt;
1389 }
1390
1391 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
1392 {
1393 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
1394 }
1395
1396 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp,
1397 PowerPCCPU *cpu)
1398 {
1399 CPUPPCState *env = &cpu->env;
1400
1401 /* The TCG path should also be holding the BQL at this point */
1402 g_assert(qemu_mutex_iothread_locked());
1403
1404 if (msr_pr) {
1405 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1406 env->gpr[3] = H_PRIVILEGE;
1407 } else {
1408 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]);
1409 }
1410 }
1411
1412 struct LPCRSyncState {
1413 target_ulong value;
1414 target_ulong mask;
1415 };
1416
1417 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg)
1418 {
1419 struct LPCRSyncState *s = arg.host_ptr;
1420 PowerPCCPU *cpu = POWERPC_CPU(cs);
1421 CPUPPCState *env = &cpu->env;
1422 target_ulong lpcr;
1423
1424 cpu_synchronize_state(cs);
1425 lpcr = env->spr[SPR_LPCR];
1426 lpcr &= ~s->mask;
1427 lpcr |= s->value;
1428 ppc_store_lpcr(cpu, lpcr);
1429 }
1430
1431 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask)
1432 {
1433 CPUState *cs;
1434 struct LPCRSyncState s = {
1435 .value = value,
1436 .mask = mask
1437 };
1438 CPU_FOREACH(cs) {
1439 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s));
1440 }
1441 }
1442
1443 static void spapr_get_pate(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry)
1444 {
1445 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1446
1447 /* Copy PATE1:GR into PATE0:HR */
1448 entry->dw0 = spapr->patb_entry & PATE0_HR;
1449 entry->dw1 = spapr->patb_entry;
1450 }
1451
1452 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1453 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1454 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1455 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1456 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1457
1458 /*
1459 * Get the fd to access the kernel htab, re-opening it if necessary
1460 */
1461 static int get_htab_fd(SpaprMachineState *spapr)
1462 {
1463 Error *local_err = NULL;
1464
1465 if (spapr->htab_fd >= 0) {
1466 return spapr->htab_fd;
1467 }
1468
1469 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err);
1470 if (spapr->htab_fd < 0) {
1471 error_report_err(local_err);
1472 }
1473
1474 return spapr->htab_fd;
1475 }
1476
1477 void close_htab_fd(SpaprMachineState *spapr)
1478 {
1479 if (spapr->htab_fd >= 0) {
1480 close(spapr->htab_fd);
1481 }
1482 spapr->htab_fd = -1;
1483 }
1484
1485 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp)
1486 {
1487 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1488
1489 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1;
1490 }
1491
1492 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp)
1493 {
1494 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1495
1496 assert(kvm_enabled());
1497
1498 if (!spapr->htab) {
1499 return 0;
1500 }
1501
1502 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18);
1503 }
1504
1505 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp,
1506 hwaddr ptex, int n)
1507 {
1508 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1509 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64;
1510
1511 if (!spapr->htab) {
1512 /*
1513 * HTAB is controlled by KVM. Fetch into temporary buffer
1514 */
1515 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64);
1516 kvmppc_read_hptes(hptes, ptex, n);
1517 return hptes;
1518 }
1519
1520 /*
1521 * HTAB is controlled by QEMU. Just point to the internally
1522 * accessible PTEG.
1523 */
1524 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset);
1525 }
1526
1527 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp,
1528 const ppc_hash_pte64_t *hptes,
1529 hwaddr ptex, int n)
1530 {
1531 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1532
1533 if (!spapr->htab) {
1534 g_free((void *)hptes);
1535 }
1536
1537 /* Nothing to do for qemu managed HPT */
1538 }
1539
1540 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex,
1541 uint64_t pte0, uint64_t pte1)
1542 {
1543 SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp);
1544 hwaddr offset = ptex * HASH_PTE_SIZE_64;
1545
1546 if (!spapr->htab) {
1547 kvmppc_write_hpte(ptex, pte0, pte1);
1548 } else {
1549 if (pte0 & HPTE64_V_VALID) {
1550 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1);
1551 /*
1552 * When setting valid, we write PTE1 first. This ensures
1553 * proper synchronization with the reading code in
1554 * ppc_hash64_pteg_search()
1555 */
1556 smp_wmb();
1557 stq_p(spapr->htab + offset, pte0);
1558 } else {
1559 stq_p(spapr->htab + offset, pte0);
1560 /*
1561 * When clearing it we set PTE0 first. This ensures proper
1562 * synchronization with the reading code in
1563 * ppc_hash64_pteg_search()
1564 */
1565 smp_wmb();
1566 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1);
1567 }
1568 }
1569 }
1570
1571 static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex,
1572 uint64_t pte1)
1573 {
1574 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 15;
1575 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1576
1577 if (!spapr->htab) {
1578 /* There should always be a hash table when this is called */
1579 error_report("spapr_hpte_set_c called with no hash table !");
1580 return;
1581 }
1582
1583 /* The HW performs a non-atomic byte update */
1584 stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80);
1585 }
1586
1587 static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex,
1588 uint64_t pte1)
1589 {
1590 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 14;
1591 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1592
1593 if (!spapr->htab) {
1594 /* There should always be a hash table when this is called */
1595 error_report("spapr_hpte_set_r called with no hash table !");
1596 return;
1597 }
1598
1599 /* The HW performs a non-atomic byte update */
1600 stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01);
1601 }
1602
1603 int spapr_hpt_shift_for_ramsize(uint64_t ramsize)
1604 {
1605 int shift;
1606
1607 /* We aim for a hash table of size 1/128 the size of RAM (rounded
1608 * up). The PAPR recommendation is actually 1/64 of RAM size, but
1609 * that's much more than is needed for Linux guests */
1610 shift = ctz64(pow2ceil(ramsize)) - 7;
1611 shift = MAX(shift, 18); /* Minimum architected size */
1612 shift = MIN(shift, 46); /* Maximum architected size */
1613 return shift;
1614 }
1615
1616 void spapr_free_hpt(SpaprMachineState *spapr)
1617 {
1618 g_free(spapr->htab);
1619 spapr->htab = NULL;
1620 spapr->htab_shift = 0;
1621 close_htab_fd(spapr);
1622 }
1623
1624 void spapr_reallocate_hpt(SpaprMachineState *spapr, int shift,
1625 Error **errp)
1626 {
1627 long rc;
1628
1629 /* Clean up any HPT info from a previous boot */
1630 spapr_free_hpt(spapr);
1631
1632 rc = kvmppc_reset_htab(shift);
1633 if (rc < 0) {
1634 /* kernel-side HPT needed, but couldn't allocate one */
1635 error_setg_errno(errp, errno,
1636 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1637 shift);
1638 /* This is almost certainly fatal, but if the caller really
1639 * wants to carry on with shift == 0, it's welcome to try */
1640 } else if (rc > 0) {
1641 /* kernel-side HPT allocated */
1642 if (rc != shift) {
1643 error_setg(errp,
1644 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1645 shift, rc);
1646 }
1647
1648 spapr->htab_shift = shift;
1649 spapr->htab = NULL;
1650 } else {
1651 /* kernel-side HPT not needed, allocate in userspace instead */
1652 size_t size = 1ULL << shift;
1653 int i;
1654
1655 spapr->htab = qemu_memalign(size, size);
1656 if (!spapr->htab) {
1657 error_setg_errno(errp, errno,
1658 "Could not allocate HPT of order %d", shift);
1659 return;
1660 }
1661
1662 memset(spapr->htab, 0, size);
1663 spapr->htab_shift = shift;
1664
1665 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) {
1666 DIRTY_HPTE(HPTE(spapr->htab, i));
1667 }
1668 }
1669 /* We're setting up a hash table, so that means we're not radix */
1670 spapr->patb_entry = 0;
1671 spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT);
1672 }
1673
1674 void spapr_setup_hpt_and_vrma(SpaprMachineState *spapr)
1675 {
1676 int hpt_shift;
1677
1678 if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED)
1679 || (spapr->cas_reboot
1680 && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) {
1681 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size);
1682 } else {
1683 uint64_t current_ram_size;
1684
1685 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size();
1686 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size);
1687 }
1688 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal);
1689
1690 if (spapr->vrma_adjust) {
1691 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(MACHINE(spapr)),
1692 spapr->htab_shift);
1693 }
1694 }
1695
1696 static int spapr_reset_drcs(Object *child, void *opaque)
1697 {
1698 SpaprDrc *drc =
1699 (SpaprDrc *) object_dynamic_cast(child,
1700 TYPE_SPAPR_DR_CONNECTOR);
1701
1702 if (drc) {
1703 spapr_drc_reset(drc);
1704 }
1705
1706 return 0;
1707 }
1708
1709 static void spapr_machine_reset(MachineState *machine)
1710 {
1711 SpaprMachineState *spapr = SPAPR_MACHINE(machine);
1712 PowerPCCPU *first_ppc_cpu;
1713 uint32_t rtas_limit;
1714 hwaddr rtas_addr, fdt_addr;
1715 void *fdt;
1716 int rc;
1717
1718 spapr_caps_apply(spapr);
1719
1720 first_ppc_cpu = POWERPC_CPU(first_cpu);
1721 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() &&
1722 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0,
1723 spapr->max_compat_pvr)) {
1724 /*
1725 * If using KVM with radix mode available, VCPUs can be started
1726 * without a HPT because KVM will start them in radix mode.
1727 * Set the GR bit in PATE so that we know there is no HPT.
1728 */
1729 spapr->patb_entry = PATE1_GR;
1730 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT);
1731 } else {
1732 spapr_setup_hpt_and_vrma(spapr);
1733 }
1734
1735 /*
1736 * NVLink2-connected GPU RAM needs to be placed on a separate NUMA node.
1737 * We assign a new numa ID per GPU in spapr_pci_collect_nvgpu() which is
1738 * called from vPHB reset handler so we initialize the counter here.
1739 * If no NUMA is configured from the QEMU side, we start from 1 as GPU RAM
1740 * must be equally distant from any other node.
1741 * The final value of spapr->gpu_numa_id is going to be written to
1742 * max-associativity-domains in spapr_build_fdt().
1743 */
1744 spapr->gpu_numa_id = MAX(1, nb_numa_nodes);
1745 qemu_devices_reset();
1746
1747 /*
1748 * If this reset wasn't generated by CAS, we should reset our
1749 * negotiated options and start from scratch
1750 */
1751 if (!spapr->cas_reboot) {
1752 spapr_ovec_cleanup(spapr->ov5_cas);
1753 spapr->ov5_cas = spapr_ovec_new();
1754
1755 ppc_set_compat(first_ppc_cpu, spapr->max_compat_pvr, &error_fatal);
1756 }
1757
1758 /*
1759 * This is fixing some of the default configuration of the XIVE
1760 * devices. To be called after the reset of the machine devices.
1761 */
1762 spapr_irq_reset(spapr, &error_fatal);
1763
1764 /*
1765 * There is no CAS under qtest. Simulate one to please the code that
1766 * depends on spapr->ov5_cas. This is especially needed to test device
1767 * unplug, so we do that before resetting the DRCs.
1768 */
1769 if (qtest_enabled()) {
1770 spapr_ovec_cleanup(spapr->ov5_cas);
1771 spapr->ov5_cas = spapr_ovec_clone(spapr->ov5);
1772 }
1773
1774 /* DRC reset may cause a device to be unplugged. This will cause troubles
1775 * if this device is used by another device (eg, a running vhost backend
1776 * will crash QEMU if the DIMM holding the vring goes away). To avoid such
1777 * situations, we reset DRCs after all devices have been reset.
1778 */
1779 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL);
1780
1781 spapr_clear_pending_events(spapr);
1782
1783 /*
1784 * We place the device tree and RTAS just below either the top of the RMA,
1785 * or just below 2GB, whichever is lower, so that it can be
1786 * processed with 32-bit real mode code if necessary
1787 */
1788 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR);
1789 rtas_addr = rtas_limit - RTAS_MAX_SIZE;
1790 fdt_addr = rtas_addr - FDT_MAX_SIZE;
1791
1792 fdt = spapr_build_fdt(spapr);
1793
1794 spapr_load_rtas(spapr, fdt, rtas_addr);
1795
1796 rc = fdt_pack(fdt);
1797
1798 /* Should only fail if we've built a corrupted tree */
1799 assert(rc == 0);
1800
1801 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) {
1802 error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
1803 fdt_totalsize(fdt), FDT_MAX_SIZE);
1804 exit(1);
1805 }
1806
1807 /* Load the fdt */
1808 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
1809 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
1810 g_free(spapr->fdt_blob);
1811 spapr->fdt_size = fdt_totalsize(fdt);
1812 spapr->fdt_initial_size = spapr->fdt_size;
1813 spapr->fdt_blob = fdt;
1814
1815 /* Set up the entry state */
1816 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, fdt_addr);
1817 first_ppc_cpu->env.gpr[5] = 0;
1818
1819 spapr->cas_reboot = false;
1820 }
1821
1822 static void spapr_create_nvram(SpaprMachineState *spapr)
1823 {
1824 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram");
1825 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
1826
1827 if (dinfo) {
1828 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
1829 &error_fatal);
1830 }
1831
1832 qdev_init_nofail(dev);
1833
1834 spapr->nvram = (struct SpaprNvram *)dev;
1835 }
1836
1837 static void spapr_rtc_create(SpaprMachineState *spapr)
1838 {
1839 object_initialize_child(OBJECT(spapr), "rtc",
1840 &spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC,
1841 &error_fatal, NULL);
1842 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized",
1843 &error_fatal);
1844 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc),
1845 "date", &error_fatal);
1846 }
1847
1848 /* Returns whether we want to use VGA or not */
1849 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp)
1850 {
1851 switch (vga_interface_type) {
1852 case VGA_NONE:
1853 return false;
1854 case VGA_DEVICE:
1855 return true;
1856 case VGA_STD:
1857 case VGA_VIRTIO:
1858 case VGA_CIRRUS:
1859 return pci_vga_init(pci_bus) != NULL;
1860 default:
1861 error_setg(errp,
1862 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1863 return false;
1864 }
1865 }
1866
1867 static int spapr_pre_load(void *opaque)
1868 {
1869 int rc;
1870
1871 rc = spapr_caps_pre_load(opaque);
1872 if (rc) {
1873 return rc;
1874 }
1875
1876 return 0;
1877 }
1878
1879 static int spapr_post_load(void *opaque, int version_id)
1880 {
1881 SpaprMachineState *spapr = (SpaprMachineState *)opaque;
1882 int err = 0;
1883
1884 err = spapr_caps_post_migration(spapr);
1885 if (err) {
1886 return err;
1887 }
1888
1889 /*
1890 * In earlier versions, there was no separate qdev for the PAPR
1891 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1892 * So when migrating from those versions, poke the incoming offset
1893 * value into the RTC device
1894 */
1895 if (version_id < 3) {
1896 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset);
1897 if (err) {
1898 return err;
1899 }
1900 }
1901
1902 if (kvm_enabled() && spapr->patb_entry) {
1903 PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
1904 bool radix = !!(spapr->patb_entry & PATE1_GR);
1905 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE);
1906
1907 /*
1908 * Update LPCR:HR and UPRT as they may not be set properly in
1909 * the stream
1910 */
1911 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0,
1912 LPCR_HR | LPCR_UPRT);
1913
1914 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry);
1915 if (err) {
1916 error_report("Process table config unsupported by the host");
1917 return -EINVAL;
1918 }
1919 }
1920
1921 err = spapr_irq_post_load(spapr, version_id);
1922 if (err) {
1923 return err;
1924 }
1925
1926 return err;
1927 }
1928
1929 static int spapr_pre_save(void *opaque)
1930 {
1931 int rc;
1932
1933 rc = spapr_caps_pre_save(opaque);
1934 if (rc) {
1935 return rc;
1936 }
1937
1938 return 0;
1939 }
1940
1941 static bool version_before_3(void *opaque, int version_id)
1942 {
1943 return version_id < 3;
1944 }
1945
1946 static bool spapr_pending_events_needed(void *opaque)
1947 {
1948 SpaprMachineState *spapr = (SpaprMachineState *)opaque;
1949 return !QTAILQ_EMPTY(&spapr->pending_events);
1950 }
1951
1952 static const VMStateDescription vmstate_spapr_event_entry = {
1953 .name = "spapr_event_log_entry",
1954 .version_id = 1,
1955 .minimum_version_id = 1,
1956 .fields = (VMStateField[]) {
1957 VMSTATE_UINT32(summary, SpaprEventLogEntry),
1958 VMSTATE_UINT32(extended_length, SpaprEventLogEntry),
1959 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0,
1960 NULL, extended_length),
1961 VMSTATE_END_OF_LIST()
1962 },
1963 };
1964
1965 static const VMStateDescription vmstate_spapr_pending_events = {
1966 .name = "spapr_pending_events",
1967 .version_id = 1,
1968 .minimum_version_id = 1,
1969 .needed = spapr_pending_events_needed,
1970 .fields = (VMStateField[]) {
1971 VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1,
1972 vmstate_spapr_event_entry, SpaprEventLogEntry, next),
1973 VMSTATE_END_OF_LIST()
1974 },
1975 };
1976
1977 static bool spapr_ov5_cas_needed(void *opaque)
1978 {
1979 SpaprMachineState *spapr = opaque;
1980 SpaprOptionVector *ov5_mask = spapr_ovec_new();
1981 SpaprOptionVector *ov5_legacy = spapr_ovec_new();
1982 SpaprOptionVector *ov5_removed = spapr_ovec_new();
1983 bool cas_needed;
1984
1985 /* Prior to the introduction of SpaprOptionVector, we had two option
1986 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY.
1987 * Both of these options encode machine topology into the device-tree
1988 * in such a way that the now-booted OS should still be able to interact
1989 * appropriately with QEMU regardless of what options were actually
1990 * negotiatied on the source side.
1991 *
1992 * As such, we can avoid migrating the CAS-negotiated options if these
1993 * are the only options available on the current machine/platform.
1994 * Since these are the only options available for pseries-2.7 and
1995 * earlier, this allows us to maintain old->new/new->old migration
1996 * compatibility.
1997 *
1998 * For QEMU 2.8+, there are additional CAS-negotiatable options available
1999 * via default pseries-2.8 machines and explicit command-line parameters.
2000 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware
2001 * of the actual CAS-negotiated values to continue working properly. For
2002 * example, availability of memory unplug depends on knowing whether
2003 * OV5_HP_EVT was negotiated via CAS.
2004 *
2005 * Thus, for any cases where the set of available CAS-negotiatable
2006 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we
2007 * include the CAS-negotiated options in the migration stream, unless
2008 * if they affect boot time behaviour only.
2009 */
2010 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY);
2011 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY);
2012 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2);
2013
2014 /* spapr_ovec_diff returns true if bits were removed. we avoid using
2015 * the mask itself since in the future it's possible "legacy" bits may be
2016 * removed via machine options, which could generate a false positive
2017 * that breaks migration.
2018 */
2019 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask);
2020 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy);
2021
2022 spapr_ovec_cleanup(ov5_mask);
2023 spapr_ovec_cleanup(ov5_legacy);
2024 spapr_ovec_cleanup(ov5_removed);
2025
2026 return cas_needed;
2027 }
2028
2029 static const VMStateDescription vmstate_spapr_ov5_cas = {
2030 .name = "spapr_option_vector_ov5_cas",
2031 .version_id = 1,
2032 .minimum_version_id = 1,
2033 .needed = spapr_ov5_cas_needed,
2034 .fields = (VMStateField[]) {
2035 VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1,
2036 vmstate_spapr_ovec, SpaprOptionVector),
2037 VMSTATE_END_OF_LIST()
2038 },
2039 };
2040
2041 static bool spapr_patb_entry_needed(void *opaque)
2042 {
2043 SpaprMachineState *spapr = opaque;
2044
2045 return !!spapr->patb_entry;
2046 }
2047
2048 static const VMStateDescription vmstate_spapr_patb_entry = {
2049 .name = "spapr_patb_entry",
2050 .version_id = 1,
2051 .minimum_version_id = 1,
2052 .needed = spapr_patb_entry_needed,
2053 .fields = (VMStateField[]) {
2054 VMSTATE_UINT64(patb_entry, SpaprMachineState),
2055 VMSTATE_END_OF_LIST()
2056 },
2057 };
2058
2059 static bool spapr_irq_map_needed(void *opaque)
2060 {
2061 SpaprMachineState *spapr = opaque;
2062
2063 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr);
2064 }
2065
2066 static const VMStateDescription vmstate_spapr_irq_map = {
2067 .name = "spapr_irq_map",
2068 .version_id = 1,
2069 .minimum_version_id = 1,
2070 .needed = spapr_irq_map_needed,
2071 .fields = (VMStateField[]) {
2072 VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr),
2073 VMSTATE_END_OF_LIST()
2074 },
2075 };
2076
2077 static bool spapr_dtb_needed(void *opaque)
2078 {
2079 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque);
2080
2081 return smc->update_dt_enabled;
2082 }
2083
2084 static int spapr_dtb_pre_load(void *opaque)
2085 {
2086 SpaprMachineState *spapr = (SpaprMachineState *)opaque;
2087
2088 g_free(spapr->fdt_blob);
2089 spapr->fdt_blob = NULL;
2090 spapr->fdt_size = 0;
2091
2092 return 0;
2093 }
2094
2095 static const VMStateDescription vmstate_spapr_dtb = {
2096 .name = "spapr_dtb",
2097 .version_id = 1,
2098 .minimum_version_id = 1,
2099 .needed = spapr_dtb_needed,
2100 .pre_load = spapr_dtb_pre_load,
2101 .fields = (VMStateField[]) {
2102 VMSTATE_UINT32(fdt_initial_size, SpaprMachineState),
2103 VMSTATE_UINT32(fdt_size, SpaprMachineState),
2104 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL,
2105 fdt_size),
2106 VMSTATE_END_OF_LIST()
2107 },
2108 };
2109
2110 static const VMStateDescription vmstate_spapr = {
2111 .name = "spapr",
2112 .version_id = 3,
2113 .minimum_version_id = 1,
2114 .pre_load = spapr_pre_load,
2115 .post_load = spapr_post_load,
2116 .pre_save = spapr_pre_save,
2117 .fields = (VMStateField[]) {
2118 /* used to be @next_irq */
2119 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4),
2120
2121 /* RTC offset */
2122 VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3),
2123
2124 VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2),
2125 VMSTATE_END_OF_LIST()
2126 },
2127 .subsections = (const VMStateDescription*[]) {
2128 &vmstate_spapr_ov5_cas,
2129 &vmstate_spapr_patb_entry,
2130 &vmstate_spapr_pending_events,
2131 &vmstate_spapr_cap_htm,
2132 &vmstate_spapr_cap_vsx,
2133 &vmstate_spapr_cap_dfp,
2134 &vmstate_spapr_cap_cfpc,
2135 &vmstate_spapr_cap_sbbc,
2136 &vmstate_spapr_cap_ibs,
2137 &vmstate_spapr_cap_hpt_maxpagesize,
2138 &vmstate_spapr_irq_map,
2139 &vmstate_spapr_cap_nested_kvm_hv,
2140 &vmstate_spapr_dtb,
2141 &vmstate_spapr_cap_large_decr,
2142 &vmstate_spapr_cap_ccf_assist,
2143 NULL
2144 }
2145 };
2146
2147 static int htab_save_setup(QEMUFile *f, void *opaque)
2148 {
2149 SpaprMachineState *spapr = opaque;
2150
2151 /* "Iteration" header */
2152 if (!spapr->htab_shift) {
2153 qemu_put_be32(f, -1);
2154 } else {
2155 qemu_put_be32(f, spapr->htab_shift);
2156 }
2157
2158 if (spapr->htab) {
2159 spapr->htab_save_index = 0;
2160 spapr->htab_first_pass = true;
2161 } else {
2162 if (spapr->htab_shift) {
2163 assert(kvm_enabled());
2164 }
2165 }
2166
2167
2168 return 0;
2169 }
2170
2171 static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr,
2172 int chunkstart, int n_valid, int n_invalid)
2173 {
2174 qemu_put_be32(f, chunkstart);
2175 qemu_put_be16(f, n_valid);
2176 qemu_put_be16(f, n_invalid);
2177 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
2178 HASH_PTE_SIZE_64 * n_valid);
2179 }
2180
2181 static void htab_save_end_marker(QEMUFile *f)
2182 {
2183 qemu_put_be32(f, 0);
2184 qemu_put_be16(f, 0);
2185 qemu_put_be16(f, 0);
2186 }
2187
2188 static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr,
2189 int64_t max_ns)
2190 {
2191 bool has_timeout = max_ns != -1;
2192 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
2193 int index = spapr->htab_save_index;
2194 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
2195
2196 assert(spapr->htab_first_pass);
2197
2198 do {
2199 int chunkstart;
2200
2201 /* Consume invalid HPTEs */
2202 while ((index < htabslots)
2203 && !HPTE_VALID(HPTE(spapr->htab, index))) {
2204 CLEAN_HPTE(HPTE(spapr->htab, index));
2205 index++;
2206 }
2207
2208 /* Consume valid HPTEs */
2209 chunkstart = index;
2210 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
2211 && HPTE_VALID(HPTE(spapr->htab, index))) {
2212 CLEAN_HPTE(HPTE(spapr->htab, index));
2213 index++;
2214 }
2215
2216 if (index > chunkstart) {
2217 int n_valid = index - chunkstart;
2218
2219 htab_save_chunk(f, spapr, chunkstart, n_valid, 0);
2220
2221 if (has_timeout &&
2222 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
2223 break;
2224 }
2225 }
2226 } while ((index < htabslots) && !qemu_file_rate_limit(f));
2227
2228 if (index >= htabslots) {
2229 assert(index == htabslots);
2230 index = 0;
2231 spapr->htab_first_pass = false;
2232 }
2233 spapr->htab_save_index = index;
2234 }
2235
2236 static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr,
2237 int64_t max_ns)
2238 {
2239 bool final = max_ns < 0;
2240 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
2241 int examined = 0, sent = 0;
2242 int index = spapr->htab_save_index;
2243 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
2244
2245 assert(!spapr->htab_first_pass);
2246
2247 do {
2248 int chunkstart, invalidstart;
2249
2250 /* Consume non-dirty HPTEs */
2251 while ((index < htabslots)
2252 && !HPTE_DIRTY(HPTE(spapr->htab, index))) {
2253 index++;
2254 examined++;
2255 }
2256
2257 chunkstart = index;
2258 /* Consume valid dirty HPTEs */
2259 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
2260 && HPTE_DIRTY(HPTE(spapr->htab, index))
2261 && HPTE_VALID(HPTE(spapr->htab, index))) {
2262 CLEAN_HPTE(HPTE(spapr->htab, index));
2263 index++;
2264 examined++;
2265 }
2266
2267 invalidstart = index;
2268 /* Consume invalid dirty HPTEs */
2269 while ((index < htabslots) && (index - invalidstart < USHRT_MAX)
2270 && HPTE_DIRTY(HPTE(spapr->htab, index))
2271 && !HPTE_VALID(HPTE(spapr->htab, index))) {
2272 CLEAN_HPTE(HPTE(spapr->htab, index));
2273 index++;
2274 examined++;
2275 }
2276
2277 if (index > chunkstart) {
2278 int n_valid = invalidstart - chunkstart;
2279 int n_invalid = index - invalidstart;
2280
2281 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid);
2282 sent += index - chunkstart;
2283
2284 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
2285 break;
2286 }
2287 }
2288
2289 if (examined >= htabslots) {
2290 break;
2291 }
2292
2293 if (index >= htabslots) {
2294 assert(index == htabslots);
2295 index = 0;
2296 }
2297 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final));
2298
2299 if (index >= htabslots) {
2300 assert(index == htabslots);
2301 index = 0;
2302 }
2303
2304 spapr->htab_save_index = index;
2305
2306 return (examined >= htabslots) && (sent == 0) ? 1 : 0;
2307 }
2308
2309 #define MAX_ITERATION_NS 5000000 /* 5 ms */
2310 #define MAX_KVM_BUF_SIZE 2048
2311
2312 static int htab_save_iterate(QEMUFile *f, void *opaque)
2313 {
2314 SpaprMachineState *spapr = opaque;
2315 int fd;
2316 int rc = 0;
2317
2318 /* Iteration header */
2319 if (!spapr->htab_shift) {
2320 qemu_put_be32(f, -1);
2321 return 1;
2322 } else {
2323 qemu_put_be32(f, 0);
2324 }
2325
2326 if (!spapr->htab) {
2327 assert(kvm_enabled());
2328
2329 fd = get_htab_fd(spapr);
2330 if (fd < 0) {
2331 return fd;
2332 }
2333
2334 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS);
2335 if (rc < 0) {
2336 return rc;
2337 }
2338 } else if (spapr->htab_first_pass) {
2339 htab_save_first_pass(f, spapr, MAX_ITERATION_NS);
2340 } else {
2341 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS);
2342 }
2343
2344 htab_save_end_marker(f);
2345
2346 return rc;
2347 }
2348
2349 static int htab_save_complete(QEMUFile *f, void *opaque)
2350 {
2351 SpaprMachineState *spapr = opaque;
2352 int fd;
2353
2354 /* Iteration header */
2355 if (!spapr->htab_shift) {
2356 qemu_put_be32(f, -1);
2357 return 0;
2358 } else {
2359 qemu_put_be32(f, 0);
2360 }
2361
2362 if (!spapr->htab) {
2363 int rc;
2364
2365 assert(kvm_enabled());
2366
2367 fd = get_htab_fd(spapr);
2368 if (fd < 0) {
2369 return fd;
2370 }
2371
2372 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1);
2373 if (rc < 0) {
2374 return rc;
2375 }
2376 } else {
2377 if (spapr->htab_first_pass) {
2378 htab_save_first_pass(f, spapr, -1);
2379 }
2380 htab_save_later_pass(f, spapr, -1);
2381 }
2382
2383 /* End marker */
2384 htab_save_end_marker(f);
2385
2386 return 0;
2387 }
2388
2389 static int htab_load(QEMUFile *f, void *opaque, int version_id)
2390 {
2391 SpaprMachineState *spapr = opaque;
2392 uint32_t section_hdr;
2393 int fd = -1;
2394 Error *local_err = NULL;
2395
2396 if (version_id < 1 || version_id > 1) {
2397 error_report("htab_load() bad version");
2398 return -EINVAL;
2399 }
2400
2401 section_hdr = qemu_get_be32(f);
2402
2403 if (section_hdr == -1) {
2404 spapr_free_hpt(spapr);
2405 return 0;
2406 }
2407
2408 if (section_hdr) {
2409 /* First section gives the htab size */
2410 spapr_reallocate_hpt(spapr, section_hdr, &local_err);
2411 if (local_err) {
2412 error_report_err(local_err);
2413 return -EINVAL;
2414 }
2415 return 0;
2416 }
2417
2418 if (!spapr->htab) {
2419 assert(kvm_enabled());
2420
2421 fd = kvmppc_get_htab_fd(true, 0, &local_err);
2422 if (fd < 0) {
2423 error_report_err(local_err);
2424 return fd;
2425 }
2426 }
2427
2428 while (true) {
2429 uint32_t index;
2430 uint16_t n_valid, n_invalid;
2431
2432 index = qemu_get_be32(f);
2433 n_valid = qemu_get_be16(f);
2434 n_invalid = qemu_get_be16(f);
2435
2436 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) {
2437 /* End of Stream */
2438 break;
2439 }
2440
2441 if ((index + n_valid + n_invalid) >
2442 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) {
2443 /* Bad index in stream */
2444 error_report(
2445 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
2446 index, n_valid, n_invalid, spapr->htab_shift);
2447 return -EINVAL;
2448 }
2449
2450 if (spapr->htab) {
2451 if (n_valid) {
2452 qemu_get_buffer(f, HPTE(spapr->htab, index),
2453 HASH_PTE_SIZE_64 * n_valid);
2454 }
2455 if (n_invalid) {
2456 memset(HPTE(spapr->htab, index + n_valid), 0,
2457 HASH_PTE_SIZE_64 * n_invalid);
2458 }
2459 } else {
2460 int rc;
2461
2462 assert(fd >= 0);
2463
2464 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid);
2465 if (rc < 0) {
2466 return rc;
2467 }
2468 }
2469 }
2470
2471 if (!spapr->htab) {
2472 assert(fd >= 0);
2473 close(fd);
2474 }
2475
2476 return 0;
2477 }
2478
2479 static void htab_save_cleanup(void *opaque)
2480 {
2481 SpaprMachineState *spapr = opaque;
2482
2483 close_htab_fd(spapr);
2484 }
2485
2486 static SaveVMHandlers savevm_htab_handlers = {
2487 .save_setup = htab_save_setup,
2488 .save_live_iterate = htab_save_iterate,
2489 .save_live_complete_precopy = htab_save_complete,
2490 .save_cleanup = htab_save_cleanup,
2491 .load_state = htab_load,
2492 };
2493
2494 static void spapr_boot_set(void *opaque, const char *boot_device,
2495 Error **errp)
2496 {
2497 MachineState *machine = MACHINE(opaque);
2498 machine->boot_order = g_strdup(boot_device);
2499 }
2500
2501 static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr)
2502 {
2503 MachineState *machine = MACHINE(spapr);
2504 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
2505 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size;
2506 int i;
2507
2508 for (i = 0; i < nr_lmbs; i++) {
2509 uint64_t addr;
2510
2511 addr = i * lmb_size + machine->device_memory->base;
2512 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB,
2513 addr / lmb_size);
2514 }
2515 }
2516
2517 /*
2518 * If RAM size, maxmem size and individual node mem sizes aren't aligned
2519 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
2520 * since we can't support such unaligned sizes with DRCONF_MEMORY.
2521 */
2522 static void spapr_validate_node_memory(MachineState *machine, Error **errp)
2523 {
2524 int i;
2525
2526 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) {
2527 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT
2528 " is not aligned to %" PRIu64 " MiB",
2529 machine->ram_size,
2530 SPAPR_MEMORY_BLOCK_SIZE / MiB);
2531 return;
2532 }
2533
2534 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) {
2535 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT
2536 " is not aligned to %" PRIu64 " MiB",
2537 machine->ram_size,
2538 SPAPR_MEMORY_BLOCK_SIZE / MiB);
2539 return;
2540 }
2541
2542 for (i = 0; i < nb_numa_nodes; i++) {
2543 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) {
2544 error_setg(errp,
2545 "Node %d memory size 0x%" PRIx64
2546 " is not aligned to %" PRIu64 " MiB",
2547 i, numa_info[i].node_mem,
2548 SPAPR_MEMORY_BLOCK_SIZE / MiB);
2549 return;
2550 }
2551 }
2552 }
2553
2554 /* find cpu slot in machine->possible_cpus by core_id */
2555 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
2556 {
2557 int index = id / ms->smp.threads;
2558
2559 if (index >= ms->possible_cpus->len) {
2560 return NULL;
2561 }
2562 if (idx) {
2563 *idx = index;
2564 }
2565 return &ms->possible_cpus->cpus[index];
2566 }
2567
2568 static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp)
2569 {
2570 MachineState *ms = MACHINE(spapr);
2571 Error *local_err = NULL;
2572 bool vsmt_user = !!spapr->vsmt;
2573 int kvm_smt = kvmppc_smt_threads();
2574 int ret;
2575 unsigned int smp_threads = ms->smp.threads;
2576
2577 if (!kvm_enabled() && (smp_threads > 1)) {
2578 error_setg(&local_err, "TCG cannot support more than 1 thread/core "
2579 "on a pseries machine");
2580 goto out;
2581 }
2582 if (!is_power_of_2(smp_threads)) {
2583 error_setg(&local_err, "Cannot support %d threads/core on a pseries "
2584 "machine because it must be a power of 2", smp_threads);
2585 goto out;
2586 }
2587
2588 /* Detemine the VSMT mode to use: */
2589 if (vsmt_user) {
2590 if (spapr->vsmt < smp_threads) {
2591 error_setg(&local_err, "Cannot support VSMT mode %d"
2592 " because it must be >= threads/core (%d)",
2593 spapr->vsmt, smp_threads);
2594 goto out;
2595 }
2596 /* In this case, spapr->vsmt has been set by the command line */
2597 } else {
2598 /*
2599 * Default VSMT value is tricky, because we need it to be as
2600 * consistent as possible (for migration), but this requires
2601 * changing it for at least some existing cases. We pick 8 as
2602 * the value that we'd get with KVM on POWER8, the
2603 * overwhelmingly common case in production systems.
2604 */
2605 spapr->vsmt = MAX(8, smp_threads);
2606 }
2607
2608 /* KVM: If necessary, set the SMT mode: */
2609 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) {
2610 ret = kvmppc_set_smt_threads(spapr->vsmt);
2611 if (ret) {
2612 /* Looks like KVM isn't able to change VSMT mode */
2613 error_setg(&local_err,
2614 "Failed to set KVM's VSMT mode to %d (errno %d)",
2615 spapr->vsmt, ret);
2616 /* We can live with that if the default one is big enough
2617 * for the number of threads, and a submultiple of the one
2618 * we want. In this case we'll waste some vcpu ids, but
2619 * behaviour will be correct */
2620 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) {
2621 warn_report_err(local_err);
2622 local_err = NULL;
2623 goto out;
2624 } else {
2625 if (!vsmt_user) {
2626 error_append_hint(&local_err,
2627 "On PPC, a VM with %d threads/core"
2628 " on a host with %d threads/core"
2629 " requires the use of VSMT mode %d.\n",
2630 smp_threads, kvm_smt, spapr->vsmt);
2631 }
2632 kvmppc_hint_smt_possible(&local_err);
2633 goto out;
2634 }
2635 }
2636 }
2637 /* else TCG: nothing to do currently */
2638 out:
2639 error_propagate(errp, local_err);
2640 }
2641
2642 static void spapr_init_cpus(SpaprMachineState *spapr)
2643 {
2644 MachineState *machine = MACHINE(spapr);
2645 MachineClass *mc = MACHINE_GET_CLASS(machine);
2646 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
2647 const char *type = spapr_get_cpu_core_type(machine->cpu_type);
2648 const CPUArchIdList *possible_cpus;
2649 unsigned int smp_cpus = machine->smp.cpus;
2650 unsigned int smp_threads = machine->smp.threads;
2651 unsigned int max_cpus = machine->smp.max_cpus;
2652 int boot_cores_nr = smp_cpus / smp_threads;
2653 int i;
2654
2655 possible_cpus = mc->possible_cpu_arch_ids(machine);
2656 if (mc->has_hotpluggable_cpus) {
2657 if (smp_cpus % smp_threads) {
2658 error_report("smp_cpus (%u) must be multiple of threads (%u)",
2659 smp_cpus, smp_threads);
2660 exit(1);
2661 }
2662 if (max_cpus % smp_threads) {
2663 error_report("max_cpus (%u) must be multiple of threads (%u)",
2664 max_cpus, smp_threads);
2665 exit(1);
2666 }
2667 } else {
2668 if (max_cpus != smp_cpus) {
2669 error_report("This machine version does not support CPU hotplug");
2670 exit(1);
2671 }
2672 boot_cores_nr = possible_cpus->len;
2673 }
2674
2675 if (smc->pre_2_10_has_unused_icps) {
2676 int i;
2677
2678 for (i = 0; i < spapr_max_server_number(spapr); i++) {
2679 /* Dummy entries get deregistered when real ICPState objects
2680 * are registered during CPU core hotplug.
2681 */
2682 pre_2_10_vmstate_register_dummy_icp(i);
2683 }
2684 }
2685
2686 for (i = 0; i < possible_cpus->len; i++) {
2687 int core_id = i * smp_threads;
2688
2689 if (mc->has_hotpluggable_cpus) {
2690 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU,
2691 spapr_vcpu_id(spapr, core_id));
2692 }
2693
2694 if (i < boot_cores_nr) {
2695 Object *core = object_new(type);
2696 int nr_threads = smp_threads;
2697
2698 /* Handle the partially filled core for older machine types */
2699 if ((i + 1) * smp_threads >= smp_cpus) {
2700 nr_threads = smp_cpus - i * smp_threads;
2701 }
2702
2703 object_property_set_int(core, nr_threads, "nr-threads",
2704 &error_fatal);
2705 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID,
2706 &error_fatal);
2707 object_property_set_bool(core, true, "realized", &error_fatal);
2708
2709 object_unref(core);
2710 }
2711 }
2712 }
2713
2714 static PCIHostState *spapr_create_default_phb(void)
2715 {
2716 DeviceState *dev;
2717
2718 dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE);
2719 qdev_prop_set_uint32(dev, "index", 0);
2720 qdev_init_nofail(dev);
2721
2722 return PCI_HOST_BRIDGE(dev);
2723 }
2724
2725 /* pSeries LPAR / sPAPR hardware init */
2726 static void spapr_machine_init(MachineState *machine)
2727 {
2728 SpaprMachineState *spapr = SPAPR_MACHINE(machine);
2729 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
2730 const char *kernel_filename = machine->kernel_filename;
2731 const char *initrd_filename = machine->initrd_filename;
2732 PCIHostState *phb;
2733 int i;
2734 MemoryRegion *sysmem = get_system_memory();
2735 MemoryRegion *ram = g_new(MemoryRegion, 1);
2736 hwaddr node0_size = spapr_node0_size(machine);
2737 long load_limit, fw_size;
2738 char *filename;
2739 Error *resize_hpt_err = NULL;
2740
2741 msi_nonbroken = true;
2742
2743 QLIST_INIT(&spapr->phbs);
2744 QTAILQ_INIT(&spapr->pending_dimm_unplugs);
2745
2746 /* Determine capabilities to run with */
2747 spapr_caps_init(spapr);
2748
2749 kvmppc_check_papr_resize_hpt(&resize_hpt_err);
2750 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) {
2751 /*
2752 * If the user explicitly requested a mode we should either
2753 * supply it, or fail completely (which we do below). But if
2754 * it's not set explicitly, we reset our mode to something
2755 * that works
2756 */
2757 if (resize_hpt_err) {
2758 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED;
2759 error_free(resize_hpt_err);
2760 resize_hpt_err = NULL;
2761 } else {
2762 spapr->resize_hpt = smc->resize_hpt_default;
2763 }
2764 }
2765
2766 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT);
2767
2768 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) {
2769 /*
2770 * User requested HPT resize, but this host can't supply it. Bail out
2771 */
2772 error_report_err(resize_hpt_err);
2773 exit(1);
2774 }
2775
2776 spapr->rma_size = node0_size;
2777
2778 /* With KVM, we don't actually know whether KVM supports an
2779 * unbounded RMA (PR KVM) or is limited by the hash table size
2780 * (HV KVM using VRMA), so we always assume the latter
2781 *
2782 * In that case, we also limit the initial allocations for RTAS
2783 * etc... to 256M since we have no way to know what the VRMA size
2784 * is going to be as it depends on the size of the hash table
2785 * which isn't determined yet.
2786 */
2787 if (kvm_enabled()) {
2788 spapr->vrma_adjust = 1;
2789 spapr->rma_size = MIN(spapr->rma_size, 0x10000000);
2790 }
2791
2792 /* Actually we don't support unbounded RMA anymore since we added
2793 * proper emulation of HV mode. The max we can get is 16G which
2794 * also happens to be what we configure for PAPR mode so make sure
2795 * we don't do anything bigger than that
2796 */
2797 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull);
2798
2799 if (spapr->rma_size > node0_size) {
2800 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")",
2801 spapr->rma_size);
2802 exit(1);
2803 }
2804
2805 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
2806 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD;
2807
2808 /*
2809 * VSMT must be set in order to be able to compute VCPU ids, ie to
2810 * call spapr_max_server_number() or spapr_vcpu_id().
2811 */
2812 spapr_set_vsmt_mode(spapr, &error_fatal);
2813
2814 /* Set up Interrupt Controller before we create the VCPUs */
2815 spapr_irq_init(spapr, &error_fatal);
2816
2817 /* Set up containers for ibm,client-architecture-support negotiated options
2818 */
2819 spapr->ov5 = spapr_ovec_new();
2820 spapr->ov5_cas = spapr_ovec_new();
2821
2822 if (smc->dr_lmb_enabled) {
2823 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY);
2824 spapr_validate_node_memory(machine, &error_fatal);
2825 }
2826
2827 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY);
2828
2829 /* advertise support for dedicated HP event source to guests */
2830 if (spapr->use_hotplug_event_source) {
2831 spapr_ovec_set(spapr->ov5, OV5_HP_EVT);
2832 }
2833
2834 /* advertise support for HPT resizing */
2835 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) {
2836 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE);
2837 }
2838
2839 /* advertise support for ibm,dyamic-memory-v2 */
2840 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2);
2841
2842 /* advertise XIVE on POWER9 machines */
2843 if (spapr->irq->ov5 & (SPAPR_OV5_XIVE_EXPLOIT | SPAPR_OV5_XIVE_BOTH)) {
2844 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT);
2845 }
2846
2847 /* init CPUs */
2848 spapr_init_cpus(spapr);
2849
2850 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) &&
2851 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0,
2852 spapr->max_compat_pvr)) {
2853 /* KVM and TCG always allow GTSE with radix... */
2854 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE);
2855 }
2856 /* ... but not with hash (currently). */
2857
2858 if (kvm_enabled()) {
2859 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
2860 kvmppc_enable_logical_ci_hcalls();
2861 kvmppc_enable_set_mode_hcall();
2862
2863 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */
2864 kvmppc_enable_clear_ref_mod_hcalls();
2865
2866 /* Enable H_PAGE_INIT */
2867 kvmppc_enable_h_page_init();
2868 }
2869
2870 /* allocate RAM */
2871 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram",
2872 machine->ram_size);
2873 memory_region_add_subregion(sysmem, 0, ram);
2874
2875 /* always allocate the device memory information */
2876 machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
2877
2878 /* initialize hotplug memory address space */
2879 if (machine->ram_size < machine->maxram_size) {
2880 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size;
2881 /*
2882 * Limit the number of hotpluggable memory slots to half the number
2883 * slots that KVM supports, leaving the other half for PCI and other
2884 * devices. However ensure that number of slots doesn't drop below 32.
2885 */
2886 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 :
2887 SPAPR_MAX_RAM_SLOTS;
2888
2889 if (max_memslots < SPAPR_MAX_RAM_SLOTS) {
2890 max_memslots = SPAPR_MAX_RAM_SLOTS;
2891 }
2892 if (machine->ram_slots > max_memslots) {
2893 error_report("Specified number of memory slots %"
2894 PRIu64" exceeds max supported %d",
2895 machine->ram_slots, max_memslots);
2896 exit(1);
2897 }
2898
2899 machine->device_memory->base = ROUND_UP(machine->ram_size,
2900 SPAPR_DEVICE_MEM_ALIGN);
2901 memory_region_init(&machine->device_memory->mr, OBJECT(spapr),
2902 "device-memory", device_mem_size);
2903 memory_region_add_subregion(sysmem, machine->device_memory->base,
2904 &machine->device_memory->mr);
2905 }
2906
2907 if (smc->dr_lmb_enabled) {
2908 spapr_create_lmb_dr_connectors(spapr);
2909 }
2910
2911 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
2912 if (!filename) {
2913 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin");
2914 exit(1);
2915 }
2916 spapr->rtas_size = get_image_size(filename);
2917 if (spapr->rtas_size < 0) {
2918 error_report("Could not get size of LPAR rtas '%s'", filename);
2919 exit(1);
2920 }
2921 spapr->rtas_blob = g_malloc(spapr->rtas_size);
2922 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) {
2923 error_report("Could not load LPAR rtas '%s'", filename);
2924 exit(1);
2925 }
2926 if (spapr->rtas_size > RTAS_MAX_SIZE) {
2927 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)",
2928 (size_t)spapr->rtas_size, RTAS_MAX_SIZE);
2929 exit(1);
2930 }
2931 g_free(filename);
2932
2933 /* Set up RTAS event infrastructure */
2934 spapr_events_init(spapr);
2935
2936 /* Set up the RTC RTAS interfaces */
2937 spapr_rtc_create(spapr);
2938
2939 /* Set up VIO bus */
2940 spapr->vio_bus = spapr_vio_bus_init();
2941
2942 for (i = 0; i < serial_max_hds(); i++) {
2943 if (serial_hd(i)) {
2944 spapr_vty_create(spapr->vio_bus, serial_hd(i));
2945 }
2946 }
2947
2948 /* We always have at least the nvram device on VIO */
2949 spapr_create_nvram(spapr);
2950
2951 /*
2952 * Setup hotplug / dynamic-reconfiguration connectors. top-level
2953 * connectors (described in root DT node's "ibm,drc-types" property)
2954 * are pre-initialized here. additional child connectors (such as
2955 * connectors for a PHBs PCI slots) are added as needed during their
2956 * parent's realization.
2957 */
2958 if (smc->dr_phb_enabled) {
2959 for (i = 0; i < SPAPR_MAX_PHBS; i++) {
2960 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i);
2961 }
2962 }
2963
2964 /* Set up PCI */
2965 spapr_pci_rtas_init();
2966
2967 phb = spapr_create_default_phb();
2968
2969 for (i = 0; i < nb_nics; i++) {
2970 NICInfo *nd = &nd_table[i];
2971
2972 if (!nd->model) {
2973 nd->model = g_strdup("spapr-vlan");
2974 }
2975
2976 if (g_str_equal(nd->model, "spapr-vlan") ||
2977 g_str_equal(nd->model, "ibmveth")) {
2978 spapr_vlan_create(spapr->vio_bus, nd);
2979 } else {
2980 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL);
2981 }
2982 }
2983
2984 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
2985 spapr_vscsi_create(spapr->vio_bus);
2986 }
2987
2988 /* Graphics */
2989 if (spapr_vga_init(phb->bus, &error_fatal)) {
2990 spapr->has_graphics = true;
2991 machine->usb |= defaults_enabled() && !machine->usb_disabled;
2992 }
2993
2994 if (machine->usb) {
2995 if (smc->use_ohci_by_default) {
2996 pci_create_simple(phb->bus, -1, "pci-ohci");
2997 } else {
2998 pci_create_simple(phb->bus, -1, "nec-usb-xhci");
2999 }
3000
3001 if (spapr->has_graphics) {
3002 USBBus *usb_bus = usb_bus_find(-1);
3003
3004 usb_create_simple(usb_bus, "usb-kbd");
3005 usb_create_simple(usb_bus, "usb-mouse");
3006 }
3007 }
3008
3009 if (spapr->rma_size < (MIN_RMA_SLOF * MiB)) {
3010 error_report(
3011 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
3012 MIN_RMA_SLOF);
3013 exit(1);
3014 }
3015
3016 if (kernel_filename) {
3017 uint64_t lowaddr = 0;
3018
3019 spapr->kernel_size = load_elf(kernel_filename, NULL,
3020 translate_kernel_address, NULL,
3021 NULL, &lowaddr, NULL, 1,
3022 PPC_ELF_MACHINE, 0, 0);
3023 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) {
3024 spapr->kernel_size = load_elf(kernel_filename, NULL,
3025 translate_kernel_address, NULL, NULL,
3026 &lowaddr, NULL, 0, PPC_ELF_MACHINE,
3027 0, 0);
3028 spapr->kernel_le = spapr->kernel_size > 0;
3029 }
3030 if (spapr->kernel_size < 0) {
3031 error_report("error loading %s: %s", kernel_filename,
3032 load_elf_strerror(spapr->kernel_size));
3033 exit(1);
3034 }
3035
3036 /* load initrd */
3037 if (initrd_filename) {
3038 /* Try to locate the initrd in the gap between the kernel
3039 * and the firmware. Add a bit of space just in case
3040 */
3041 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size
3042 + 0x1ffff) & ~0xffff;
3043 spapr->initrd_size = load_image_targphys(initrd_filename,
3044 spapr->initrd_base,
3045 load_limit
3046 - spapr->initrd_base);
3047 if (spapr->initrd_size < 0) {
3048 error_report("could not load initial ram disk '%s'",
3049 initrd_filename);
3050 exit(1);
3051 }
3052 }
3053 }
3054
3055 if (bios_name == NULL) {
3056 bios_name = FW_FILE_NAME;
3057 }
3058 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
3059 if (!filename) {
3060 error_report("Could not find LPAR firmware '%s'", bios_name);
3061 exit(1);
3062 }
3063 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
3064 if (fw_size <= 0) {
3065 error_report("Could not load LPAR firmware '%s'", filename);
3066 exit(1);
3067 }
3068 g_free(filename);
3069
3070 /* FIXME: Should register things through the MachineState's qdev
3071 * interface, this is a legacy from the sPAPREnvironment structure
3072 * which predated MachineState but had a similar function */
3073 vmstate_register(NULL, 0, &vmstate_spapr, spapr);
3074 register_savevm_live(NULL, "spapr/htab", -1, 1,
3075 &savevm_htab_handlers, spapr);
3076
3077 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine),
3078 &error_fatal);
3079
3080 qemu_register_boot_set(spapr_boot_set, spapr);
3081
3082 /*
3083 * Nothing needs to be done to resume a suspended guest because
3084 * suspending does not change the machine state, so no need for
3085 * a ->wakeup method.
3086 */
3087 qemu_register_wakeup_support();
3088
3089 if (kvm_enabled()) {
3090 /* to stop and start vmclock */
3091 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change,
3092 &spapr->tb);
3093
3094 kvmppc_spapr_enable_inkernel_multitce();
3095 }
3096 }
3097
3098 static int spapr_kvm_type(MachineState *machine, const char *vm_type)
3099 {
3100 if (!vm_type) {
3101 return 0;
3102 }
3103
3104 if (!strcmp(vm_type, "HV")) {
3105 return 1;
3106 }
3107
3108 if (!strcmp(vm_type, "PR")) {
3109 return 2;
3110 }
3111
3112 error_report("Unknown kvm-type specified '%s'", vm_type);
3113 exit(1);
3114 }
3115
3116 /*
3117 * Implementation of an interface to adjust firmware path
3118 * for the bootindex property handling.
3119 */
3120 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus,
3121 DeviceState *dev)
3122 {
3123 #define CAST(type, obj, name) \
3124 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
3125 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE);
3126 SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE);
3127 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON);
3128
3129 if (d) {
3130 void *spapr = CAST(void, bus->parent, "spapr-vscsi");
3131 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI);
3132 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE);
3133
3134 if (spapr) {
3135 /*
3136 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
3137 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form
3138 * 0x8000 | (target << 8) | (bus << 5) | lun
3139 * (see the "Logical unit addressing format" table in SAM5)
3140 */
3141 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun;
3142 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
3143 (uint64_t)id << 48);
3144 } else if (virtio) {
3145 /*
3146 * We use SRP luns of the form 01000000 | (target << 8) | lun
3147 * in the top 32 bits of the 64-bit LUN
3148 * Note: the quote above is from SLOF and it is wrong,
3149 * the actual binding is:
3150 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
3151 */
3152 unsigned id = 0x1000000 | (d->id << 16) | d->lun;
3153 if (d->lun >= 256) {
3154 /* Use the LUN "flat space addressing method" */
3155 id |= 0x4000;
3156 }
3157 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
3158 (uint64_t)id << 32);
3159 } else if (usb) {
3160 /*
3161 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
3162 * in the top 32 bits of the 64-bit LUN
3163 */
3164 unsigned usb_port = atoi(usb->port->path);
3165 unsigned id = 0x1000000 | (usb_port << 16) | d->lun;
3166 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
3167 (uint64_t)id << 32);
3168 }
3169 }
3170
3171 /*
3172 * SLOF probes the USB devices, and if it recognizes that the device is a
3173 * storage device, it changes its name to "storage" instead of "usb-host",
3174 * and additionally adds a child node for the SCSI LUN, so the correct
3175 * boot path in SLOF is something like .../storage@1/disk@xxx" instead.
3176 */
3177 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) {
3178 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE);
3179 if (usb_host_dev_is_scsi_storage(usbdev)) {
3180 return g_strdup_printf("storage@%s/disk", usbdev->port->path);
3181 }
3182 }
3183
3184 if (phb) {
3185 /* Replace "pci" with "pci@800000020000000" */
3186 return g_strdup_printf("pci@%"PRIX64, phb->buid);
3187 }
3188
3189 if (vsc) {
3190 /* Same logic as virtio above */
3191 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun;
3192 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32);
3193 }
3194
3195 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) {
3196 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */
3197 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE);
3198 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn));
3199 }
3200
3201 return NULL;
3202 }
3203
3204 static char *spapr_get_kvm_type(Object *obj, Error **errp)
3205 {
3206 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3207
3208 return g_strdup(spapr->kvm_type);
3209 }
3210
3211 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp)
3212 {
3213 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3214
3215 g_free(spapr->kvm_type);
3216 spapr->kvm_type = g_strdup(value);
3217 }
3218
3219 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp)
3220 {
3221 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3222
3223 return spapr->use_hotplug_event_source;
3224 }
3225
3226 static void spapr_set_modern_hotplug_events(Object *obj, bool value,
3227 Error **errp)
3228 {
3229 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3230
3231 spapr->use_hotplug_event_source = value;
3232 }
3233
3234 static bool spapr_get_msix_emulation(Object *obj, Error **errp)
3235 {
3236 return true;
3237 }
3238
3239 static char *spapr_get_resize_hpt(Object *obj, Error **errp)
3240 {
3241 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3242
3243 switch (spapr->resize_hpt) {
3244 case SPAPR_RESIZE_HPT_DEFAULT:
3245 return g_strdup("default");
3246 case SPAPR_RESIZE_HPT_DISABLED:
3247 return g_strdup("disabled");
3248 case SPAPR_RESIZE_HPT_ENABLED:
3249 return g_strdup("enabled");
3250 case SPAPR_RESIZE_HPT_REQUIRED:
3251 return g_strdup("required");
3252 }
3253 g_assert_not_reached();
3254 }
3255
3256 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp)
3257 {
3258 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3259
3260 if (strcmp(value, "default") == 0) {
3261 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT;
3262 } else if (strcmp(value, "disabled") == 0) {
3263 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED;
3264 } else if (strcmp(value, "enabled") == 0) {
3265 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED;
3266 } else if (strcmp(value, "required") == 0) {
3267 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED;
3268 } else {
3269 error_setg(errp, "Bad value for \"resize-hpt\" property");
3270 }
3271 }
3272
3273 static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name,
3274 void *opaque, Error **errp)
3275 {
3276 visit_type_uint32(v, name, (uint32_t *)opaque, errp);
3277 }
3278
3279 static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name,
3280 void *opaque, Error **errp)
3281 {
3282 visit_type_uint32(v, name, (uint32_t *)opaque, errp);
3283 }
3284
3285 static char *spapr_get_ic_mode(Object *obj, Error **errp)
3286 {
3287 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3288
3289 if (spapr->irq == &spapr_irq_xics_legacy) {
3290 return g_strdup("legacy");
3291 } else if (spapr->irq == &spapr_irq_xics) {
3292 return g_strdup("xics");
3293 } else if (spapr->irq == &spapr_irq_xive) {
3294 return g_strdup("xive");
3295 } else if (spapr->irq == &spapr_irq_dual) {
3296 return g_strdup("dual");
3297 }
3298 g_assert_not_reached();
3299 }
3300
3301 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp)
3302 {
3303 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3304
3305 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) {
3306 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode");
3307 return;
3308 }
3309
3310 /* The legacy IRQ backend can not be set */
3311 if (strcmp(value