spapr: Enable ISA 3.0 MMU mode selection via CAS
[qemu.git] / hw / ppc / spapr.c
1 /*
2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
3 *
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 *
26 */
27 #include "qemu/osdep.h"
28 #include "qapi/error.h"
29 #include "sysemu/sysemu.h"
30 #include "sysemu/numa.h"
31 #include "hw/hw.h"
32 #include "qemu/log.h"
33 #include "hw/fw-path-provider.h"
34 #include "elf.h"
35 #include "net/net.h"
36 #include "sysemu/device_tree.h"
37 #include "sysemu/block-backend.h"
38 #include "sysemu/cpus.h"
39 #include "sysemu/hw_accel.h"
40 #include "kvm_ppc.h"
41 #include "migration/migration.h"
42 #include "mmu-hash64.h"
43 #include "mmu-book3s-v3.h"
44 #include "qom/cpu.h"
45
46 #include "hw/boards.h"
47 #include "hw/ppc/ppc.h"
48 #include "hw/loader.h"
49
50 #include "hw/ppc/fdt.h"
51 #include "hw/ppc/spapr.h"
52 #include "hw/ppc/spapr_vio.h"
53 #include "hw/pci-host/spapr.h"
54 #include "hw/ppc/xics.h"
55 #include "hw/pci/msi.h"
56
57 #include "hw/pci/pci.h"
58 #include "hw/scsi/scsi.h"
59 #include "hw/virtio/virtio-scsi.h"
60
61 #include "exec/address-spaces.h"
62 #include "hw/usb.h"
63 #include "qemu/config-file.h"
64 #include "qemu/error-report.h"
65 #include "trace.h"
66 #include "hw/nmi.h"
67 #include "hw/intc/intc.h"
68
69 #include "hw/compat.h"
70 #include "qemu/cutils.h"
71 #include "hw/ppc/spapr_cpu_core.h"
72 #include "qmp-commands.h"
73
74 #include <libfdt.h>
75
76 /* SLOF memory layout:
77 *
78 * SLOF raw image loaded at 0, copies its romfs right below the flat
79 * device-tree, then position SLOF itself 31M below that
80 *
81 * So we set FW_OVERHEAD to 40MB which should account for all of that
82 * and more
83 *
84 * We load our kernel at 4M, leaving space for SLOF initial image
85 */
86 #define FDT_MAX_SIZE 0x100000
87 #define RTAS_MAX_SIZE 0x10000
88 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */
89 #define FW_MAX_SIZE 0x400000
90 #define FW_FILE_NAME "slof.bin"
91 #define FW_OVERHEAD 0x2800000
92 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
93
94 #define MIN_RMA_SLOF 128UL
95
96 #define PHANDLE_XICP 0x00001111
97
98 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift))
99
100 static int try_create_xics(sPAPRMachineState *spapr, const char *type_ics,
101 const char *type_icp, int nr_servers,
102 int nr_irqs, Error **errp)
103 {
104 XICSFabric *xi = XICS_FABRIC(spapr);
105 Error *err = NULL, *local_err = NULL;
106 ICSState *ics = NULL;
107 int i;
108
109 ics = ICS_SIMPLE(object_new(type_ics));
110 object_property_add_child(OBJECT(spapr), "ics", OBJECT(ics), NULL);
111 object_property_set_int(OBJECT(ics), nr_irqs, "nr-irqs", &err);
112 object_property_add_const_link(OBJECT(ics), "xics", OBJECT(xi), NULL);
113 object_property_set_bool(OBJECT(ics), true, "realized", &local_err);
114 error_propagate(&err, local_err);
115 if (err) {
116 goto error;
117 }
118
119 spapr->icps = g_malloc0(nr_servers * sizeof(ICPState));
120 spapr->nr_servers = nr_servers;
121
122 for (i = 0; i < nr_servers; i++) {
123 ICPState *icp = &spapr->icps[i];
124
125 object_initialize(icp, sizeof(*icp), type_icp);
126 object_property_add_child(OBJECT(spapr), "icp[*]", OBJECT(icp), NULL);
127 object_property_add_const_link(OBJECT(icp), "xics", OBJECT(xi), NULL);
128 object_property_set_bool(OBJECT(icp), true, "realized", &err);
129 if (err) {
130 goto error;
131 }
132 object_unref(OBJECT(icp));
133 }
134
135 spapr->ics = ics;
136 return 0;
137
138 error:
139 error_propagate(errp, err);
140 if (ics) {
141 object_unparent(OBJECT(ics));
142 }
143 return -1;
144 }
145
146 static int xics_system_init(MachineState *machine,
147 int nr_servers, int nr_irqs, Error **errp)
148 {
149 int rc = -1;
150
151 if (kvm_enabled()) {
152 Error *err = NULL;
153
154 if (machine_kernel_irqchip_allowed(machine) &&
155 !xics_kvm_init(SPAPR_MACHINE(machine), errp)) {
156 rc = try_create_xics(SPAPR_MACHINE(machine), TYPE_ICS_KVM,
157 TYPE_KVM_ICP, nr_servers, nr_irqs, &err);
158 }
159 if (machine_kernel_irqchip_required(machine) && rc < 0) {
160 error_reportf_err(err,
161 "kernel_irqchip requested but unavailable: ");
162 } else {
163 error_free(err);
164 }
165 }
166
167 if (rc < 0) {
168 xics_spapr_init(SPAPR_MACHINE(machine), errp);
169 rc = try_create_xics(SPAPR_MACHINE(machine), TYPE_ICS_SIMPLE,
170 TYPE_ICP, nr_servers, nr_irqs, errp);
171 }
172
173 return rc;
174 }
175
176 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
177 int smt_threads)
178 {
179 int i, ret = 0;
180 uint32_t servers_prop[smt_threads];
181 uint32_t gservers_prop[smt_threads * 2];
182 int index = ppc_get_vcpu_dt_id(cpu);
183
184 if (cpu->compat_pvr) {
185 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr);
186 if (ret < 0) {
187 return ret;
188 }
189 }
190
191 /* Build interrupt servers and gservers properties */
192 for (i = 0; i < smt_threads; i++) {
193 servers_prop[i] = cpu_to_be32(index + i);
194 /* Hack, direct the group queues back to cpu 0 */
195 gservers_prop[i*2] = cpu_to_be32(index + i);
196 gservers_prop[i*2 + 1] = 0;
197 }
198 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
199 servers_prop, sizeof(servers_prop));
200 if (ret < 0) {
201 return ret;
202 }
203 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s",
204 gservers_prop, sizeof(gservers_prop));
205
206 return ret;
207 }
208
209 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, CPUState *cs)
210 {
211 int ret = 0;
212 PowerPCCPU *cpu = POWERPC_CPU(cs);
213 int index = ppc_get_vcpu_dt_id(cpu);
214 uint32_t associativity[] = {cpu_to_be32(0x5),
215 cpu_to_be32(0x0),
216 cpu_to_be32(0x0),
217 cpu_to_be32(0x0),
218 cpu_to_be32(cs->numa_node),
219 cpu_to_be32(index)};
220
221 /* Advertise NUMA via ibm,associativity */
222 if (nb_numa_nodes > 1) {
223 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity,
224 sizeof(associativity));
225 }
226
227 return ret;
228 }
229
230 /* Populate the "ibm,pa-features" property */
231 static void spapr_populate_pa_features(CPUPPCState *env, void *fdt, int offset)
232 {
233 uint8_t pa_features_206[] = { 6, 0,
234 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
235 uint8_t pa_features_207[] = { 24, 0,
236 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
237 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
238 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
239 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
240 uint8_t pa_features_300[] = { 66, 0,
241 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
242 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */
243 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */
244 /* 6: DS207 */
245 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
246 /* 16: Vector */
247 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
248 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */
249 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 18 - 23 */
250 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
251 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
252 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */
253 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
254 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */
255 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */
256 /* 42: PM, 44: PC RA, 46: SC vec'd */
257 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
258 /* 48: SIMD, 50: QP BFP, 52: String */
259 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
260 /* 54: DecFP, 56: DecI, 58: SHA */
261 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
262 /* 60: NM atomic, 62: RNG */
263 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
264 };
265 uint8_t *pa_features;
266 size_t pa_size;
267
268 switch (POWERPC_MMU_VER(env->mmu_model)) {
269 case POWERPC_MMU_VER_2_06:
270 pa_features = pa_features_206;
271 pa_size = sizeof(pa_features_206);
272 break;
273 case POWERPC_MMU_VER_2_07:
274 pa_features = pa_features_207;
275 pa_size = sizeof(pa_features_207);
276 break;
277 case POWERPC_MMU_VER_3_00:
278 pa_features = pa_features_300;
279 pa_size = sizeof(pa_features_300);
280 break;
281 default:
282 return;
283 }
284
285 if (env->ci_large_pages) {
286 /*
287 * Note: we keep CI large pages off by default because a 64K capable
288 * guest provisioned with large pages might otherwise try to map a qemu
289 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
290 * even if that qemu runs on a 4k host.
291 * We dd this bit back here if we are confident this is not an issue
292 */
293 pa_features[3] |= 0x20;
294 }
295 if (kvmppc_has_cap_htm() && pa_size > 24) {
296 pa_features[24] |= 0x80; /* Transactional memory support */
297 }
298
299 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size)));
300 }
301
302 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr)
303 {
304 int ret = 0, offset, cpus_offset;
305 CPUState *cs;
306 char cpu_model[32];
307 int smt = kvmppc_smt_threads();
308 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
309
310 CPU_FOREACH(cs) {
311 PowerPCCPU *cpu = POWERPC_CPU(cs);
312 DeviceClass *dc = DEVICE_GET_CLASS(cs);
313 int index = ppc_get_vcpu_dt_id(cpu);
314 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu));
315
316 if ((index % smt) != 0) {
317 continue;
318 }
319
320 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index);
321
322 cpus_offset = fdt_path_offset(fdt, "/cpus");
323 if (cpus_offset < 0) {
324 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"),
325 "cpus");
326 if (cpus_offset < 0) {
327 return cpus_offset;
328 }
329 }
330 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model);
331 if (offset < 0) {
332 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model);
333 if (offset < 0) {
334 return offset;
335 }
336 }
337
338 ret = fdt_setprop(fdt, offset, "ibm,pft-size",
339 pft_size_prop, sizeof(pft_size_prop));
340 if (ret < 0) {
341 return ret;
342 }
343
344 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cs);
345 if (ret < 0) {
346 return ret;
347 }
348
349 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt);
350 if (ret < 0) {
351 return ret;
352 }
353 }
354 return ret;
355 }
356
357 static hwaddr spapr_node0_size(void)
358 {
359 MachineState *machine = MACHINE(qdev_get_machine());
360
361 if (nb_numa_nodes) {
362 int i;
363 for (i = 0; i < nb_numa_nodes; ++i) {
364 if (numa_info[i].node_mem) {
365 return MIN(pow2floor(numa_info[i].node_mem),
366 machine->ram_size);
367 }
368 }
369 }
370 return machine->ram_size;
371 }
372
373 static void add_str(GString *s, const gchar *s1)
374 {
375 g_string_append_len(s, s1, strlen(s1) + 1);
376 }
377
378 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start,
379 hwaddr size)
380 {
381 uint32_t associativity[] = {
382 cpu_to_be32(0x4), /* length */
383 cpu_to_be32(0x0), cpu_to_be32(0x0),
384 cpu_to_be32(0x0), cpu_to_be32(nodeid)
385 };
386 char mem_name[32];
387 uint64_t mem_reg_property[2];
388 int off;
389
390 mem_reg_property[0] = cpu_to_be64(start);
391 mem_reg_property[1] = cpu_to_be64(size);
392
393 sprintf(mem_name, "memory@" TARGET_FMT_lx, start);
394 off = fdt_add_subnode(fdt, 0, mem_name);
395 _FDT(off);
396 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
397 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
398 sizeof(mem_reg_property))));
399 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
400 sizeof(associativity))));
401 return off;
402 }
403
404 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt)
405 {
406 MachineState *machine = MACHINE(spapr);
407 hwaddr mem_start, node_size;
408 int i, nb_nodes = nb_numa_nodes;
409 NodeInfo *nodes = numa_info;
410 NodeInfo ramnode;
411
412 /* No NUMA nodes, assume there is just one node with whole RAM */
413 if (!nb_numa_nodes) {
414 nb_nodes = 1;
415 ramnode.node_mem = machine->ram_size;
416 nodes = &ramnode;
417 }
418
419 for (i = 0, mem_start = 0; i < nb_nodes; ++i) {
420 if (!nodes[i].node_mem) {
421 continue;
422 }
423 if (mem_start >= machine->ram_size) {
424 node_size = 0;
425 } else {
426 node_size = nodes[i].node_mem;
427 if (node_size > machine->ram_size - mem_start) {
428 node_size = machine->ram_size - mem_start;
429 }
430 }
431 if (!mem_start) {
432 /* ppc_spapr_init() checks for rma_size <= node0_size already */
433 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size);
434 mem_start += spapr->rma_size;
435 node_size -= spapr->rma_size;
436 }
437 for ( ; node_size; ) {
438 hwaddr sizetmp = pow2floor(node_size);
439
440 /* mem_start != 0 here */
441 if (ctzl(mem_start) < ctzl(sizetmp)) {
442 sizetmp = 1ULL << ctzl(mem_start);
443 }
444
445 spapr_populate_memory_node(fdt, i, mem_start, sizetmp);
446 node_size -= sizetmp;
447 mem_start += sizetmp;
448 }
449 }
450
451 return 0;
452 }
453
454 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
455 sPAPRMachineState *spapr)
456 {
457 PowerPCCPU *cpu = POWERPC_CPU(cs);
458 CPUPPCState *env = &cpu->env;
459 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
460 int index = ppc_get_vcpu_dt_id(cpu);
461 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
462 0xffffffff, 0xffffffff};
463 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq()
464 : SPAPR_TIMEBASE_FREQ;
465 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
466 uint32_t page_sizes_prop[64];
467 size_t page_sizes_prop_size;
468 uint32_t vcpus_per_socket = smp_threads * smp_cores;
469 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
470 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu));
471 sPAPRDRConnector *drc;
472 sPAPRDRConnectorClass *drck;
473 int drc_index;
474 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ];
475 int i;
476
477 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index);
478 if (drc) {
479 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
480 drc_index = drck->get_index(drc);
481 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)));
482 }
483
484 _FDT((fdt_setprop_cell(fdt, offset, "reg", index)));
485 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
486
487 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
488 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
489 env->dcache_line_size)));
490 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
491 env->dcache_line_size)));
492 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
493 env->icache_line_size)));
494 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
495 env->icache_line_size)));
496
497 if (pcc->l1_dcache_size) {
498 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
499 pcc->l1_dcache_size)));
500 } else {
501 error_report("Warning: Unknown L1 dcache size for cpu");
502 }
503 if (pcc->l1_icache_size) {
504 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
505 pcc->l1_icache_size)));
506 } else {
507 error_report("Warning: Unknown L1 icache size for cpu");
508 }
509
510 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
511 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
512 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr)));
513 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr)));
514 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
515 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
516
517 if (env->spr_cb[SPR_PURR].oea_read) {
518 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
519 }
520
521 if (env->mmu_model & POWERPC_MMU_1TSEG) {
522 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
523 segs, sizeof(segs))));
524 }
525
526 /* Advertise VMX/VSX (vector extensions) if available
527 * 0 / no property == no vector extensions
528 * 1 == VMX / Altivec available
529 * 2 == VSX available */
530 if (env->insns_flags & PPC_ALTIVEC) {
531 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
532
533 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
534 }
535
536 /* Advertise DFP (Decimal Floating Point) if available
537 * 0 / no property == no DFP
538 * 1 == DFP available */
539 if (env->insns_flags2 & PPC2_DFP) {
540 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
541 }
542
543 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop,
544 sizeof(page_sizes_prop));
545 if (page_sizes_prop_size) {
546 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
547 page_sizes_prop, page_sizes_prop_size)));
548 }
549
550 spapr_populate_pa_features(env, fdt, offset);
551
552 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
553 cs->cpu_index / vcpus_per_socket)));
554
555 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size",
556 pft_size_prop, sizeof(pft_size_prop))));
557
558 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cs));
559
560 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt));
561
562 if (pcc->radix_page_info) {
563 for (i = 0; i < pcc->radix_page_info->count; i++) {
564 radix_AP_encodings[i] =
565 cpu_to_be32(pcc->radix_page_info->entries[i]);
566 }
567 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings",
568 radix_AP_encodings,
569 pcc->radix_page_info->count *
570 sizeof(radix_AP_encodings[0]))));
571 }
572 }
573
574 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr)
575 {
576 CPUState *cs;
577 int cpus_offset;
578 char *nodename;
579 int smt = kvmppc_smt_threads();
580
581 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
582 _FDT(cpus_offset);
583 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
584 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
585
586 /*
587 * We walk the CPUs in reverse order to ensure that CPU DT nodes
588 * created by fdt_add_subnode() end up in the right order in FDT
589 * for the guest kernel the enumerate the CPUs correctly.
590 */
591 CPU_FOREACH_REVERSE(cs) {
592 PowerPCCPU *cpu = POWERPC_CPU(cs);
593 int index = ppc_get_vcpu_dt_id(cpu);
594 DeviceClass *dc = DEVICE_GET_CLASS(cs);
595 int offset;
596
597 if ((index % smt) != 0) {
598 continue;
599 }
600
601 nodename = g_strdup_printf("%s@%x", dc->fw_name, index);
602 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
603 g_free(nodename);
604 _FDT(offset);
605 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
606 }
607
608 }
609
610 /*
611 * Adds ibm,dynamic-reconfiguration-memory node.
612 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
613 * of this device tree node.
614 */
615 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt)
616 {
617 MachineState *machine = MACHINE(spapr);
618 int ret, i, offset;
619 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
620 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)};
621 uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size;
622 uint32_t nr_lmbs = (spapr->hotplug_memory.base +
623 memory_region_size(&spapr->hotplug_memory.mr)) /
624 lmb_size;
625 uint32_t *int_buf, *cur_index, buf_len;
626 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1;
627
628 /*
629 * Don't create the node if there is no hotpluggable memory
630 */
631 if (machine->ram_size == machine->maxram_size) {
632 return 0;
633 }
634
635 /*
636 * Allocate enough buffer size to fit in ibm,dynamic-memory
637 * or ibm,associativity-lookup-arrays
638 */
639 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2)
640 * sizeof(uint32_t);
641 cur_index = int_buf = g_malloc0(buf_len);
642
643 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory");
644
645 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size,
646 sizeof(prop_lmb_size));
647 if (ret < 0) {
648 goto out;
649 }
650
651 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff);
652 if (ret < 0) {
653 goto out;
654 }
655
656 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0);
657 if (ret < 0) {
658 goto out;
659 }
660
661 /* ibm,dynamic-memory */
662 int_buf[0] = cpu_to_be32(nr_lmbs);
663 cur_index++;
664 for (i = 0; i < nr_lmbs; i++) {
665 uint64_t addr = i * lmb_size;
666 uint32_t *dynamic_memory = cur_index;
667
668 if (i >= hotplug_lmb_start) {
669 sPAPRDRConnector *drc;
670 sPAPRDRConnectorClass *drck;
671
672 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, i);
673 g_assert(drc);
674 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
675
676 dynamic_memory[0] = cpu_to_be32(addr >> 32);
677 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
678 dynamic_memory[2] = cpu_to_be32(drck->get_index(drc));
679 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
680 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL));
681 if (memory_region_present(get_system_memory(), addr)) {
682 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED);
683 } else {
684 dynamic_memory[5] = cpu_to_be32(0);
685 }
686 } else {
687 /*
688 * LMB information for RMA, boot time RAM and gap b/n RAM and
689 * hotplug memory region -- all these are marked as reserved
690 * and as having no valid DRC.
691 */
692 dynamic_memory[0] = cpu_to_be32(addr >> 32);
693 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
694 dynamic_memory[2] = cpu_to_be32(0);
695 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
696 dynamic_memory[4] = cpu_to_be32(-1);
697 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED |
698 SPAPR_LMB_FLAGS_DRC_INVALID);
699 }
700
701 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE;
702 }
703 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len);
704 if (ret < 0) {
705 goto out;
706 }
707
708 /* ibm,associativity-lookup-arrays */
709 cur_index = int_buf;
710 int_buf[0] = cpu_to_be32(nr_nodes);
711 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */
712 cur_index += 2;
713 for (i = 0; i < nr_nodes; i++) {
714 uint32_t associativity[] = {
715 cpu_to_be32(0x0),
716 cpu_to_be32(0x0),
717 cpu_to_be32(0x0),
718 cpu_to_be32(i)
719 };
720 memcpy(cur_index, associativity, sizeof(associativity));
721 cur_index += 4;
722 }
723 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf,
724 (cur_index - int_buf) * sizeof(uint32_t));
725 out:
726 g_free(int_buf);
727 return ret;
728 }
729
730 static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt,
731 sPAPROptionVector *ov5_updates)
732 {
733 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
734 int ret = 0, offset;
735
736 /* Generate ibm,dynamic-reconfiguration-memory node if required */
737 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) {
738 g_assert(smc->dr_lmb_enabled);
739 ret = spapr_populate_drconf_memory(spapr, fdt);
740 if (ret) {
741 goto out;
742 }
743 }
744
745 offset = fdt_path_offset(fdt, "/chosen");
746 if (offset < 0) {
747 offset = fdt_add_subnode(fdt, 0, "chosen");
748 if (offset < 0) {
749 return offset;
750 }
751 }
752 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas,
753 "ibm,architecture-vec-5");
754
755 out:
756 return ret;
757 }
758
759 int spapr_h_cas_compose_response(sPAPRMachineState *spapr,
760 target_ulong addr, target_ulong size,
761 sPAPROptionVector *ov5_updates)
762 {
763 void *fdt, *fdt_skel;
764 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 };
765
766 size -= sizeof(hdr);
767
768 /* Create sceleton */
769 fdt_skel = g_malloc0(size);
770 _FDT((fdt_create(fdt_skel, size)));
771 _FDT((fdt_begin_node(fdt_skel, "")));
772 _FDT((fdt_end_node(fdt_skel)));
773 _FDT((fdt_finish(fdt_skel)));
774 fdt = g_malloc0(size);
775 _FDT((fdt_open_into(fdt_skel, fdt, size)));
776 g_free(fdt_skel);
777
778 /* Fixup cpu nodes */
779 _FDT((spapr_fixup_cpu_dt(fdt, spapr)));
780
781 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) {
782 return -1;
783 }
784
785 /* Pack resulting tree */
786 _FDT((fdt_pack(fdt)));
787
788 if (fdt_totalsize(fdt) + sizeof(hdr) > size) {
789 trace_spapr_cas_failed(size);
790 return -1;
791 }
792
793 cpu_physical_memory_write(addr, &hdr, sizeof(hdr));
794 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt));
795 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr));
796 g_free(fdt);
797
798 return 0;
799 }
800
801 static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt)
802 {
803 int rtas;
804 GString *hypertas = g_string_sized_new(256);
805 GString *qemu_hypertas = g_string_sized_new(256);
806 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) };
807 uint64_t max_hotplug_addr = spapr->hotplug_memory.base +
808 memory_region_size(&spapr->hotplug_memory.mr);
809 uint32_t lrdr_capacity[] = {
810 cpu_to_be32(max_hotplug_addr >> 32),
811 cpu_to_be32(max_hotplug_addr & 0xffffffff),
812 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE),
813 cpu_to_be32(max_cpus / smp_threads),
814 };
815
816 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas"));
817
818 /* hypertas */
819 add_str(hypertas, "hcall-pft");
820 add_str(hypertas, "hcall-term");
821 add_str(hypertas, "hcall-dabr");
822 add_str(hypertas, "hcall-interrupt");
823 add_str(hypertas, "hcall-tce");
824 add_str(hypertas, "hcall-vio");
825 add_str(hypertas, "hcall-splpar");
826 add_str(hypertas, "hcall-bulk");
827 add_str(hypertas, "hcall-set-mode");
828 add_str(hypertas, "hcall-sprg0");
829 add_str(hypertas, "hcall-copy");
830 add_str(hypertas, "hcall-debug");
831 add_str(qemu_hypertas, "hcall-memop1");
832
833 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
834 add_str(hypertas, "hcall-multi-tce");
835 }
836 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions",
837 hypertas->str, hypertas->len));
838 g_string_free(hypertas, TRUE);
839 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions",
840 qemu_hypertas->str, qemu_hypertas->len));
841 g_string_free(qemu_hypertas, TRUE);
842
843 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points",
844 refpoints, sizeof(refpoints)));
845
846 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max",
847 RTAS_ERROR_LOG_MAX));
848 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate",
849 RTAS_EVENT_SCAN_RATE));
850
851 if (msi_nonbroken) {
852 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0));
853 }
854
855 /*
856 * According to PAPR, rtas ibm,os-term does not guarantee a return
857 * back to the guest cpu.
858 *
859 * While an additional ibm,extended-os-term property indicates
860 * that rtas call return will always occur. Set this property.
861 */
862 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0));
863
864 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity",
865 lrdr_capacity, sizeof(lrdr_capacity)));
866
867 spapr_dt_rtas_tokens(fdt, rtas);
868 }
869
870 /* Prepare ibm,arch-vec-5-platform-support, which indicates the MMU features
871 * that the guest may request and thus the valid values for bytes 24..26 of
872 * option vector 5: */
873 static void spapr_dt_ov5_platform_support(void *fdt, int chosen)
874 {
875 char val[2 * 3] = {
876 24, 0x00, /* Hash/Radix, filled in below. */
877 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */
878 26, 0x40, /* Radix options: GTSE == yes. */
879 };
880
881 if (kvm_enabled()) {
882 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) {
883 val[1] = 0x80; /* OV5_MMU_BOTH */
884 } else if (kvmppc_has_cap_mmu_radix()) {
885 val[1] = 0x40; /* OV5_MMU_RADIX_300 */
886 } else {
887 val[1] = 0x00; /* Hash */
888 }
889 } else {
890 /* TODO: TCG case, hash */
891 val[1] = 0x00;
892 }
893 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support",
894 val, sizeof(val)));
895 }
896
897 static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt)
898 {
899 MachineState *machine = MACHINE(spapr);
900 int chosen;
901 const char *boot_device = machine->boot_order;
902 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus);
903 size_t cb = 0;
904 char *bootlist = get_boot_devices_list(&cb, true);
905
906 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen"));
907
908 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline));
909 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start",
910 spapr->initrd_base));
911 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end",
912 spapr->initrd_base + spapr->initrd_size));
913
914 if (spapr->kernel_size) {
915 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR),
916 cpu_to_be64(spapr->kernel_size) };
917
918 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel",
919 &kprop, sizeof(kprop)));
920 if (spapr->kernel_le) {
921 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0));
922 }
923 }
924 if (boot_menu) {
925 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu)));
926 }
927 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width));
928 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height));
929 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth));
930
931 if (cb && bootlist) {
932 int i;
933
934 for (i = 0; i < cb; i++) {
935 if (bootlist[i] == '\n') {
936 bootlist[i] = ' ';
937 }
938 }
939 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist));
940 }
941
942 if (boot_device && strlen(boot_device)) {
943 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device));
944 }
945
946 if (!spapr->has_graphics && stdout_path) {
947 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path));
948 }
949
950 spapr_dt_ov5_platform_support(fdt, chosen);
951
952 g_free(stdout_path);
953 g_free(bootlist);
954 }
955
956 static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt)
957 {
958 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR
959 * KVM to work under pHyp with some guest co-operation */
960 int hypervisor;
961 uint8_t hypercall[16];
962
963 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor"));
964 /* indicate KVM hypercall interface */
965 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm"));
966 if (kvmppc_has_cap_fixup_hcalls()) {
967 /*
968 * Older KVM versions with older guest kernels were broken
969 * with the magic page, don't allow the guest to map it.
970 */
971 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall,
972 sizeof(hypercall))) {
973 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions",
974 hypercall, sizeof(hypercall)));
975 }
976 }
977 }
978
979 static void *spapr_build_fdt(sPAPRMachineState *spapr,
980 hwaddr rtas_addr,
981 hwaddr rtas_size)
982 {
983 MachineState *machine = MACHINE(qdev_get_machine());
984 MachineClass *mc = MACHINE_GET_CLASS(machine);
985 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
986 int ret;
987 void *fdt;
988 sPAPRPHBState *phb;
989 char *buf;
990
991 fdt = g_malloc0(FDT_MAX_SIZE);
992 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
993
994 /* Root node */
995 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp"));
996 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)"));
997 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries"));
998
999 /*
1000 * Add info to guest to indentify which host is it being run on
1001 * and what is the uuid of the guest
1002 */
1003 if (kvmppc_get_host_model(&buf)) {
1004 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf));
1005 g_free(buf);
1006 }
1007 if (kvmppc_get_host_serial(&buf)) {
1008 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf));
1009 g_free(buf);
1010 }
1011
1012 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
1013
1014 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf));
1015 if (qemu_uuid_set) {
1016 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf));
1017 }
1018 g_free(buf);
1019
1020 if (qemu_get_vm_name()) {
1021 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name",
1022 qemu_get_vm_name()));
1023 }
1024
1025 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2));
1026 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2));
1027
1028 /* /interrupt controller */
1029 spapr_dt_xics(spapr->nr_servers, fdt, PHANDLE_XICP);
1030
1031 ret = spapr_populate_memory(spapr, fdt);
1032 if (ret < 0) {
1033 error_report("couldn't setup memory nodes in fdt");
1034 exit(1);
1035 }
1036
1037 /* /vdevice */
1038 spapr_dt_vdevice(spapr->vio_bus, fdt);
1039
1040 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) {
1041 ret = spapr_rng_populate_dt(fdt);
1042 if (ret < 0) {
1043 error_report("could not set up rng device in the fdt");
1044 exit(1);
1045 }
1046 }
1047
1048 QLIST_FOREACH(phb, &spapr->phbs, list) {
1049 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt);
1050 if (ret < 0) {
1051 error_report("couldn't setup PCI devices in fdt");
1052 exit(1);
1053 }
1054 }
1055
1056 /* cpus */
1057 spapr_populate_cpus_dt_node(fdt, spapr);
1058
1059 if (smc->dr_lmb_enabled) {
1060 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB));
1061 }
1062
1063 if (mc->has_hotpluggable_cpus) {
1064 int offset = fdt_path_offset(fdt, "/cpus");
1065 ret = spapr_drc_populate_dt(fdt, offset, NULL,
1066 SPAPR_DR_CONNECTOR_TYPE_CPU);
1067 if (ret < 0) {
1068 error_report("Couldn't set up CPU DR device tree properties");
1069 exit(1);
1070 }
1071 }
1072
1073 /* /event-sources */
1074 spapr_dt_events(spapr, fdt);
1075
1076 /* /rtas */
1077 spapr_dt_rtas(spapr, fdt);
1078
1079 /* /chosen */
1080 spapr_dt_chosen(spapr, fdt);
1081
1082 /* /hypervisor */
1083 if (kvm_enabled()) {
1084 spapr_dt_hypervisor(spapr, fdt);
1085 }
1086
1087 /* Build memory reserve map */
1088 if (spapr->kernel_size) {
1089 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size)));
1090 }
1091 if (spapr->initrd_size) {
1092 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size)));
1093 }
1094
1095 /* ibm,client-architecture-support updates */
1096 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas);
1097 if (ret < 0) {
1098 error_report("couldn't setup CAS properties fdt");
1099 exit(1);
1100 }
1101
1102 return fdt;
1103 }
1104
1105 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
1106 {
1107 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
1108 }
1109
1110 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp,
1111 PowerPCCPU *cpu)
1112 {
1113 CPUPPCState *env = &cpu->env;
1114
1115 /* The TCG path should also be holding the BQL at this point */
1116 g_assert(qemu_mutex_iothread_locked());
1117
1118 if (msr_pr) {
1119 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1120 env->gpr[3] = H_PRIVILEGE;
1121 } else {
1122 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]);
1123 }
1124 }
1125
1126 static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp)
1127 {
1128 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1129
1130 return spapr->patb_entry;
1131 }
1132
1133 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1134 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1135 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1136 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1137 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1138
1139 /*
1140 * Get the fd to access the kernel htab, re-opening it if necessary
1141 */
1142 static int get_htab_fd(sPAPRMachineState *spapr)
1143 {
1144 if (spapr->htab_fd >= 0) {
1145 return spapr->htab_fd;
1146 }
1147
1148 spapr->htab_fd = kvmppc_get_htab_fd(false);
1149 if (spapr->htab_fd < 0) {
1150 error_report("Unable to open fd for reading hash table from KVM: %s",
1151 strerror(errno));
1152 }
1153
1154 return spapr->htab_fd;
1155 }
1156
1157 void close_htab_fd(sPAPRMachineState *spapr)
1158 {
1159 if (spapr->htab_fd >= 0) {
1160 close(spapr->htab_fd);
1161 }
1162 spapr->htab_fd = -1;
1163 }
1164
1165 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp)
1166 {
1167 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1168
1169 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1;
1170 }
1171
1172 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp,
1173 hwaddr ptex, int n)
1174 {
1175 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1176 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64;
1177
1178 if (!spapr->htab) {
1179 /*
1180 * HTAB is controlled by KVM. Fetch into temporary buffer
1181 */
1182 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64);
1183 kvmppc_read_hptes(hptes, ptex, n);
1184 return hptes;
1185 }
1186
1187 /*
1188 * HTAB is controlled by QEMU. Just point to the internally
1189 * accessible PTEG.
1190 */
1191 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset);
1192 }
1193
1194 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp,
1195 const ppc_hash_pte64_t *hptes,
1196 hwaddr ptex, int n)
1197 {
1198 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1199
1200 if (!spapr->htab) {
1201 g_free((void *)hptes);
1202 }
1203
1204 /* Nothing to do for qemu managed HPT */
1205 }
1206
1207 static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex,
1208 uint64_t pte0, uint64_t pte1)
1209 {
1210 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1211 hwaddr offset = ptex * HASH_PTE_SIZE_64;
1212
1213 if (!spapr->htab) {
1214 kvmppc_write_hpte(ptex, pte0, pte1);
1215 } else {
1216 stq_p(spapr->htab + offset, pte0);
1217 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1);
1218 }
1219 }
1220
1221 static int spapr_hpt_shift_for_ramsize(uint64_t ramsize)
1222 {
1223 int shift;
1224
1225 /* We aim for a hash table of size 1/128 the size of RAM (rounded
1226 * up). The PAPR recommendation is actually 1/64 of RAM size, but
1227 * that's much more than is needed for Linux guests */
1228 shift = ctz64(pow2ceil(ramsize)) - 7;
1229 shift = MAX(shift, 18); /* Minimum architected size */
1230 shift = MIN(shift, 46); /* Maximum architected size */
1231 return shift;
1232 }
1233
1234 static void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift,
1235 Error **errp)
1236 {
1237 long rc;
1238
1239 /* Clean up any HPT info from a previous boot */
1240 g_free(spapr->htab);
1241 spapr->htab = NULL;
1242 spapr->htab_shift = 0;
1243 close_htab_fd(spapr);
1244
1245 rc = kvmppc_reset_htab(shift);
1246 if (rc < 0) {
1247 /* kernel-side HPT needed, but couldn't allocate one */
1248 error_setg_errno(errp, errno,
1249 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1250 shift);
1251 /* This is almost certainly fatal, but if the caller really
1252 * wants to carry on with shift == 0, it's welcome to try */
1253 } else if (rc > 0) {
1254 /* kernel-side HPT allocated */
1255 if (rc != shift) {
1256 error_setg(errp,
1257 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1258 shift, rc);
1259 }
1260
1261 spapr->htab_shift = shift;
1262 spapr->htab = NULL;
1263 } else {
1264 /* kernel-side HPT not needed, allocate in userspace instead */
1265 size_t size = 1ULL << shift;
1266 int i;
1267
1268 spapr->htab = qemu_memalign(size, size);
1269 if (!spapr->htab) {
1270 error_setg_errno(errp, errno,
1271 "Could not allocate HPT of order %d", shift);
1272 return;
1273 }
1274
1275 memset(spapr->htab, 0, size);
1276 spapr->htab_shift = shift;
1277
1278 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) {
1279 DIRTY_HPTE(HPTE(spapr->htab, i));
1280 }
1281 }
1282 }
1283
1284 void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr)
1285 {
1286 spapr_reallocate_hpt(spapr,
1287 spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size),
1288 &error_fatal);
1289 if (spapr->vrma_adjust) {
1290 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(),
1291 spapr->htab_shift);
1292 }
1293 /* We're setting up a hash table, so that means we're not radix */
1294 spapr->patb_entry = 0;
1295 }
1296
1297 static void find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque)
1298 {
1299 bool matched = false;
1300
1301 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
1302 matched = true;
1303 }
1304
1305 if (!matched) {
1306 error_report("Device %s is not supported by this machine yet.",
1307 qdev_fw_name(DEVICE(sbdev)));
1308 exit(1);
1309 }
1310 }
1311
1312 static void ppc_spapr_reset(void)
1313 {
1314 MachineState *machine = MACHINE(qdev_get_machine());
1315 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
1316 PowerPCCPU *first_ppc_cpu;
1317 uint32_t rtas_limit;
1318 hwaddr rtas_addr, fdt_addr;
1319 void *fdt;
1320 int rc;
1321
1322 /* Check for unknown sysbus devices */
1323 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL);
1324
1325 if (kvm_enabled() && kvmppc_has_cap_mmu_radix()) {
1326 /* If using KVM with radix mode available, VCPUs can be started
1327 * without a HPT because KVM will start them in radix mode.
1328 * Set the GR bit in PATB so that we know there is no HPT. */
1329 spapr->patb_entry = PATBE1_GR;
1330 } else {
1331 spapr->patb_entry = 0;
1332 spapr_setup_hpt_and_vrma(spapr);
1333 }
1334
1335 qemu_devices_reset();
1336
1337 /*
1338 * We place the device tree and RTAS just below either the top of the RMA,
1339 * or just below 2GB, whichever is lowere, so that it can be
1340 * processed with 32-bit real mode code if necessary
1341 */
1342 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR);
1343 rtas_addr = rtas_limit - RTAS_MAX_SIZE;
1344 fdt_addr = rtas_addr - FDT_MAX_SIZE;
1345
1346 /* if this reset wasn't generated by CAS, we should reset our
1347 * negotiated options and start from scratch */
1348 if (!spapr->cas_reboot) {
1349 spapr_ovec_cleanup(spapr->ov5_cas);
1350 spapr->ov5_cas = spapr_ovec_new();
1351 }
1352
1353 fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size);
1354
1355 spapr_load_rtas(spapr, fdt, rtas_addr);
1356
1357 rc = fdt_pack(fdt);
1358
1359 /* Should only fail if we've built a corrupted tree */
1360 assert(rc == 0);
1361
1362 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) {
1363 error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
1364 fdt_totalsize(fdt), FDT_MAX_SIZE);
1365 exit(1);
1366 }
1367
1368 /* Load the fdt */
1369 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
1370 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
1371 g_free(fdt);
1372
1373 /* Set up the entry state */
1374 first_ppc_cpu = POWERPC_CPU(first_cpu);
1375 first_ppc_cpu->env.gpr[3] = fdt_addr;
1376 first_ppc_cpu->env.gpr[5] = 0;
1377 first_cpu->halted = 0;
1378 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT;
1379
1380 spapr->cas_reboot = false;
1381 }
1382
1383 static void spapr_create_nvram(sPAPRMachineState *spapr)
1384 {
1385 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram");
1386 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
1387
1388 if (dinfo) {
1389 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
1390 &error_fatal);
1391 }
1392
1393 qdev_init_nofail(dev);
1394
1395 spapr->nvram = (struct sPAPRNVRAM *)dev;
1396 }
1397
1398 static void spapr_rtc_create(sPAPRMachineState *spapr)
1399 {
1400 object_initialize(&spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC);
1401 object_property_add_child(OBJECT(spapr), "rtc", OBJECT(&spapr->rtc),
1402 &error_fatal);
1403 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized",
1404 &error_fatal);
1405 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc),
1406 "date", &error_fatal);
1407 }
1408
1409 /* Returns whether we want to use VGA or not */
1410 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp)
1411 {
1412 switch (vga_interface_type) {
1413 case VGA_NONE:
1414 return false;
1415 case VGA_DEVICE:
1416 return true;
1417 case VGA_STD:
1418 case VGA_VIRTIO:
1419 return pci_vga_init(pci_bus) != NULL;
1420 default:
1421 error_setg(errp,
1422 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1423 return false;
1424 }
1425 }
1426
1427 static int spapr_post_load(void *opaque, int version_id)
1428 {
1429 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque;
1430 int err = 0;
1431
1432 if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) {
1433 int i;
1434 for (i = 0; i < spapr->nr_servers; i++) {
1435 icp_resend(&spapr->icps[i]);
1436 }
1437 }
1438
1439 /* In earlier versions, there was no separate qdev for the PAPR
1440 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1441 * So when migrating from those versions, poke the incoming offset
1442 * value into the RTC device */
1443 if (version_id < 3) {
1444 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset);
1445 }
1446
1447 return err;
1448 }
1449
1450 static bool version_before_3(void *opaque, int version_id)
1451 {
1452 return version_id < 3;
1453 }
1454
1455 static bool spapr_ov5_cas_needed(void *opaque)
1456 {
1457 sPAPRMachineState *spapr = opaque;
1458 sPAPROptionVector *ov5_mask = spapr_ovec_new();
1459 sPAPROptionVector *ov5_legacy = spapr_ovec_new();
1460 sPAPROptionVector *ov5_removed = spapr_ovec_new();
1461 bool cas_needed;
1462
1463 /* Prior to the introduction of sPAPROptionVector, we had two option
1464 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY.
1465 * Both of these options encode machine topology into the device-tree
1466 * in such a way that the now-booted OS should still be able to interact
1467 * appropriately with QEMU regardless of what options were actually
1468 * negotiatied on the source side.
1469 *
1470 * As such, we can avoid migrating the CAS-negotiated options if these
1471 * are the only options available on the current machine/platform.
1472 * Since these are the only options available for pseries-2.7 and
1473 * earlier, this allows us to maintain old->new/new->old migration
1474 * compatibility.
1475 *
1476 * For QEMU 2.8+, there are additional CAS-negotiatable options available
1477 * via default pseries-2.8 machines and explicit command-line parameters.
1478 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware
1479 * of the actual CAS-negotiated values to continue working properly. For
1480 * example, availability of memory unplug depends on knowing whether
1481 * OV5_HP_EVT was negotiated via CAS.
1482 *
1483 * Thus, for any cases where the set of available CAS-negotiatable
1484 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we
1485 * include the CAS-negotiated options in the migration stream.
1486 */
1487 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY);
1488 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY);
1489
1490 /* spapr_ovec_diff returns true if bits were removed. we avoid using
1491 * the mask itself since in the future it's possible "legacy" bits may be
1492 * removed via machine options, which could generate a false positive
1493 * that breaks migration.
1494 */
1495 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask);
1496 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy);
1497
1498 spapr_ovec_cleanup(ov5_mask);
1499 spapr_ovec_cleanup(ov5_legacy);
1500 spapr_ovec_cleanup(ov5_removed);
1501
1502 return cas_needed;
1503 }
1504
1505 static const VMStateDescription vmstate_spapr_ov5_cas = {
1506 .name = "spapr_option_vector_ov5_cas",
1507 .version_id = 1,
1508 .minimum_version_id = 1,
1509 .needed = spapr_ov5_cas_needed,
1510 .fields = (VMStateField[]) {
1511 VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1,
1512 vmstate_spapr_ovec, sPAPROptionVector),
1513 VMSTATE_END_OF_LIST()
1514 },
1515 };
1516
1517 static bool spapr_patb_entry_needed(void *opaque)
1518 {
1519 sPAPRMachineState *spapr = opaque;
1520
1521 return !!spapr->patb_entry;
1522 }
1523
1524 static const VMStateDescription vmstate_spapr_patb_entry = {
1525 .name = "spapr_patb_entry",
1526 .version_id = 1,
1527 .minimum_version_id = 1,
1528 .needed = spapr_patb_entry_needed,
1529 .fields = (VMStateField[]) {
1530 VMSTATE_UINT64(patb_entry, sPAPRMachineState),
1531 VMSTATE_END_OF_LIST()
1532 },
1533 };
1534
1535 static const VMStateDescription vmstate_spapr = {
1536 .name = "spapr",
1537 .version_id = 3,
1538 .minimum_version_id = 1,
1539 .post_load = spapr_post_load,
1540 .fields = (VMStateField[]) {
1541 /* used to be @next_irq */
1542 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4),
1543
1544 /* RTC offset */
1545 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3),
1546
1547 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2),
1548 VMSTATE_END_OF_LIST()
1549 },
1550 .subsections = (const VMStateDescription*[]) {
1551 &vmstate_spapr_ov5_cas,
1552 &vmstate_spapr_patb_entry,
1553 NULL
1554 }
1555 };
1556
1557 static int htab_save_setup(QEMUFile *f, void *opaque)
1558 {
1559 sPAPRMachineState *spapr = opaque;
1560
1561 /* "Iteration" header */
1562 qemu_put_be32(f, spapr->htab_shift);
1563
1564 if (spapr->htab) {
1565 spapr->htab_save_index = 0;
1566 spapr->htab_first_pass = true;
1567 } else {
1568 assert(kvm_enabled());
1569 }
1570
1571
1572 return 0;
1573 }
1574
1575 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr,
1576 int64_t max_ns)
1577 {
1578 bool has_timeout = max_ns != -1;
1579 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1580 int index = spapr->htab_save_index;
1581 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1582
1583 assert(spapr->htab_first_pass);
1584
1585 do {
1586 int chunkstart;
1587
1588 /* Consume invalid HPTEs */
1589 while ((index < htabslots)
1590 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1591 CLEAN_HPTE(HPTE(spapr->htab, index));
1592 index++;
1593 }
1594
1595 /* Consume valid HPTEs */
1596 chunkstart = index;
1597 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
1598 && HPTE_VALID(HPTE(spapr->htab, index))) {
1599 CLEAN_HPTE(HPTE(spapr->htab, index));
1600 index++;
1601 }
1602
1603 if (index > chunkstart) {
1604 int n_valid = index - chunkstart;
1605
1606 qemu_put_be32(f, chunkstart);
1607 qemu_put_be16(f, n_valid);
1608 qemu_put_be16(f, 0);
1609 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1610 HASH_PTE_SIZE_64 * n_valid);
1611
1612 if (has_timeout &&
1613 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1614 break;
1615 }
1616 }
1617 } while ((index < htabslots) && !qemu_file_rate_limit(f));
1618
1619 if (index >= htabslots) {
1620 assert(index == htabslots);
1621 index = 0;
1622 spapr->htab_first_pass = false;
1623 }
1624 spapr->htab_save_index = index;
1625 }
1626
1627 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr,
1628 int64_t max_ns)
1629 {
1630 bool final = max_ns < 0;
1631 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1632 int examined = 0, sent = 0;
1633 int index = spapr->htab_save_index;
1634 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1635
1636 assert(!spapr->htab_first_pass);
1637
1638 do {
1639 int chunkstart, invalidstart;
1640
1641 /* Consume non-dirty HPTEs */
1642 while ((index < htabslots)
1643 && !HPTE_DIRTY(HPTE(spapr->htab, index))) {
1644 index++;
1645 examined++;
1646 }
1647
1648 chunkstart = index;
1649 /* Consume valid dirty HPTEs */
1650 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
1651 && HPTE_DIRTY(HPTE(spapr->htab, index))
1652 && HPTE_VALID(HPTE(spapr->htab, index))) {
1653 CLEAN_HPTE(HPTE(spapr->htab, index));
1654 index++;
1655 examined++;
1656 }
1657
1658 invalidstart = index;
1659 /* Consume invalid dirty HPTEs */
1660 while ((index < htabslots) && (index - invalidstart < USHRT_MAX)
1661 && HPTE_DIRTY(HPTE(spapr->htab, index))
1662 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1663 CLEAN_HPTE(HPTE(spapr->htab, index));
1664 index++;
1665 examined++;
1666 }
1667
1668 if (index > chunkstart) {
1669 int n_valid = invalidstart - chunkstart;
1670 int n_invalid = index - invalidstart;
1671
1672 qemu_put_be32(f, chunkstart);
1673 qemu_put_be16(f, n_valid);
1674 qemu_put_be16(f, n_invalid);
1675 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1676 HASH_PTE_SIZE_64 * n_valid);
1677 sent += index - chunkstart;
1678
1679 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1680 break;
1681 }
1682 }
1683
1684 if (examined >= htabslots) {
1685 break;
1686 }
1687
1688 if (index >= htabslots) {
1689 assert(index == htabslots);
1690 index = 0;
1691 }
1692 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final));
1693
1694 if (index >= htabslots) {
1695 assert(index == htabslots);
1696 index = 0;
1697 }
1698
1699 spapr->htab_save_index = index;
1700
1701 return (examined >= htabslots) && (sent == 0) ? 1 : 0;
1702 }
1703
1704 #define MAX_ITERATION_NS 5000000 /* 5 ms */
1705 #define MAX_KVM_BUF_SIZE 2048
1706
1707 static int htab_save_iterate(QEMUFile *f, void *opaque)
1708 {
1709 sPAPRMachineState *spapr = opaque;
1710 int fd;
1711 int rc = 0;
1712
1713 /* Iteration header */
1714 qemu_put_be32(f, 0);
1715
1716 if (!spapr->htab) {
1717 assert(kvm_enabled());
1718
1719 fd = get_htab_fd(spapr);
1720 if (fd < 0) {
1721 return fd;
1722 }
1723
1724 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS);
1725 if (rc < 0) {
1726 return rc;
1727 }
1728 } else if (spapr->htab_first_pass) {
1729 htab_save_first_pass(f, spapr, MAX_ITERATION_NS);
1730 } else {
1731 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS);
1732 }
1733
1734 /* End marker */
1735 qemu_put_be32(f, 0);
1736 qemu_put_be16(f, 0);
1737 qemu_put_be16(f, 0);
1738
1739 return rc;
1740 }
1741
1742 static int htab_save_complete(QEMUFile *f, void *opaque)
1743 {
1744 sPAPRMachineState *spapr = opaque;
1745 int fd;
1746
1747 /* Iteration header */
1748 qemu_put_be32(f, 0);
1749
1750 if (!spapr->htab) {
1751 int rc;
1752
1753 assert(kvm_enabled());
1754
1755 fd = get_htab_fd(spapr);
1756 if (fd < 0) {
1757 return fd;
1758 }
1759
1760 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1);
1761 if (rc < 0) {
1762 return rc;
1763 }
1764 } else {
1765 if (spapr->htab_first_pass) {
1766 htab_save_first_pass(f, spapr, -1);
1767 }
1768 htab_save_later_pass(f, spapr, -1);
1769 }
1770
1771 /* End marker */
1772 qemu_put_be32(f, 0);
1773 qemu_put_be16(f, 0);
1774 qemu_put_be16(f, 0);
1775
1776 return 0;
1777 }
1778
1779 static int htab_load(QEMUFile *f, void *opaque, int version_id)
1780 {
1781 sPAPRMachineState *spapr = opaque;
1782 uint32_t section_hdr;
1783 int fd = -1;
1784
1785 if (version_id < 1 || version_id > 1) {
1786 error_report("htab_load() bad version");
1787 return -EINVAL;
1788 }
1789
1790 section_hdr = qemu_get_be32(f);
1791
1792 if (section_hdr) {
1793 Error *local_err = NULL;
1794
1795 /* First section gives the htab size */
1796 spapr_reallocate_hpt(spapr, section_hdr, &local_err);
1797 if (local_err) {
1798 error_report_err(local_err);
1799 return -EINVAL;
1800 }
1801 return 0;
1802 }
1803
1804 if (!spapr->htab) {
1805 assert(kvm_enabled());
1806
1807 fd = kvmppc_get_htab_fd(true);
1808 if (fd < 0) {
1809 error_report("Unable to open fd to restore KVM hash table: %s",
1810 strerror(errno));
1811 }
1812 }
1813
1814 while (true) {
1815 uint32_t index;
1816 uint16_t n_valid, n_invalid;
1817
1818 index = qemu_get_be32(f);
1819 n_valid = qemu_get_be16(f);
1820 n_invalid = qemu_get_be16(f);
1821
1822 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) {
1823 /* End of Stream */
1824 break;
1825 }
1826
1827 if ((index + n_valid + n_invalid) >
1828 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) {
1829 /* Bad index in stream */
1830 error_report(
1831 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
1832 index, n_valid, n_invalid, spapr->htab_shift);
1833 return -EINVAL;
1834 }
1835
1836 if (spapr->htab) {
1837 if (n_valid) {
1838 qemu_get_buffer(f, HPTE(spapr->htab, index),
1839 HASH_PTE_SIZE_64 * n_valid);
1840 }
1841 if (n_invalid) {
1842 memset(HPTE(spapr->htab, index + n_valid), 0,
1843 HASH_PTE_SIZE_64 * n_invalid);
1844 }
1845 } else {
1846 int rc;
1847
1848 assert(fd >= 0);
1849
1850 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid);
1851 if (rc < 0) {
1852 return rc;
1853 }
1854 }
1855 }
1856
1857 if (!spapr->htab) {
1858 assert(fd >= 0);
1859 close(fd);
1860 }
1861
1862 return 0;
1863 }
1864
1865 static void htab_cleanup(void *opaque)
1866 {
1867 sPAPRMachineState *spapr = opaque;
1868
1869 close_htab_fd(spapr);
1870 }
1871
1872 static SaveVMHandlers savevm_htab_handlers = {
1873 .save_live_setup = htab_save_setup,
1874 .save_live_iterate = htab_save_iterate,
1875 .save_live_complete_precopy = htab_save_complete,
1876 .cleanup = htab_cleanup,
1877 .load_state = htab_load,
1878 };
1879
1880 static void spapr_boot_set(void *opaque, const char *boot_device,
1881 Error **errp)
1882 {
1883 MachineState *machine = MACHINE(qdev_get_machine());
1884 machine->boot_order = g_strdup(boot_device);
1885 }
1886
1887 /*
1888 * Reset routine for LMB DR devices.
1889 *
1890 * Unlike PCI DR devices, LMB DR devices explicitly register this reset
1891 * routine. Reset for PCI DR devices will be handled by PHB reset routine
1892 * when it walks all its children devices. LMB devices reset occurs
1893 * as part of spapr_ppc_reset().
1894 */
1895 static void spapr_drc_reset(void *opaque)
1896 {
1897 sPAPRDRConnector *drc = opaque;
1898 DeviceState *d = DEVICE(drc);
1899
1900 if (d) {
1901 device_reset(d);
1902 }
1903 }
1904
1905 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr)
1906 {
1907 MachineState *machine = MACHINE(spapr);
1908 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
1909 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size;
1910 int i;
1911
1912 for (i = 0; i < nr_lmbs; i++) {
1913 sPAPRDRConnector *drc;
1914 uint64_t addr;
1915
1916 addr = i * lmb_size + spapr->hotplug_memory.base;
1917 drc = spapr_dr_connector_new(OBJECT(spapr), SPAPR_DR_CONNECTOR_TYPE_LMB,
1918 addr/lmb_size);
1919 qemu_register_reset(spapr_drc_reset, drc);
1920 }
1921 }
1922
1923 /*
1924 * If RAM size, maxmem size and individual node mem sizes aren't aligned
1925 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
1926 * since we can't support such unaligned sizes with DRCONF_MEMORY.
1927 */
1928 static void spapr_validate_node_memory(MachineState *machine, Error **errp)
1929 {
1930 int i;
1931
1932 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) {
1933 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT
1934 " is not aligned to %llu MiB",
1935 machine->ram_size,
1936 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1937 return;
1938 }
1939
1940 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) {
1941 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT
1942 " is not aligned to %llu MiB",
1943 machine->ram_size,
1944 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1945 return;
1946 }
1947
1948 for (i = 0; i < nb_numa_nodes; i++) {
1949 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) {
1950 error_setg(errp,
1951 "Node %d memory size 0x%" PRIx64
1952 " is not aligned to %llu MiB",
1953 i, numa_info[i].node_mem,
1954 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1955 return;
1956 }
1957 }
1958 }
1959
1960 /* find cpu slot in machine->possible_cpus by core_id */
1961 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
1962 {
1963 int index = id / smp_threads;
1964
1965 if (index >= ms->possible_cpus->len) {
1966 return NULL;
1967 }
1968 if (idx) {
1969 *idx = index;
1970 }
1971 return &ms->possible_cpus->cpus[index];
1972 }
1973
1974 static void spapr_init_cpus(sPAPRMachineState *spapr)
1975 {
1976 MachineState *machine = MACHINE(spapr);
1977 MachineClass *mc = MACHINE_GET_CLASS(machine);
1978 char *type = spapr_get_cpu_core_type(machine->cpu_model);
1979 int smt = kvmppc_smt_threads();
1980 const CPUArchIdList *possible_cpus;
1981 int boot_cores_nr = smp_cpus / smp_threads;
1982 int i;
1983
1984 if (!type) {
1985 error_report("Unable to find sPAPR CPU Core definition");
1986 exit(1);
1987 }
1988
1989 possible_cpus = mc->possible_cpu_arch_ids(machine);
1990 if (mc->has_hotpluggable_cpus) {
1991 if (smp_cpus % smp_threads) {
1992 error_report("smp_cpus (%u) must be multiple of threads (%u)",
1993 smp_cpus, smp_threads);
1994 exit(1);
1995 }
1996 if (max_cpus % smp_threads) {
1997 error_report("max_cpus (%u) must be multiple of threads (%u)",
1998 max_cpus, smp_threads);
1999 exit(1);
2000 }
2001 } else {
2002 if (max_cpus != smp_cpus) {
2003 error_report("This machine version does not support CPU hotplug");
2004 exit(1);
2005 }
2006 boot_cores_nr = possible_cpus->len;
2007 }
2008
2009 for (i = 0; i < possible_cpus->len; i++) {
2010 int core_id = i * smp_threads;
2011
2012 if (mc->has_hotpluggable_cpus) {
2013 sPAPRDRConnector *drc =
2014 spapr_dr_connector_new(OBJECT(spapr),
2015 SPAPR_DR_CONNECTOR_TYPE_CPU,
2016 (core_id / smp_threads) * smt);
2017
2018 qemu_register_reset(spapr_drc_reset, drc);
2019 }
2020
2021 if (i < boot_cores_nr) {
2022 Object *core = object_new(type);
2023 int nr_threads = smp_threads;
2024
2025 /* Handle the partially filled core for older machine types */
2026 if ((i + 1) * smp_threads >= smp_cpus) {
2027 nr_threads = smp_cpus - i * smp_threads;
2028 }
2029
2030 object_property_set_int(core, nr_threads, "nr-threads",
2031 &error_fatal);
2032 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID,
2033 &error_fatal);
2034 object_property_set_bool(core, true, "realized", &error_fatal);
2035 }
2036 }
2037 g_free(type);
2038 }
2039
2040 /* pSeries LPAR / sPAPR hardware init */
2041 static void ppc_spapr_init(MachineState *machine)
2042 {
2043 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
2044 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
2045 const char *kernel_filename = machine->kernel_filename;
2046 const char *initrd_filename = machine->initrd_filename;
2047 PCIHostState *phb;
2048 int i;
2049 MemoryRegion *sysmem = get_system_memory();
2050 MemoryRegion *ram = g_new(MemoryRegion, 1);
2051 MemoryRegion *rma_region;
2052 void *rma = NULL;
2053 hwaddr rma_alloc_size;
2054 hwaddr node0_size = spapr_node0_size();
2055 long load_limit, fw_size;
2056 char *filename;
2057 int smt = kvmppc_smt_threads();
2058
2059 msi_nonbroken = true;
2060
2061 QLIST_INIT(&spapr->phbs);
2062
2063 /* Allocate RMA if necessary */
2064 rma_alloc_size = kvmppc_alloc_rma(&rma);
2065
2066 if (rma_alloc_size == -1) {
2067 error_report("Unable to create RMA");
2068 exit(1);
2069 }
2070
2071 if (rma_alloc_size && (rma_alloc_size < node0_size)) {
2072 spapr->rma_size = rma_alloc_size;
2073 } else {
2074 spapr->rma_size = node0_size;
2075
2076 /* With KVM, we don't actually know whether KVM supports an
2077 * unbounded RMA (PR KVM) or is limited by the hash table size
2078 * (HV KVM using VRMA), so we always assume the latter
2079 *
2080 * In that case, we also limit the initial allocations for RTAS
2081 * etc... to 256M since we have no way to know what the VRMA size
2082 * is going to be as it depends on the size of the hash table
2083 * isn't determined yet.
2084 */
2085 if (kvm_enabled()) {
2086 spapr->vrma_adjust = 1;
2087 spapr->rma_size = MIN(spapr->rma_size, 0x10000000);
2088 }
2089
2090 /* Actually we don't support unbounded RMA anymore since we
2091 * added proper emulation of HV mode. The max we can get is
2092 * 16G which also happens to be what we configure for PAPR
2093 * mode so make sure we don't do anything bigger than that
2094 */
2095 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull);
2096 }
2097
2098 if (spapr->rma_size > node0_size) {
2099 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")",
2100 spapr->rma_size);
2101 exit(1);
2102 }
2103
2104 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
2105 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD;
2106
2107 /* Set up Interrupt Controller before we create the VCPUs */
2108 xics_system_init(machine, DIV_ROUND_UP(max_cpus * smt, smp_threads),
2109 XICS_IRQS_SPAPR, &error_fatal);
2110
2111 /* Set up containers for ibm,client-set-architecture negotiated options */
2112 spapr->ov5 = spapr_ovec_new();
2113 spapr->ov5_cas = spapr_ovec_new();
2114
2115 if (smc->dr_lmb_enabled) {
2116 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY);
2117 spapr_validate_node_memory(machine, &error_fatal);
2118 }
2119
2120 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY);
2121 if (kvmppc_has_cap_mmu_radix()) {
2122 /* KVM always allows GTSE with radix... */
2123 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE);
2124 }
2125 /* ... but not with hash (currently). */
2126
2127 /* advertise support for dedicated HP event source to guests */
2128 if (spapr->use_hotplug_event_source) {
2129 spapr_ovec_set(spapr->ov5, OV5_HP_EVT);
2130 }
2131
2132 /* init CPUs */
2133 if (machine->cpu_model == NULL) {
2134 machine->cpu_model = kvm_enabled() ? "host" : smc->tcg_default_cpu;
2135 }
2136
2137 ppc_cpu_parse_features(machine->cpu_model);
2138
2139 spapr_init_cpus(spapr);
2140
2141 if (kvm_enabled()) {
2142 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
2143 kvmppc_enable_logical_ci_hcalls();
2144 kvmppc_enable_set_mode_hcall();
2145
2146 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */
2147 kvmppc_enable_clear_ref_mod_hcalls();
2148 }
2149
2150 /* allocate RAM */
2151 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram",
2152 machine->ram_size);
2153 memory_region_add_subregion(sysmem, 0, ram);
2154
2155 if (rma_alloc_size && rma) {
2156 rma_region = g_new(MemoryRegion, 1);
2157 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma",
2158 rma_alloc_size, rma);
2159 vmstate_register_ram_global(rma_region);
2160 memory_region_add_subregion(sysmem, 0, rma_region);
2161 }
2162
2163 /* initialize hotplug memory address space */
2164 if (machine->ram_size < machine->maxram_size) {
2165 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size;
2166 /*
2167 * Limit the number of hotpluggable memory slots to half the number
2168 * slots that KVM supports, leaving the other half for PCI and other
2169 * devices. However ensure that number of slots doesn't drop below 32.
2170 */
2171 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 :
2172 SPAPR_MAX_RAM_SLOTS;
2173
2174 if (max_memslots < SPAPR_MAX_RAM_SLOTS) {
2175 max_memslots = SPAPR_MAX_RAM_SLOTS;
2176 }
2177 if (machine->ram_slots > max_memslots) {
2178 error_report("Specified number of memory slots %"
2179 PRIu64" exceeds max supported %d",
2180 machine->ram_slots, max_memslots);
2181 exit(1);
2182 }
2183
2184 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size,
2185 SPAPR_HOTPLUG_MEM_ALIGN);
2186 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr),
2187 "hotplug-memory", hotplug_mem_size);
2188 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base,
2189 &spapr->hotplug_memory.mr);
2190 }
2191
2192 if (smc->dr_lmb_enabled) {
2193 spapr_create_lmb_dr_connectors(spapr);
2194 }
2195
2196 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
2197 if (!filename) {
2198 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin");
2199 exit(1);
2200 }
2201 spapr->rtas_size = get_image_size(filename);
2202 if (spapr->rtas_size < 0) {
2203 error_report("Could not get size of LPAR rtas '%s'", filename);
2204 exit(1);
2205 }
2206 spapr->rtas_blob = g_malloc(spapr->rtas_size);
2207 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) {
2208 error_report("Could not load LPAR rtas '%s'", filename);
2209 exit(1);
2210 }
2211 if (spapr->rtas_size > RTAS_MAX_SIZE) {
2212 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)",
2213 (size_t)spapr->rtas_size, RTAS_MAX_SIZE);
2214 exit(1);
2215 }
2216 g_free(filename);
2217
2218 /* Set up RTAS event infrastructure */
2219 spapr_events_init(spapr);
2220
2221 /* Set up the RTC RTAS interfaces */
2222 spapr_rtc_create(spapr);
2223
2224 /* Set up VIO bus */
2225 spapr->vio_bus = spapr_vio_bus_init();
2226
2227 for (i = 0; i < MAX_SERIAL_PORTS; i++) {
2228 if (serial_hds[i]) {
2229 spapr_vty_create(spapr->vio_bus, serial_hds[i]);
2230 }
2231 }
2232
2233 /* We always have at least the nvram device on VIO */
2234 spapr_create_nvram(spapr);
2235
2236 /* Set up PCI */
2237 spapr_pci_rtas_init();
2238
2239 phb = spapr_create_phb(spapr, 0);
2240
2241 for (i = 0; i < nb_nics; i++) {
2242 NICInfo *nd = &nd_table[i];
2243
2244 if (!nd->model) {
2245 nd->model = g_strdup("ibmveth");
2246 }
2247
2248 if (strcmp(nd->model, "ibmveth") == 0) {
2249 spapr_vlan_create(spapr->vio_bus, nd);
2250 } else {
2251 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL);
2252 }
2253 }
2254
2255 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
2256 spapr_vscsi_create(spapr->vio_bus);
2257 }
2258
2259 /* Graphics */
2260 if (spapr_vga_init(phb->bus, &error_fatal)) {
2261 spapr->has_graphics = true;
2262 machine->usb |= defaults_enabled() && !machine->usb_disabled;
2263 }
2264
2265 if (machine->usb) {
2266 if (smc->use_ohci_by_default) {
2267 pci_create_simple(phb->bus, -1, "pci-ohci");
2268 } else {
2269 pci_create_simple(phb->bus, -1, "nec-usb-xhci");
2270 }
2271
2272 if (spapr->has_graphics) {
2273 USBBus *usb_bus = usb_bus_find(-1);
2274
2275 usb_create_simple(usb_bus, "usb-kbd");
2276 usb_create_simple(usb_bus, "usb-mouse");
2277 }
2278 }
2279
2280 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) {
2281 error_report(
2282 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
2283 MIN_RMA_SLOF);
2284 exit(1);
2285 }
2286
2287 if (kernel_filename) {
2288 uint64_t lowaddr = 0;
2289
2290 spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address,
2291 NULL, NULL, &lowaddr, NULL, 1,
2292 PPC_ELF_MACHINE, 0, 0);
2293 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) {
2294 spapr->kernel_size = load_elf(kernel_filename,
2295 translate_kernel_address, NULL, NULL,
2296 &lowaddr, NULL, 0, PPC_ELF_MACHINE,
2297 0, 0);
2298 spapr->kernel_le = spapr->kernel_size > 0;
2299 }
2300 if (spapr->kernel_size < 0) {
2301 error_report("error loading %s: %s", kernel_filename,
2302 load_elf_strerror(spapr->kernel_size));
2303 exit(1);
2304 }
2305
2306 /* load initrd */
2307 if (initrd_filename) {
2308 /* Try to locate the initrd in the gap between the kernel
2309 * and the firmware. Add a bit of space just in case
2310 */
2311 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size
2312 + 0x1ffff) & ~0xffff;
2313 spapr->initrd_size = load_image_targphys(initrd_filename,
2314 spapr->initrd_base,
2315 load_limit
2316 - spapr->initrd_base);
2317 if (spapr->initrd_size < 0) {
2318 error_report("could not load initial ram disk '%s'",
2319 initrd_filename);
2320 exit(1);
2321 }
2322 }
2323 }
2324
2325 if (bios_name == NULL) {
2326 bios_name = FW_FILE_NAME;
2327 }
2328 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
2329 if (!filename) {
2330 error_report("Could not find LPAR firmware '%s'", bios_name);
2331 exit(1);
2332 }
2333 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
2334 if (fw_size <= 0) {
2335 error_report("Could not load LPAR firmware '%s'", filename);
2336 exit(1);
2337 }
2338 g_free(filename);
2339
2340 /* FIXME: Should register things through the MachineState's qdev
2341 * interface, this is a legacy from the sPAPREnvironment structure
2342 * which predated MachineState but had a similar function */
2343 vmstate_register(NULL, 0, &vmstate_spapr, spapr);
2344 register_savevm_live(NULL, "spapr/htab", -1, 1,
2345 &savevm_htab_handlers, spapr);
2346
2347 /* used by RTAS */
2348 QTAILQ_INIT(&spapr->ccs_list);
2349 qemu_register_reset(spapr_ccs_reset_hook, spapr);
2350
2351 qemu_register_boot_set(spapr_boot_set, spapr);
2352
2353 /* to stop and start vmclock */
2354 if (kvm_enabled()) {
2355 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change,
2356 &spapr->tb);
2357 }
2358 }
2359
2360 static int spapr_kvm_type(const char *vm_type)
2361 {
2362 if (!vm_type) {
2363 return 0;
2364 }
2365
2366 if (!strcmp(vm_type, "HV")) {
2367 return 1;
2368 }
2369
2370 if (!strcmp(vm_type, "PR")) {
2371 return 2;
2372 }
2373
2374 error_report("Unknown kvm-type specified '%s'", vm_type);
2375 exit(1);
2376 }
2377
2378 /*
2379 * Implementation of an interface to adjust firmware path
2380 * for the bootindex property handling.
2381 */
2382 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus,
2383 DeviceState *dev)
2384 {
2385 #define CAST(type, obj, name) \
2386 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
2387 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE);
2388 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE);
2389
2390 if (d) {
2391 void *spapr = CAST(void, bus->parent, "spapr-vscsi");
2392 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI);
2393 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE);
2394
2395 if (spapr) {
2396 /*
2397 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
2398 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun
2399 * in the top 16 bits of the 64-bit LUN
2400 */
2401 unsigned id = 0x8000 | (d->id << 8) | d->lun;
2402 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2403 (uint64_t)id << 48);
2404 } else if (virtio) {
2405 /*
2406 * We use SRP luns of the form 01000000 | (target << 8) | lun
2407 * in the top 32 bits of the 64-bit LUN
2408 * Note: the quote above is from SLOF and it is wrong,
2409 * the actual binding is:
2410 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
2411 */
2412 unsigned id = 0x1000000 | (d->id << 16) | d->lun;
2413 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2414 (uint64_t)id << 32);
2415 } else if (usb) {
2416 /*
2417 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
2418 * in the top 32 bits of the 64-bit LUN
2419 */
2420 unsigned usb_port = atoi(usb->port->path);
2421 unsigned id = 0x1000000 | (usb_port << 16) | d->lun;
2422 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2423 (uint64_t)id << 32);
2424 }
2425 }
2426
2427 /*
2428 * SLOF probes the USB devices, and if it recognizes that the device is a
2429 * storage device, it changes its name to "storage" instead of "usb-host",
2430 * and additionally adds a child node for the SCSI LUN, so the correct
2431 * boot path in SLOF is something like .../storage@1/disk@xxx" instead.
2432 */
2433 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) {
2434 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE);
2435 if (usb_host_dev_is_scsi_storage(usbdev)) {
2436 return g_strdup_printf("storage@%s/disk", usbdev->port->path);
2437 }
2438 }
2439
2440 if (phb) {
2441 /* Replace "pci" with "pci@800000020000000" */
2442 return g_strdup_printf("pci@%"PRIX64, phb->buid);
2443 }
2444
2445 return NULL;
2446 }
2447
2448 static char *spapr_get_kvm_type(Object *obj, Error **errp)
2449 {
2450 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2451
2452 return g_strdup(spapr->kvm_type);
2453 }
2454
2455 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp)
2456 {
2457 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2458
2459 g_free(spapr->kvm_type);
2460 spapr->kvm_type = g_strdup(value);
2461 }
2462
2463 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp)
2464 {
2465 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2466
2467 return spapr->use_hotplug_event_source;
2468 }
2469
2470 static void spapr_set_modern_hotplug_events(Object *obj, bool value,
2471 Error **errp)
2472 {
2473 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2474
2475 spapr->use_hotplug_event_source = value;
2476 }
2477
2478 static void spapr_machine_initfn(Object *obj)
2479 {
2480 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2481
2482 spapr->htab_fd = -1;
2483 spapr->use_hotplug_event_source = true;
2484 object_property_add_str(obj, "kvm-type",
2485 spapr_get_kvm_type, spapr_set_kvm_type, NULL);
2486 object_property_set_description(obj, "kvm-type",
2487 "Specifies the KVM virtualization mode (HV, PR)",
2488 NULL);
2489 object_property_add_bool(obj, "modern-hotplug-events",
2490 spapr_get_modern_hotplug_events,
2491 spapr_set_modern_hotplug_events,
2492 NULL);
2493 object_property_set_description(obj, "modern-hotplug-events",
2494 "Use dedicated hotplug event mechanism in"
2495 " place of standard EPOW events when possible"
2496 " (required for memory hot-unplug support)",
2497 NULL);
2498 }
2499
2500 static void spapr_machine_finalizefn(Object *obj)
2501 {
2502 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2503
2504 g_free(spapr->kvm_type);
2505 }
2506
2507 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg)
2508 {
2509 cpu_synchronize_state(cs);
2510 ppc_cpu_do_system_reset(cs);
2511 }
2512
2513 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp)
2514 {
2515 CPUState *cs;
2516
2517 CPU_FOREACH(cs) {
2518 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL);
2519 }
2520 }
2521
2522 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size,
2523 uint32_t node, bool dedicated_hp_event_source,
2524 Error **errp)
2525 {
2526 sPAPRDRConnector *drc;
2527 sPAPRDRConnectorClass *drck;
2528 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE;
2529 int i, fdt_offset, fdt_size;
2530 void *fdt;
2531 uint64_t addr = addr_start;
2532
2533 for (i = 0; i < nr_lmbs; i++) {
2534 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB,
2535 addr/SPAPR_MEMORY_BLOCK_SIZE);
2536 g_assert(drc);
2537
2538 fdt = create_device_tree(&fdt_size);
2539 fdt_offset = spapr_populate_memory_node(fdt, node, addr,
2540 SPAPR_MEMORY_BLOCK_SIZE);
2541
2542 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2543 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, errp);
2544 addr += SPAPR_MEMORY_BLOCK_SIZE;
2545 if (!dev->hotplugged) {
2546 /* guests expect coldplugged LMBs to be pre-allocated */
2547 drck->set_allocation_state(drc, SPAPR_DR_ALLOCATION_STATE_USABLE);
2548 drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED);
2549 }
2550 }
2551 /* send hotplug notification to the
2552 * guest only in case of hotplugged memory
2553 */
2554 if (dev->hotplugged) {
2555 if (dedicated_hp_event_source) {
2556 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB,
2557 addr_start / SPAPR_MEMORY_BLOCK_SIZE);
2558 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2559 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
2560 nr_lmbs,
2561 drck->get_index(drc));
2562 } else {
2563 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB,
2564 nr_lmbs);
2565 }
2566 }
2567 }
2568
2569 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2570 uint32_t node, Error **errp)
2571 {
2572 Error *local_err = NULL;
2573 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev);
2574 PCDIMMDevice *dimm = PC_DIMM(dev);
2575 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2576 MemoryRegion *mr = ddc->get_memory_region(dimm);
2577 uint64_t align = memory_region_get_alignment(mr);
2578 uint64_t size = memory_region_size(mr);
2579 uint64_t addr;
2580 char *mem_dev;
2581
2582 if (size % SPAPR_MEMORY_BLOCK_SIZE) {
2583 error_setg(&local_err, "Hotplugged memory size must be a multiple of "
2584 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE/M_BYTE);
2585 goto out;
2586 }
2587
2588 mem_dev = object_property_get_str(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, NULL);
2589 if (mem_dev && !kvmppc_is_mem_backend_page_size_ok(mem_dev)) {
2590 error_setg(&local_err, "Memory backend has bad page size. "
2591 "Use 'memory-backend-file' with correct mem-path.");
2592 goto out;
2593 }
2594
2595 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err);
2596 if (local_err) {
2597 goto out;
2598 }
2599
2600 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err);
2601 if (local_err) {
2602 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr);
2603 goto out;
2604 }
2605
2606 spapr_add_lmbs(dev, addr, size, node,
2607 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT),
2608 &error_abort);
2609
2610 out:
2611 error_propagate(errp, local_err);
2612 }
2613
2614 typedef struct sPAPRDIMMState {
2615 uint32_t nr_lmbs;
2616 } sPAPRDIMMState;
2617
2618 static void spapr_lmb_release(DeviceState *dev, void *opaque)
2619 {
2620 sPAPRDIMMState *ds = (sPAPRDIMMState *)opaque;
2621 HotplugHandler *hotplug_ctrl;
2622
2623 if (--ds->nr_lmbs) {
2624 return;
2625 }
2626
2627 g_free(ds);
2628
2629 /*
2630 * Now that all the LMBs have been removed by the guest, call the
2631 * pc-dimm unplug handler to cleanup up the pc-dimm device.
2632 */
2633 hotplug_ctrl = qdev_get_hotplug_handler(dev);
2634 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort);
2635 }
2636
2637 static void spapr_del_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size,
2638 Error **errp)
2639 {
2640 sPAPRDRConnector *drc;
2641 sPAPRDRConnectorClass *drck;
2642 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE;
2643 int i;
2644 sPAPRDIMMState *ds = g_malloc0(sizeof(sPAPRDIMMState));
2645 uint64_t addr = addr_start;
2646
2647 ds->nr_lmbs = nr_lmbs;
2648 for (i = 0; i < nr_lmbs; i++) {
2649 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB,
2650 addr / SPAPR_MEMORY_BLOCK_SIZE);
2651 g_assert(drc);
2652
2653 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2654 drck->detach(drc, dev, spapr_lmb_release, ds, errp);
2655 addr += SPAPR_MEMORY_BLOCK_SIZE;
2656 }
2657
2658 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB,
2659 addr_start / SPAPR_MEMORY_BLOCK_SIZE);
2660 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2661 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
2662 nr_lmbs,
2663 drck->get_index(drc));
2664 }
2665
2666 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev,
2667 Error **errp)
2668 {
2669 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev);
2670 PCDIMMDevice *dimm = PC_DIMM(dev);
2671 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2672 MemoryRegion *mr = ddc->get_memory_region(dimm);
2673
2674 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr);
2675 object_unparent(OBJECT(dev));
2676 }
2677
2678 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev,
2679 DeviceState *dev, Error **errp)
2680 {
2681 Error *local_err = NULL;
2682 PCDIMMDevice *dimm = PC_DIMM(dev);
2683 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2684 MemoryRegion *mr = ddc->get_memory_region(dimm);
2685 uint64_t size = memory_region_size(mr);
2686 uint64_t addr;
2687
2688 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err);
2689 if (local_err) {
2690 goto out;
2691 }
2692
2693 spapr_del_lmbs(dev, addr, size, &error_abort);
2694 out:
2695 error_propagate(errp, local_err);
2696 }
2697
2698 void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset,
2699 sPAPRMachineState *spapr)
2700 {
2701 PowerPCCPU *cpu = POWERPC_CPU(cs);
2702 DeviceClass *dc = DEVICE_GET_CLASS(cs);
2703 int id = ppc_get_vcpu_dt_id(cpu);
2704 void *fdt;
2705 int offset, fdt_size;
2706 char *nodename;
2707
2708 fdt = create_device_tree(&fdt_size);
2709 nodename = g_strdup_printf("%s@%x", dc->fw_name, id);
2710 offset = fdt_add_subnode(fdt, 0, nodename);
2711
2712 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
2713 g_free(nodename);
2714
2715 *fdt_offset = offset;
2716 return fdt;
2717 }
2718
2719 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev,
2720 Error **errp)
2721 {
2722 MachineState *ms = MACHINE(qdev_get_machine());
2723 CPUCore *cc = CPU_CORE(dev);
2724 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL);
2725
2726 core_slot->cpu = NULL;
2727 object_unparent(OBJECT(dev));
2728 }
2729
2730 static void spapr_core_release(DeviceState *dev, void *opaque)
2731 {
2732 HotplugHandler *hotplug_ctrl;
2733
2734 hotplug_ctrl = qdev_get_hotplug_handler(dev);
2735 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort);
2736 }
2737
2738 static
2739 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev,
2740 Error **errp)
2741 {
2742 int index;
2743 sPAPRDRConnector *drc;
2744 sPAPRDRConnectorClass *drck;
2745 Error *local_err = NULL;
2746 CPUCore *cc = CPU_CORE(dev);
2747 int smt = kvmppc_smt_threads();
2748
2749 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) {
2750 error_setg(errp, "Unable to find CPU core with core-id: %d",
2751 cc->core_id);
2752 return;
2753 }
2754 if (index == 0) {
2755 error_setg(errp, "Boot CPU core may not be unplugged");
2756 return;
2757 }
2758
2759 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt);
2760 g_assert(drc);
2761
2762 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2763 drck->detach(drc, dev, spapr_core_release, NULL, &local_err);
2764 if (local_err) {
2765 error_propagate(errp, local_err);
2766 return;
2767 }
2768
2769 spapr_hotplug_req_remove_by_index(drc);
2770 }
2771
2772 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2773 Error **errp)
2774 {
2775 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
2776 MachineClass *mc = MACHINE_GET_CLASS(spapr);
2777 sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev));
2778 CPUCore *cc = CPU_CORE(dev);
2779 CPUState *cs = CPU(core->threads);
2780 sPAPRDRConnector *drc;
2781 Error *local_err = NULL;
2782 void *fdt = NULL;
2783 int fdt_offset = 0;
2784 int smt = kvmppc_smt_threads();
2785 CPUArchId *core_slot;
2786 int index;
2787
2788 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
2789 if (!core_slot) {
2790 error_setg(errp, "Unable to find CPU core with core-id: %d",
2791 cc->core_id);
2792 return;
2793 }
2794 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt);
2795
2796 g_assert(drc || !mc->has_hotpluggable_cpus);
2797
2798 /*
2799 * Setup CPU DT entries only for hotplugged CPUs. For boot time or
2800 * coldplugged CPUs DT entries are setup in spapr_build_fdt().
2801 */
2802 if (dev->hotplugged) {
2803 fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr);
2804 }
2805
2806 if (drc) {
2807 sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2808 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, &local_err);
2809 if (local_err) {
2810 g_free(fdt);
2811 error_propagate(errp, local_err);
2812 return;
2813 }
2814 }
2815
2816 if (dev->hotplugged) {
2817 /*
2818 * Send hotplug notification interrupt to the guest only in case
2819 * of hotplugged CPUs.
2820 */
2821 spapr_hotplug_req_add_by_index(drc);
2822 } else {
2823 /*
2824 * Set the right DRC states for cold plugged CPU.
2825 */
2826 if (drc) {
2827 sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2828 drck->set_allocation_state(drc, SPAPR_DR_ALLOCATION_STATE_USABLE);
2829 drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED);
2830 }
2831 }
2832 core_slot->cpu = OBJECT(dev);
2833 }
2834
2835 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2836 Error **errp)
2837 {
2838 MachineState *machine = MACHINE(OBJECT(hotplug_dev));
2839 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev);
2840 Error *local_err = NULL;
2841 CPUCore *cc = CPU_CORE(dev);
2842 char *base_core_type = spapr_get_cpu_core_type(machine->cpu_model);
2843 const char *type = object_get_typename(OBJECT(dev));
2844 CPUArchId *core_slot;
2845 int index;
2846
2847 if (dev->hotplugged && !mc->has_hotpluggable_cpus) {
2848 error_setg(&local_err, "CPU hotplug not supported for this machine");
2849 goto out;
2850 }
2851
2852 if (strcmp(base_core_type, type)) {
2853 error_setg(&local_err, "CPU core type should be %s", base_core_type);
2854 goto out;
2855 }
2856
2857 if (cc->core_id % smp_threads) {
2858 error_setg(&local_err, "invalid core id %d", cc->core_id);
2859 goto out;
2860 }
2861
2862 if (cc->nr_threads != smp_threads) {
2863 error_setg(errp, "invalid nr-threads %d, must be %d",
2864 cc->nr_threads, smp_threads);
2865 return;
2866 }
2867
2868 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
2869 if (!core_slot) {
2870 error_setg(&local_err, "core id %d out of range", cc->core_id);
2871 goto out;
2872 }
2873
2874 if (core_slot->cpu) {
2875 error_setg(&local_err, "core %d already populated", cc->core_id);
2876 goto out;
2877 }
2878
2879 out:
2880 g_free(base_core_type);
2881 error_propagate(errp, local_err);
2882 }
2883
2884 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev,
2885 DeviceState *dev, Error **errp)
2886 {
2887 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine());
2888
2889 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2890 int node;
2891
2892 if (!smc->dr_lmb_enabled) {
2893 error_setg(errp, "Memory hotplug not supported for this machine");
2894 return;
2895 }
2896 node = object_property_get_int(OBJECT(dev), PC_DIMM_NODE_PROP, errp);
2897 if (*errp) {
2898 return;
2899 }
2900 if (node < 0 || node >= MAX_NODES) {
2901 error_setg(errp, "Invaild node %d", node);
2902 return;
2903 }
2904
2905 /*
2906 * Currently PowerPC kernel doesn't allow hot-adding memory to
2907 * memory-less node, but instead will silently add the memory
2908 * to the first node that has some memory. This causes two
2909 * unexpected behaviours for the user.
2910 *
2911 * - Memory gets hotplugged to a different node than what the user
2912 * specified.
2913 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs
2914 * to memory-less node, a reboot will set things accordingly
2915 * and the previously hotplugged memory now ends in the right node.
2916 * This appears as if some memory moved from one node to another.
2917 *
2918 * So until kernel starts supporting memory hotplug to memory-less
2919 * nodes, just prevent such attempts upfront in QEMU.
2920 */
2921 if (nb_numa_nodes && !numa_info[node].node_mem) {
2922 error_setg(errp, "Can't hotplug memory to memory-less node %d",
2923 node);
2924 return;
2925 }
2926
2927 spapr_memory_plug(hotplug_dev, dev, node, errp);
2928 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2929 spapr_core_plug(hotplug_dev, dev, errp);
2930 }
2931 }
2932
2933 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev,
2934 DeviceState *dev, Error **errp)
2935 {
2936 sPAPRMachineState *sms = SPAPR_MACHINE(qdev_get_machine());
2937 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
2938
2939 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2940 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) {
2941 spapr_memory_unplug(hotplug_dev, dev, errp);
2942 } else {
2943 error_setg(errp, "Memory hot unplug not supported for this guest");
2944 }
2945 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2946 if (!mc->has_hotpluggable_cpus) {
2947 error_setg(errp, "CPU hot unplug not supported on this machine");
2948 return;
2949 }
2950 spapr_core_unplug(hotplug_dev, dev, errp);
2951 }
2952 }
2953
2954 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev,
2955 DeviceState *dev, Error **errp)
2956 {
2957 sPAPRMachineState *sms = SPAPR_MACHINE(qdev_get_machine());
2958 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
2959
2960 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2961 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) {
2962 spapr_memory_unplug_request(hotplug_dev, dev, errp);
2963 } else {
2964 /* NOTE: this means there is a window after guest reset, prior to
2965 * CAS negotiation, where unplug requests will fail due to the
2966 * capability not being detected yet. This is a bit different than
2967 * the case with PCI unplug, where the events will be queued and
2968 * eventually handled by the guest after boot
2969 */
2970 error_setg(errp, "Memory hot unplug not supported for this guest");
2971 }
2972 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2973 if (!mc->has_hotpluggable_cpus) {
2974 error_setg(errp, "CPU hot unplug not supported on this machine");
2975 return;
2976 }
2977 spapr_core_unplug_request(hotplug_dev, dev, errp);
2978 }
2979 }
2980
2981 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev,
2982 DeviceState *dev, Error **errp)
2983 {
2984 if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2985 spapr_core_pre_plug(hotplug_dev, dev, errp);
2986 }
2987 }
2988
2989 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine,
2990 DeviceState *dev)
2991 {
2992 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
2993 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2994 return HOTPLUG_HANDLER(machine);
2995 }
2996 return NULL;
2997 }
2998
2999 static unsigned spapr_cpu_index_to_socket_id(unsigned cpu_index)
3000 {
3001 /* Allocate to NUMA nodes on a "socket" basis (not that concept of
3002 * socket means much for the paravirtualized PAPR platform) */
3003 return cpu_index / smp_threads / smp_cores;
3004 }
3005
3006 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine)
3007 {
3008 int i;
3009 int spapr_max_cores = max_cpus / smp_threads;
3010 MachineClass *mc = MACHINE_GET_CLASS(machine);
3011
3012 if (!mc->has_hotpluggable_cpus) {
3013 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads;
3014 }
3015 if (machine->possible_cpus) {
3016 assert(machine->possible_cpus->len == spapr_max_cores);
3017 return machine->possible_cpus;
3018 }
3019
3020 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
3021 sizeof(CPUArchId) * spapr_max_cores);
3022 machine->possible_cpus->len = spapr_max_cores;
3023 for (i = 0; i < machine->possible_cpus->len; i++) {
3024 int core_id = i * smp_threads;
3025
3026 machine->possible_cpus->cpus[i].vcpus_count = smp_threads;
3027 machine->possible_cpus->cpus[i].arch_id = core_id;
3028 machine->possible_cpus->cpus[i].props.has_core_id = true;
3029 machine->possible_cpus->cpus[i].props.core_id = core_id;
3030 /* TODO: add 'has_node/node' here to describe
3031 to which node core belongs */
3032 }
3033 return machine->possible_cpus;
3034 }
3035
3036 static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index,
3037 uint64_t *buid, hwaddr *pio,
3038 hwaddr *mmio32, hwaddr *mmio64,
3039 unsigned n_dma, uint32_t *liobns, Error **errp)
3040 {
3041 /*
3042 * New-style PHB window placement.
3043 *
3044 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window
3045 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO
3046 * windows.
3047 *
3048 * Some guest kernels can't work with MMIO windows above 1<<46
3049 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB
3050 *
3051 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each
3052 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the
3053 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the
3054 * 1TiB 64-bit MMIO windows for each PHB.
3055 */
3056 const uint64_t base_buid = 0x800000020000000ULL;
3057 #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \
3058 SPAPR_PCI_MEM64_WIN_SIZE - 1)
3059 int i;
3060
3061 /* Sanity check natural alignments */
3062 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
3063 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
3064 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0);
3065 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0);
3066 /* Sanity check bounds */
3067 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) >
3068 SPAPR_PCI_MEM32_WIN_SIZE);
3069 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) >
3070 SPAPR_PCI_MEM64_WIN_SIZE);
3071
3072 if (index >= SPAPR_MAX_PHBS) {
3073 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)",
3074 SPAPR_MAX_PHBS - 1);
3075 return;
3076 }
3077
3078 *buid = base_buid + index;
3079 for (i = 0; i < n_dma; ++i) {
3080 liobns[i] = SPAPR_PCI_LIOBN(index, i);
3081 }
3082
3083 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE;
3084 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE;
3085 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE;
3086 }
3087
3088 static ICSState *spapr_ics_get(XICSFabric *dev, int irq)
3089 {
3090 sPAPRMachineState *spapr = SPAPR_MACHINE(dev);
3091
3092 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL;
3093 }
3094
3095 static void spapr_ics_resend(XICSFabric *dev)
3096 {
3097 sPAPRMachineState *spapr = SPAPR_MACHINE(dev);
3098
3099 ics_resend(spapr->ics);
3100 }
3101
3102 static ICPState *spapr_icp_get(XICSFabric *xi, int server)
3103 {
3104 sPAPRMachineState *spapr = SPAPR_MACHINE(xi);
3105
3106 return (server < spapr->nr_servers) ? &spapr->icps[server] : NULL;
3107 }
3108
3109 static void spapr_pic_print_info(InterruptStatsProvider *obj,
3110 Monitor *mon)
3111 {
3112 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
3113 int i;
3114
3115 for (i = 0; i < spapr->nr_servers; i++) {
3116 icp_pic_print_info(&spapr->icps[i], mon);
3117 }
3118
3119 ics_pic_print_info(spapr->ics, mon);
3120 }
3121
3122 static void spapr_machine_class_init(ObjectClass *oc, void *data)
3123 {
3124 MachineClass *mc = MACHINE_CLASS(oc);
3125 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc);
3126 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
3127 NMIClass *nc = NMI_CLASS(oc);
3128 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
3129 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc);
3130 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
3131 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
3132
3133 mc->desc = "pSeries Logical Partition (PAPR compliant)";
3134
3135 /*
3136 * We set up the default / latest behaviour here. The class_init
3137 * functions for the specific versioned machine types can override
3138 * these details for backwards compatibility
3139 */
3140 mc->init = ppc_spapr_init;
3141 mc->reset = ppc_spapr_reset;
3142 mc->block_default_type = IF_SCSI;
3143 mc->max_cpus = 1024;
3144 mc->no_parallel = 1;
3145 mc->default_boot_order = "";
3146 mc->default_ram_size = 512 * M_BYTE;
3147 mc->kvm_type = spapr_kvm_type;
3148 mc->has_dynamic_sysbus = true;
3149 mc->pci_allow_0_address = true;
3150 mc->get_hotplug_handler = spapr_get_hotplug_handler;
3151 hc->pre_plug = spapr_machine_device_pre_plug;
3152 hc->plug = spapr_machine_device_plug;
3153 hc->unplug = spapr_machine_device_unplug;
3154 mc->cpu_index_to_socket_id = spapr_cpu_index_to_socket_id;
3155 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids;
3156 hc->unplug_request = spapr_machine_device_unplug_request;
3157
3158 smc->dr_lmb_enabled = true;
3159 smc->tcg_default_cpu = "POWER8";
3160 mc->has_hotpluggable_cpus = true;
3161 fwc->get_dev_path = spapr_get_fw_dev_path;
3162 nc->nmi_monitor_handler = spapr_nmi;
3163 smc->phb_placement = spapr_phb_placement;
3164 vhc->hypercall = emulate_spapr_hypercall;
3165 vhc->hpt_mask = spapr_hpt_mask;
3166 vhc->map_hptes = spapr_map_hptes;
3167 vhc->unmap_hptes = spapr_unmap_hptes;
3168 vhc->store_hpte = spapr_store_hpte;
3169 vhc->get_patbe = spapr_get_patbe;
3170 xic->ics_get = spapr_ics_get;
3171 xic->ics_resend = spapr_ics_resend;
3172 xic->icp_get = spapr_icp_get;
3173 ispc->print_info = spapr_pic_print_info;
3174 /* Force NUMA node memory size to be a multiple of
3175 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity
3176 * in which LMBs are represented and hot-added
3177 */
3178 mc->numa_mem_align_shift = 28;
3179 }
3180
3181 static const TypeInfo spapr_machine_info = {
3182 .name = TYPE_SPAPR_MACHINE,
3183 .parent = TYPE_MACHINE,
3184 .abstract = true,
3185 .instance_size = sizeof(sPAPRMachineState),
3186 .instance_init = spapr_machine_initfn,
3187 .instance_finalize = spapr_machine_finalizefn,
3188 .class_size = sizeof(sPAPRMachineClass),
3189 .class_init = spapr_machine_class_init,
3190 .interfaces = (InterfaceInfo[]) {
3191 { TYPE_FW_PATH_PROVIDER },
3192 { TYPE_NMI },
3193 { TYPE_HOTPLUG_HANDLER },
3194 { TYPE_PPC_VIRTUAL_HYPERVISOR },
3195 { TYPE_XICS_FABRIC },
3196 { TYPE_INTERRUPT_STATS_PROVIDER },
3197 { }
3198 },
3199 };
3200
3201 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
3202 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
3203 void *data) \
3204 { \
3205 MachineClass *mc = MACHINE_CLASS(oc); \
3206 spapr_machine_##suffix##_class_options(mc); \
3207 if (latest) { \
3208 mc->alias = "pseries"; \
3209 mc->is_default = 1; \
3210 } \
3211 } \
3212 static void spapr_machine_##suffix##_instance_init(Object *obj) \
3213 { \
3214 MachineState *machine = MACHINE(obj); \
3215 spapr_machine_##suffix##_instance_options(machine); \
3216 } \
3217 static const TypeInfo spapr_machine_##suffix##_info = { \
3218 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
3219 .parent = TYPE_SPAPR_MACHINE, \
3220 .class_init = spapr_machine_##suffix##_class_init, \
3221 .instance_init = spapr_machine_##suffix##_instance_init, \
3222 }; \
3223 static void spapr_machine_register_##suffix(void) \
3224 { \
3225 type_register(&spapr_machine_##suffix##_info); \
3226 } \
3227 type_init(spapr_machine_register_##suffix)
3228
3229 /*
3230 * pseries-2.10
3231 */
3232 static void spapr_machine_2_10_instance_options(MachineState *machine)
3233 {
3234 }
3235
3236 static void spapr_machine_2_10_class_options(MachineClass *mc)
3237 {
3238 /* Defaults for the latest behaviour inherited from the base class */
3239 }
3240
3241 DEFINE_SPAPR_MACHINE(2_10, "2.10", true);
3242
3243 /*
3244 * pseries-2.9
3245 */
3246 #define SPAPR_COMPAT_2_9 \
3247 HW_COMPAT_2_9
3248
3249 static void spapr_machine_2_9_instance_options(MachineState *machine)
3250 {
3251 spapr_machine_2_10_instance_options(machine);
3252 }
3253
3254 static void spapr_machine_2_9_class_options(MachineClass *mc)
3255 {
3256 spapr_machine_2_10_class_options(mc);
3257 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_9);
3258 }
3259
3260 DEFINE_SPAPR_MACHINE(2_9, "2.9", false);
3261
3262 /*
3263 * pseries-2.8
3264 */
3265 #define SPAPR_COMPAT_2_8 \
3266 HW_COMPAT_2_8 \
3267 { \
3268 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
3269 .property = "pcie-extended-configuration-space", \
3270 .value = "off", \
3271 },
3272
3273 static void spapr_machine_2_8_instance_options(MachineState *machine)
3274 {
3275 spapr_machine_2_9_instance_options(machine);
3276 }
3277
3278 static void spapr_machine_2_8_class_options(MachineClass *mc)
3279 {
3280 spapr_machine_2_9_class_options(mc);
3281 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8);
3282 mc->numa_mem_align_shift = 23;
3283 }
3284
3285 DEFINE_SPAPR_MACHINE(2_8, "2.8", false);
3286
3287 /*
3288 * pseries-2.7
3289 */
3290 #define SPAPR_COMPAT_2_7 \
3291 HW_COMPAT_2_7 \
3292 { \
3293 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
3294 .property = "mem_win_size", \
3295 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\
3296 }, \
3297 { \
3298 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
3299 .property = "mem64_win_size", \
3300 .value = "0", \
3301 }, \
3302 { \
3303 .driver = TYPE_POWERPC_CPU, \
3304 .property = "pre-2.8-migration", \
3305 .value = "on", \
3306 }, \
3307 { \
3308 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
3309 .property = "pre-2.8-migration", \
3310 .value = "on", \
3311 },
3312