pseries: Add pseries-2.10 machine type
[qemu.git] / hw / ppc / spapr.c
1 /*
2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
3 *
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 *
26 */
27 #include "qemu/osdep.h"
28 #include "qapi/error.h"
29 #include "sysemu/sysemu.h"
30 #include "sysemu/numa.h"
31 #include "hw/hw.h"
32 #include "qemu/log.h"
33 #include "hw/fw-path-provider.h"
34 #include "elf.h"
35 #include "net/net.h"
36 #include "sysemu/device_tree.h"
37 #include "sysemu/block-backend.h"
38 #include "sysemu/cpus.h"
39 #include "sysemu/hw_accel.h"
40 #include "kvm_ppc.h"
41 #include "migration/migration.h"
42 #include "mmu-hash64.h"
43 #include "qom/cpu.h"
44
45 #include "hw/boards.h"
46 #include "hw/ppc/ppc.h"
47 #include "hw/loader.h"
48
49 #include "hw/ppc/fdt.h"
50 #include "hw/ppc/spapr.h"
51 #include "hw/ppc/spapr_vio.h"
52 #include "hw/pci-host/spapr.h"
53 #include "hw/ppc/xics.h"
54 #include "hw/pci/msi.h"
55
56 #include "hw/pci/pci.h"
57 #include "hw/scsi/scsi.h"
58 #include "hw/virtio/virtio-scsi.h"
59
60 #include "exec/address-spaces.h"
61 #include "hw/usb.h"
62 #include "qemu/config-file.h"
63 #include "qemu/error-report.h"
64 #include "trace.h"
65 #include "hw/nmi.h"
66 #include "hw/intc/intc.h"
67
68 #include "hw/compat.h"
69 #include "qemu/cutils.h"
70 #include "hw/ppc/spapr_cpu_core.h"
71 #include "qmp-commands.h"
72
73 #include <libfdt.h>
74
75 /* SLOF memory layout:
76 *
77 * SLOF raw image loaded at 0, copies its romfs right below the flat
78 * device-tree, then position SLOF itself 31M below that
79 *
80 * So we set FW_OVERHEAD to 40MB which should account for all of that
81 * and more
82 *
83 * We load our kernel at 4M, leaving space for SLOF initial image
84 */
85 #define FDT_MAX_SIZE 0x100000
86 #define RTAS_MAX_SIZE 0x10000
87 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */
88 #define FW_MAX_SIZE 0x400000
89 #define FW_FILE_NAME "slof.bin"
90 #define FW_OVERHEAD 0x2800000
91 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
92
93 #define MIN_RMA_SLOF 128UL
94
95 #define PHANDLE_XICP 0x00001111
96
97 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift))
98
99 static int try_create_xics(sPAPRMachineState *spapr, const char *type_ics,
100 const char *type_icp, int nr_servers,
101 int nr_irqs, Error **errp)
102 {
103 XICSFabric *xi = XICS_FABRIC(spapr);
104 Error *err = NULL, *local_err = NULL;
105 ICSState *ics = NULL;
106 int i;
107
108 ics = ICS_SIMPLE(object_new(type_ics));
109 object_property_add_child(OBJECT(spapr), "ics", OBJECT(ics), NULL);
110 object_property_set_int(OBJECT(ics), nr_irqs, "nr-irqs", &err);
111 object_property_add_const_link(OBJECT(ics), "xics", OBJECT(xi), NULL);
112 object_property_set_bool(OBJECT(ics), true, "realized", &local_err);
113 error_propagate(&err, local_err);
114 if (err) {
115 goto error;
116 }
117
118 spapr->icps = g_malloc0(nr_servers * sizeof(ICPState));
119 spapr->nr_servers = nr_servers;
120
121 for (i = 0; i < nr_servers; i++) {
122 ICPState *icp = &spapr->icps[i];
123
124 object_initialize(icp, sizeof(*icp), type_icp);
125 object_property_add_child(OBJECT(spapr), "icp[*]", OBJECT(icp), NULL);
126 object_property_add_const_link(OBJECT(icp), "xics", OBJECT(xi), NULL);
127 object_property_set_bool(OBJECT(icp), true, "realized", &err);
128 if (err) {
129 goto error;
130 }
131 object_unref(OBJECT(icp));
132 }
133
134 spapr->ics = ics;
135 return 0;
136
137 error:
138 error_propagate(errp, err);
139 if (ics) {
140 object_unparent(OBJECT(ics));
141 }
142 return -1;
143 }
144
145 static int xics_system_init(MachineState *machine,
146 int nr_servers, int nr_irqs, Error **errp)
147 {
148 int rc = -1;
149
150 if (kvm_enabled()) {
151 Error *err = NULL;
152
153 if (machine_kernel_irqchip_allowed(machine) &&
154 !xics_kvm_init(SPAPR_MACHINE(machine), errp)) {
155 rc = try_create_xics(SPAPR_MACHINE(machine), TYPE_ICS_KVM,
156 TYPE_KVM_ICP, nr_servers, nr_irqs, &err);
157 }
158 if (machine_kernel_irqchip_required(machine) && rc < 0) {
159 error_reportf_err(err,
160 "kernel_irqchip requested but unavailable: ");
161 } else {
162 error_free(err);
163 }
164 }
165
166 if (rc < 0) {
167 xics_spapr_init(SPAPR_MACHINE(machine), errp);
168 rc = try_create_xics(SPAPR_MACHINE(machine), TYPE_ICS_SIMPLE,
169 TYPE_ICP, nr_servers, nr_irqs, errp);
170 }
171
172 return rc;
173 }
174
175 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
176 int smt_threads)
177 {
178 int i, ret = 0;
179 uint32_t servers_prop[smt_threads];
180 uint32_t gservers_prop[smt_threads * 2];
181 int index = ppc_get_vcpu_dt_id(cpu);
182
183 if (cpu->compat_pvr) {
184 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr);
185 if (ret < 0) {
186 return ret;
187 }
188 }
189
190 /* Build interrupt servers and gservers properties */
191 for (i = 0; i < smt_threads; i++) {
192 servers_prop[i] = cpu_to_be32(index + i);
193 /* Hack, direct the group queues back to cpu 0 */
194 gservers_prop[i*2] = cpu_to_be32(index + i);
195 gservers_prop[i*2 + 1] = 0;
196 }
197 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
198 servers_prop, sizeof(servers_prop));
199 if (ret < 0) {
200 return ret;
201 }
202 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s",
203 gservers_prop, sizeof(gservers_prop));
204
205 return ret;
206 }
207
208 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, CPUState *cs)
209 {
210 int ret = 0;
211 PowerPCCPU *cpu = POWERPC_CPU(cs);
212 int index = ppc_get_vcpu_dt_id(cpu);
213 uint32_t associativity[] = {cpu_to_be32(0x5),
214 cpu_to_be32(0x0),
215 cpu_to_be32(0x0),
216 cpu_to_be32(0x0),
217 cpu_to_be32(cs->numa_node),
218 cpu_to_be32(index)};
219
220 /* Advertise NUMA via ibm,associativity */
221 if (nb_numa_nodes > 1) {
222 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity,
223 sizeof(associativity));
224 }
225
226 return ret;
227 }
228
229 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr)
230 {
231 int ret = 0, offset, cpus_offset;
232 CPUState *cs;
233 char cpu_model[32];
234 int smt = kvmppc_smt_threads();
235 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
236
237 CPU_FOREACH(cs) {
238 PowerPCCPU *cpu = POWERPC_CPU(cs);
239 DeviceClass *dc = DEVICE_GET_CLASS(cs);
240 int index = ppc_get_vcpu_dt_id(cpu);
241 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu));
242
243 if ((index % smt) != 0) {
244 continue;
245 }
246
247 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index);
248
249 cpus_offset = fdt_path_offset(fdt, "/cpus");
250 if (cpus_offset < 0) {
251 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"),
252 "cpus");
253 if (cpus_offset < 0) {
254 return cpus_offset;
255 }
256 }
257 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model);
258 if (offset < 0) {
259 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model);
260 if (offset < 0) {
261 return offset;
262 }
263 }
264
265 ret = fdt_setprop(fdt, offset, "ibm,pft-size",
266 pft_size_prop, sizeof(pft_size_prop));
267 if (ret < 0) {
268 return ret;
269 }
270
271 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cs);
272 if (ret < 0) {
273 return ret;
274 }
275
276 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt);
277 if (ret < 0) {
278 return ret;
279 }
280 }
281 return ret;
282 }
283
284 static hwaddr spapr_node0_size(void)
285 {
286 MachineState *machine = MACHINE(qdev_get_machine());
287
288 if (nb_numa_nodes) {
289 int i;
290 for (i = 0; i < nb_numa_nodes; ++i) {
291 if (numa_info[i].node_mem) {
292 return MIN(pow2floor(numa_info[i].node_mem),
293 machine->ram_size);
294 }
295 }
296 }
297 return machine->ram_size;
298 }
299
300 static void add_str(GString *s, const gchar *s1)
301 {
302 g_string_append_len(s, s1, strlen(s1) + 1);
303 }
304
305 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start,
306 hwaddr size)
307 {
308 uint32_t associativity[] = {
309 cpu_to_be32(0x4), /* length */
310 cpu_to_be32(0x0), cpu_to_be32(0x0),
311 cpu_to_be32(0x0), cpu_to_be32(nodeid)
312 };
313 char mem_name[32];
314 uint64_t mem_reg_property[2];
315 int off;
316
317 mem_reg_property[0] = cpu_to_be64(start);
318 mem_reg_property[1] = cpu_to_be64(size);
319
320 sprintf(mem_name, "memory@" TARGET_FMT_lx, start);
321 off = fdt_add_subnode(fdt, 0, mem_name);
322 _FDT(off);
323 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
324 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
325 sizeof(mem_reg_property))));
326 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
327 sizeof(associativity))));
328 return off;
329 }
330
331 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt)
332 {
333 MachineState *machine = MACHINE(spapr);
334 hwaddr mem_start, node_size;
335 int i, nb_nodes = nb_numa_nodes;
336 NodeInfo *nodes = numa_info;
337 NodeInfo ramnode;
338
339 /* No NUMA nodes, assume there is just one node with whole RAM */
340 if (!nb_numa_nodes) {
341 nb_nodes = 1;
342 ramnode.node_mem = machine->ram_size;
343 nodes = &ramnode;
344 }
345
346 for (i = 0, mem_start = 0; i < nb_nodes; ++i) {
347 if (!nodes[i].node_mem) {
348 continue;
349 }
350 if (mem_start >= machine->ram_size) {
351 node_size = 0;
352 } else {
353 node_size = nodes[i].node_mem;
354 if (node_size > machine->ram_size - mem_start) {
355 node_size = machine->ram_size - mem_start;
356 }
357 }
358 if (!mem_start) {
359 /* ppc_spapr_init() checks for rma_size <= node0_size already */
360 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size);
361 mem_start += spapr->rma_size;
362 node_size -= spapr->rma_size;
363 }
364 for ( ; node_size; ) {
365 hwaddr sizetmp = pow2floor(node_size);
366
367 /* mem_start != 0 here */
368 if (ctzl(mem_start) < ctzl(sizetmp)) {
369 sizetmp = 1ULL << ctzl(mem_start);
370 }
371
372 spapr_populate_memory_node(fdt, i, mem_start, sizetmp);
373 node_size -= sizetmp;
374 mem_start += sizetmp;
375 }
376 }
377
378 return 0;
379 }
380
381 /* Populate the "ibm,pa-features" property */
382 static void spapr_populate_pa_features(CPUPPCState *env, void *fdt, int offset)
383 {
384 uint8_t pa_features_206[] = { 6, 0,
385 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
386 uint8_t pa_features_207[] = { 24, 0,
387 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
388 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
389 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
390 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
391 /* Currently we don't advertise any of the "new" ISAv3.00 functionality */
392 uint8_t pa_features_300[] = { 64, 0,
393 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */
394 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
395 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
396 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
397 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 24 - 29 */
398 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 30 - 35 */
399 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 36 - 41 */
400 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 42 - 47 */
401 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 48 - 53 */
402 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 54 - 59 */
403 0x00, 0x00, 0x00, 0x00 }; /* 60 - 63 */
404
405 uint8_t *pa_features;
406 size_t pa_size;
407
408 switch (POWERPC_MMU_VER(env->mmu_model)) {
409 case POWERPC_MMU_VER_2_06:
410 pa_features = pa_features_206;
411 pa_size = sizeof(pa_features_206);
412 break;
413 case POWERPC_MMU_VER_2_07:
414 pa_features = pa_features_207;
415 pa_size = sizeof(pa_features_207);
416 break;
417 case POWERPC_MMU_VER_3_00:
418 pa_features = pa_features_300;
419 pa_size = sizeof(pa_features_300);
420 break;
421 default:
422 return;
423 }
424
425 if (env->ci_large_pages) {
426 /*
427 * Note: we keep CI large pages off by default because a 64K capable
428 * guest provisioned with large pages might otherwise try to map a qemu
429 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
430 * even if that qemu runs on a 4k host.
431 * We dd this bit back here if we are confident this is not an issue
432 */
433 pa_features[3] |= 0x20;
434 }
435 if (kvmppc_has_cap_htm() && pa_size > 24) {
436 pa_features[24] |= 0x80; /* Transactional memory support */
437 }
438
439 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size)));
440 }
441
442 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
443 sPAPRMachineState *spapr)
444 {
445 PowerPCCPU *cpu = POWERPC_CPU(cs);
446 CPUPPCState *env = &cpu->env;
447 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
448 int index = ppc_get_vcpu_dt_id(cpu);
449 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
450 0xffffffff, 0xffffffff};
451 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq()
452 : SPAPR_TIMEBASE_FREQ;
453 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
454 uint32_t page_sizes_prop[64];
455 size_t page_sizes_prop_size;
456 uint32_t vcpus_per_socket = smp_threads * smp_cores;
457 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
458 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu));
459 sPAPRDRConnector *drc;
460 sPAPRDRConnectorClass *drck;
461 int drc_index;
462
463 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index);
464 if (drc) {
465 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
466 drc_index = drck->get_index(drc);
467 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)));
468 }
469
470 _FDT((fdt_setprop_cell(fdt, offset, "reg", index)));
471 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
472
473 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
474 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
475 env->dcache_line_size)));
476 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
477 env->dcache_line_size)));
478 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
479 env->icache_line_size)));
480 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
481 env->icache_line_size)));
482
483 if (pcc->l1_dcache_size) {
484 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
485 pcc->l1_dcache_size)));
486 } else {
487 error_report("Warning: Unknown L1 dcache size for cpu");
488 }
489 if (pcc->l1_icache_size) {
490 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
491 pcc->l1_icache_size)));
492 } else {
493 error_report("Warning: Unknown L1 icache size for cpu");
494 }
495
496 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
497 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
498 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr)));
499 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr)));
500 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
501 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
502
503 if (env->spr_cb[SPR_PURR].oea_read) {
504 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
505 }
506
507 if (env->mmu_model & POWERPC_MMU_1TSEG) {
508 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
509 segs, sizeof(segs))));
510 }
511
512 /* Advertise VMX/VSX (vector extensions) if available
513 * 0 / no property == no vector extensions
514 * 1 == VMX / Altivec available
515 * 2 == VSX available */
516 if (env->insns_flags & PPC_ALTIVEC) {
517 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
518
519 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
520 }
521
522 /* Advertise DFP (Decimal Floating Point) if available
523 * 0 / no property == no DFP
524 * 1 == DFP available */
525 if (env->insns_flags2 & PPC2_DFP) {
526 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
527 }
528
529 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop,
530 sizeof(page_sizes_prop));
531 if (page_sizes_prop_size) {
532 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
533 page_sizes_prop, page_sizes_prop_size)));
534 }
535
536 spapr_populate_pa_features(env, fdt, offset);
537
538 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
539 cs->cpu_index / vcpus_per_socket)));
540
541 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size",
542 pft_size_prop, sizeof(pft_size_prop))));
543
544 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cs));
545
546 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt));
547 }
548
549 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr)
550 {
551 CPUState *cs;
552 int cpus_offset;
553 char *nodename;
554 int smt = kvmppc_smt_threads();
555
556 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
557 _FDT(cpus_offset);
558 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
559 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
560
561 /*
562 * We walk the CPUs in reverse order to ensure that CPU DT nodes
563 * created by fdt_add_subnode() end up in the right order in FDT
564 * for the guest kernel the enumerate the CPUs correctly.
565 */
566 CPU_FOREACH_REVERSE(cs) {
567 PowerPCCPU *cpu = POWERPC_CPU(cs);
568 int index = ppc_get_vcpu_dt_id(cpu);
569 DeviceClass *dc = DEVICE_GET_CLASS(cs);
570 int offset;
571
572 if ((index % smt) != 0) {
573 continue;
574 }
575
576 nodename = g_strdup_printf("%s@%x", dc->fw_name, index);
577 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
578 g_free(nodename);
579 _FDT(offset);
580 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
581 }
582
583 }
584
585 /*
586 * Adds ibm,dynamic-reconfiguration-memory node.
587 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
588 * of this device tree node.
589 */
590 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt)
591 {
592 MachineState *machine = MACHINE(spapr);
593 int ret, i, offset;
594 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
595 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)};
596 uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size;
597 uint32_t nr_lmbs = (spapr->hotplug_memory.base +
598 memory_region_size(&spapr->hotplug_memory.mr)) /
599 lmb_size;
600 uint32_t *int_buf, *cur_index, buf_len;
601 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1;
602
603 /*
604 * Don't create the node if there is no hotpluggable memory
605 */
606 if (machine->ram_size == machine->maxram_size) {
607 return 0;
608 }
609
610 /*
611 * Allocate enough buffer size to fit in ibm,dynamic-memory
612 * or ibm,associativity-lookup-arrays
613 */
614 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2)
615 * sizeof(uint32_t);
616 cur_index = int_buf = g_malloc0(buf_len);
617
618 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory");
619
620 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size,
621 sizeof(prop_lmb_size));
622 if (ret < 0) {
623 goto out;
624 }
625
626 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff);
627 if (ret < 0) {
628 goto out;
629 }
630
631 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0);
632 if (ret < 0) {
633 goto out;
634 }
635
636 /* ibm,dynamic-memory */
637 int_buf[0] = cpu_to_be32(nr_lmbs);
638 cur_index++;
639 for (i = 0; i < nr_lmbs; i++) {
640 uint64_t addr = i * lmb_size;
641 uint32_t *dynamic_memory = cur_index;
642
643 if (i >= hotplug_lmb_start) {
644 sPAPRDRConnector *drc;
645 sPAPRDRConnectorClass *drck;
646
647 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, i);
648 g_assert(drc);
649 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
650
651 dynamic_memory[0] = cpu_to_be32(addr >> 32);
652 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
653 dynamic_memory[2] = cpu_to_be32(drck->get_index(drc));
654 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
655 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL));
656 if (memory_region_present(get_system_memory(), addr)) {
657 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED);
658 } else {
659 dynamic_memory[5] = cpu_to_be32(0);
660 }
661 } else {
662 /*
663 * LMB information for RMA, boot time RAM and gap b/n RAM and
664 * hotplug memory region -- all these are marked as reserved
665 * and as having no valid DRC.
666 */
667 dynamic_memory[0] = cpu_to_be32(addr >> 32);
668 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
669 dynamic_memory[2] = cpu_to_be32(0);
670 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
671 dynamic_memory[4] = cpu_to_be32(-1);
672 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED |
673 SPAPR_LMB_FLAGS_DRC_INVALID);
674 }
675
676 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE;
677 }
678 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len);
679 if (ret < 0) {
680 goto out;
681 }
682
683 /* ibm,associativity-lookup-arrays */
684 cur_index = int_buf;
685 int_buf[0] = cpu_to_be32(nr_nodes);
686 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */
687 cur_index += 2;
688 for (i = 0; i < nr_nodes; i++) {
689 uint32_t associativity[] = {
690 cpu_to_be32(0x0),
691 cpu_to_be32(0x0),
692 cpu_to_be32(0x0),
693 cpu_to_be32(i)
694 };
695 memcpy(cur_index, associativity, sizeof(associativity));
696 cur_index += 4;
697 }
698 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf,
699 (cur_index - int_buf) * sizeof(uint32_t));
700 out:
701 g_free(int_buf);
702 return ret;
703 }
704
705 static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt,
706 sPAPROptionVector *ov5_updates)
707 {
708 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
709 int ret = 0, offset;
710
711 /* Generate ibm,dynamic-reconfiguration-memory node if required */
712 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) {
713 g_assert(smc->dr_lmb_enabled);
714 ret = spapr_populate_drconf_memory(spapr, fdt);
715 if (ret) {
716 goto out;
717 }
718 }
719
720 offset = fdt_path_offset(fdt, "/chosen");
721 if (offset < 0) {
722 offset = fdt_add_subnode(fdt, 0, "chosen");
723 if (offset < 0) {
724 return offset;
725 }
726 }
727 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas,
728 "ibm,architecture-vec-5");
729
730 out:
731 return ret;
732 }
733
734 int spapr_h_cas_compose_response(sPAPRMachineState *spapr,
735 target_ulong addr, target_ulong size,
736 sPAPROptionVector *ov5_updates)
737 {
738 void *fdt, *fdt_skel;
739 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 };
740
741 size -= sizeof(hdr);
742
743 /* Create sceleton */
744 fdt_skel = g_malloc0(size);
745 _FDT((fdt_create(fdt_skel, size)));
746 _FDT((fdt_begin_node(fdt_skel, "")));
747 _FDT((fdt_end_node(fdt_skel)));
748 _FDT((fdt_finish(fdt_skel)));
749 fdt = g_malloc0(size);
750 _FDT((fdt_open_into(fdt_skel, fdt, size)));
751 g_free(fdt_skel);
752
753 /* Fixup cpu nodes */
754 _FDT((spapr_fixup_cpu_dt(fdt, spapr)));
755
756 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) {
757 return -1;
758 }
759
760 /* Pack resulting tree */
761 _FDT((fdt_pack(fdt)));
762
763 if (fdt_totalsize(fdt) + sizeof(hdr) > size) {
764 trace_spapr_cas_failed(size);
765 return -1;
766 }
767
768 cpu_physical_memory_write(addr, &hdr, sizeof(hdr));
769 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt));
770 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr));
771 g_free(fdt);
772
773 return 0;
774 }
775
776 static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt)
777 {
778 int rtas;
779 GString *hypertas = g_string_sized_new(256);
780 GString *qemu_hypertas = g_string_sized_new(256);
781 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) };
782 uint64_t max_hotplug_addr = spapr->hotplug_memory.base +
783 memory_region_size(&spapr->hotplug_memory.mr);
784 uint32_t lrdr_capacity[] = {
785 cpu_to_be32(max_hotplug_addr >> 32),
786 cpu_to_be32(max_hotplug_addr & 0xffffffff),
787 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE),
788 cpu_to_be32(max_cpus / smp_threads),
789 };
790
791 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas"));
792
793 /* hypertas */
794 add_str(hypertas, "hcall-pft");
795 add_str(hypertas, "hcall-term");
796 add_str(hypertas, "hcall-dabr");
797 add_str(hypertas, "hcall-interrupt");
798 add_str(hypertas, "hcall-tce");
799 add_str(hypertas, "hcall-vio");
800 add_str(hypertas, "hcall-splpar");
801 add_str(hypertas, "hcall-bulk");
802 add_str(hypertas, "hcall-set-mode");
803 add_str(hypertas, "hcall-sprg0");
804 add_str(hypertas, "hcall-copy");
805 add_str(hypertas, "hcall-debug");
806 add_str(qemu_hypertas, "hcall-memop1");
807
808 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
809 add_str(hypertas, "hcall-multi-tce");
810 }
811 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions",
812 hypertas->str, hypertas->len));
813 g_string_free(hypertas, TRUE);
814 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions",
815 qemu_hypertas->str, qemu_hypertas->len));
816 g_string_free(qemu_hypertas, TRUE);
817
818 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points",
819 refpoints, sizeof(refpoints)));
820
821 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max",
822 RTAS_ERROR_LOG_MAX));
823 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate",
824 RTAS_EVENT_SCAN_RATE));
825
826 if (msi_nonbroken) {
827 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0));
828 }
829
830 /*
831 * According to PAPR, rtas ibm,os-term does not guarantee a return
832 * back to the guest cpu.
833 *
834 * While an additional ibm,extended-os-term property indicates
835 * that rtas call return will always occur. Set this property.
836 */
837 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0));
838
839 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity",
840 lrdr_capacity, sizeof(lrdr_capacity)));
841
842 spapr_dt_rtas_tokens(fdt, rtas);
843 }
844
845 static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt)
846 {
847 MachineState *machine = MACHINE(spapr);
848 int chosen;
849 const char *boot_device = machine->boot_order;
850 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus);
851 size_t cb = 0;
852 char *bootlist = get_boot_devices_list(&cb, true);
853
854 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen"));
855
856 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline));
857 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start",
858 spapr->initrd_base));
859 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end",
860 spapr->initrd_base + spapr->initrd_size));
861
862 if (spapr->kernel_size) {
863 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR),
864 cpu_to_be64(spapr->kernel_size) };
865
866 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel",
867 &kprop, sizeof(kprop)));
868 if (spapr->kernel_le) {
869 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0));
870 }
871 }
872 if (boot_menu) {
873 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu)));
874 }
875 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width));
876 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height));
877 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth));
878
879 if (cb && bootlist) {
880 int i;
881
882 for (i = 0; i < cb; i++) {
883 if (bootlist[i] == '\n') {
884 bootlist[i] = ' ';
885 }
886 }
887 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist));
888 }
889
890 if (boot_device && strlen(boot_device)) {
891 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device));
892 }
893
894 if (!spapr->has_graphics && stdout_path) {
895 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path));
896 }
897
898 g_free(stdout_path);
899 g_free(bootlist);
900 }
901
902 static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt)
903 {
904 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR
905 * KVM to work under pHyp with some guest co-operation */
906 int hypervisor;
907 uint8_t hypercall[16];
908
909 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor"));
910 /* indicate KVM hypercall interface */
911 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm"));
912 if (kvmppc_has_cap_fixup_hcalls()) {
913 /*
914 * Older KVM versions with older guest kernels were broken
915 * with the magic page, don't allow the guest to map it.
916 */
917 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall,
918 sizeof(hypercall))) {
919 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions",
920 hypercall, sizeof(hypercall)));
921 }
922 }
923 }
924
925 static void *spapr_build_fdt(sPAPRMachineState *spapr,
926 hwaddr rtas_addr,
927 hwaddr rtas_size)
928 {
929 MachineState *machine = MACHINE(qdev_get_machine());
930 MachineClass *mc = MACHINE_GET_CLASS(machine);
931 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
932 int ret;
933 void *fdt;
934 sPAPRPHBState *phb;
935 char *buf;
936
937 fdt = g_malloc0(FDT_MAX_SIZE);
938 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
939
940 /* Root node */
941 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp"));
942 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)"));
943 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries"));
944
945 /*
946 * Add info to guest to indentify which host is it being run on
947 * and what is the uuid of the guest
948 */
949 if (kvmppc_get_host_model(&buf)) {
950 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf));
951 g_free(buf);
952 }
953 if (kvmppc_get_host_serial(&buf)) {
954 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf));
955 g_free(buf);
956 }
957
958 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
959
960 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf));
961 if (qemu_uuid_set) {
962 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf));
963 }
964 g_free(buf);
965
966 if (qemu_get_vm_name()) {
967 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name",
968 qemu_get_vm_name()));
969 }
970
971 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2));
972 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2));
973
974 /* /interrupt controller */
975 spapr_dt_xics(spapr->nr_servers, fdt, PHANDLE_XICP);
976
977 ret = spapr_populate_memory(spapr, fdt);
978 if (ret < 0) {
979 error_report("couldn't setup memory nodes in fdt");
980 exit(1);
981 }
982
983 /* /vdevice */
984 spapr_dt_vdevice(spapr->vio_bus, fdt);
985
986 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) {
987 ret = spapr_rng_populate_dt(fdt);
988 if (ret < 0) {
989 error_report("could not set up rng device in the fdt");
990 exit(1);
991 }
992 }
993
994 QLIST_FOREACH(phb, &spapr->phbs, list) {
995 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt);
996 if (ret < 0) {
997 error_report("couldn't setup PCI devices in fdt");
998 exit(1);
999 }
1000 }
1001
1002 /* cpus */
1003 spapr_populate_cpus_dt_node(fdt, spapr);
1004
1005 if (smc->dr_lmb_enabled) {
1006 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB));
1007 }
1008
1009 if (mc->has_hotpluggable_cpus) {
1010 int offset = fdt_path_offset(fdt, "/cpus");
1011 ret = spapr_drc_populate_dt(fdt, offset, NULL,
1012 SPAPR_DR_CONNECTOR_TYPE_CPU);
1013 if (ret < 0) {
1014 error_report("Couldn't set up CPU DR device tree properties");
1015 exit(1);
1016 }
1017 }
1018
1019 /* /event-sources */
1020 spapr_dt_events(spapr, fdt);
1021
1022 /* /rtas */
1023 spapr_dt_rtas(spapr, fdt);
1024
1025 /* /chosen */
1026 spapr_dt_chosen(spapr, fdt);
1027
1028 /* /hypervisor */
1029 if (kvm_enabled()) {
1030 spapr_dt_hypervisor(spapr, fdt);
1031 }
1032
1033 /* Build memory reserve map */
1034 if (spapr->kernel_size) {
1035 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size)));
1036 }
1037 if (spapr->initrd_size) {
1038 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size)));
1039 }
1040
1041 /* ibm,client-architecture-support updates */
1042 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas);
1043 if (ret < 0) {
1044 error_report("couldn't setup CAS properties fdt");
1045 exit(1);
1046 }
1047
1048 return fdt;
1049 }
1050
1051 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
1052 {
1053 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
1054 }
1055
1056 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp,
1057 PowerPCCPU *cpu)
1058 {
1059 CPUPPCState *env = &cpu->env;
1060
1061 /* The TCG path should also be holding the BQL at this point */
1062 g_assert(qemu_mutex_iothread_locked());
1063
1064 if (msr_pr) {
1065 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1066 env->gpr[3] = H_PRIVILEGE;
1067 } else {
1068 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]);
1069 }
1070 }
1071
1072 static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp)
1073 {
1074 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1075
1076 return spapr->patb_entry;
1077 }
1078
1079 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1080 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1081 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1082 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1083 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1084
1085 /*
1086 * Get the fd to access the kernel htab, re-opening it if necessary
1087 */
1088 static int get_htab_fd(sPAPRMachineState *spapr)
1089 {
1090 if (spapr->htab_fd >= 0) {
1091 return spapr->htab_fd;
1092 }
1093
1094 spapr->htab_fd = kvmppc_get_htab_fd(false);
1095 if (spapr->htab_fd < 0) {
1096 error_report("Unable to open fd for reading hash table from KVM: %s",
1097 strerror(errno));
1098 }
1099
1100 return spapr->htab_fd;
1101 }
1102
1103 static void close_htab_fd(sPAPRMachineState *spapr)
1104 {
1105 if (spapr->htab_fd >= 0) {
1106 close(spapr->htab_fd);
1107 }
1108 spapr->htab_fd = -1;
1109 }
1110
1111 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp)
1112 {
1113 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1114
1115 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1;
1116 }
1117
1118 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp,
1119 hwaddr ptex, int n)
1120 {
1121 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1122 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64;
1123
1124 if (!spapr->htab) {
1125 /*
1126 * HTAB is controlled by KVM. Fetch into temporary buffer
1127 */
1128 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64);
1129 kvmppc_read_hptes(hptes, ptex, n);
1130 return hptes;
1131 }
1132
1133 /*
1134 * HTAB is controlled by QEMU. Just point to the internally
1135 * accessible PTEG.
1136 */
1137 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset);
1138 }
1139
1140 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp,
1141 const ppc_hash_pte64_t *hptes,
1142 hwaddr ptex, int n)
1143 {
1144 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1145
1146 if (!spapr->htab) {
1147 g_free((void *)hptes);
1148 }
1149
1150 /* Nothing to do for qemu managed HPT */
1151 }
1152
1153 static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex,
1154 uint64_t pte0, uint64_t pte1)
1155 {
1156 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1157 hwaddr offset = ptex * HASH_PTE_SIZE_64;
1158
1159 if (!spapr->htab) {
1160 kvmppc_write_hpte(ptex, pte0, pte1);
1161 } else {
1162 stq_p(spapr->htab + offset, pte0);
1163 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1);
1164 }
1165 }
1166
1167 static int spapr_hpt_shift_for_ramsize(uint64_t ramsize)
1168 {
1169 int shift;
1170
1171 /* We aim for a hash table of size 1/128 the size of RAM (rounded
1172 * up). The PAPR recommendation is actually 1/64 of RAM size, but
1173 * that's much more than is needed for Linux guests */
1174 shift = ctz64(pow2ceil(ramsize)) - 7;
1175 shift = MAX(shift, 18); /* Minimum architected size */
1176 shift = MIN(shift, 46); /* Maximum architected size */
1177 return shift;
1178 }
1179
1180 static void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift,
1181 Error **errp)
1182 {
1183 long rc;
1184
1185 /* Clean up any HPT info from a previous boot */
1186 g_free(spapr->htab);
1187 spapr->htab = NULL;
1188 spapr->htab_shift = 0;
1189 close_htab_fd(spapr);
1190
1191 rc = kvmppc_reset_htab(shift);
1192 if (rc < 0) {
1193 /* kernel-side HPT needed, but couldn't allocate one */
1194 error_setg_errno(errp, errno,
1195 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1196 shift);
1197 /* This is almost certainly fatal, but if the caller really
1198 * wants to carry on with shift == 0, it's welcome to try */
1199 } else if (rc > 0) {
1200 /* kernel-side HPT allocated */
1201 if (rc != shift) {
1202 error_setg(errp,
1203 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1204 shift, rc);
1205 }
1206
1207 spapr->htab_shift = shift;
1208 spapr->htab = NULL;
1209 } else {
1210 /* kernel-side HPT not needed, allocate in userspace instead */
1211 size_t size = 1ULL << shift;
1212 int i;
1213
1214 spapr->htab = qemu_memalign(size, size);
1215 if (!spapr->htab) {
1216 error_setg_errno(errp, errno,
1217 "Could not allocate HPT of order %d", shift);
1218 return;
1219 }
1220
1221 memset(spapr->htab, 0, size);
1222 spapr->htab_shift = shift;
1223
1224 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) {
1225 DIRTY_HPTE(HPTE(spapr->htab, i));
1226 }
1227 }
1228 }
1229
1230 static void find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque)
1231 {
1232 bool matched = false;
1233
1234 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
1235 matched = true;
1236 }
1237
1238 if (!matched) {
1239 error_report("Device %s is not supported by this machine yet.",
1240 qdev_fw_name(DEVICE(sbdev)));
1241 exit(1);
1242 }
1243 }
1244
1245 static void ppc_spapr_reset(void)
1246 {
1247 MachineState *machine = MACHINE(qdev_get_machine());
1248 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
1249 PowerPCCPU *first_ppc_cpu;
1250 uint32_t rtas_limit;
1251 hwaddr rtas_addr, fdt_addr;
1252 void *fdt;
1253 int rc;
1254
1255 /* Check for unknown sysbus devices */
1256 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL);
1257
1258 spapr->patb_entry = 0;
1259
1260 /* Allocate and/or reset the hash page table */
1261 spapr_reallocate_hpt(spapr,
1262 spapr_hpt_shift_for_ramsize(machine->maxram_size),
1263 &error_fatal);
1264
1265 /* Update the RMA size if necessary */
1266 if (spapr->vrma_adjust) {
1267 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(),
1268 spapr->htab_shift);
1269 }
1270
1271 qemu_devices_reset();
1272
1273 /*
1274 * We place the device tree and RTAS just below either the top of the RMA,
1275 * or just below 2GB, whichever is lowere, so that it can be
1276 * processed with 32-bit real mode code if necessary
1277 */
1278 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR);
1279 rtas_addr = rtas_limit - RTAS_MAX_SIZE;
1280 fdt_addr = rtas_addr - FDT_MAX_SIZE;
1281
1282 /* if this reset wasn't generated by CAS, we should reset our
1283 * negotiated options and start from scratch */
1284 if (!spapr->cas_reboot) {
1285 spapr_ovec_cleanup(spapr->ov5_cas);
1286 spapr->ov5_cas = spapr_ovec_new();
1287 }
1288
1289 fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size);
1290
1291 spapr_load_rtas(spapr, fdt, rtas_addr);
1292
1293 rc = fdt_pack(fdt);
1294
1295 /* Should only fail if we've built a corrupted tree */
1296 assert(rc == 0);
1297
1298 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) {
1299 error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
1300 fdt_totalsize(fdt), FDT_MAX_SIZE);
1301 exit(1);
1302 }
1303
1304 /* Load the fdt */
1305 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
1306 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
1307 g_free(fdt);
1308
1309 /* Set up the entry state */
1310 first_ppc_cpu = POWERPC_CPU(first_cpu);
1311 first_ppc_cpu->env.gpr[3] = fdt_addr;
1312 first_ppc_cpu->env.gpr[5] = 0;
1313 first_cpu->halted = 0;
1314 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT;
1315
1316 spapr->cas_reboot = false;
1317 }
1318
1319 static void spapr_create_nvram(sPAPRMachineState *spapr)
1320 {
1321 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram");
1322 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
1323
1324 if (dinfo) {
1325 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
1326 &error_fatal);
1327 }
1328
1329 qdev_init_nofail(dev);
1330
1331 spapr->nvram = (struct sPAPRNVRAM *)dev;
1332 }
1333
1334 static void spapr_rtc_create(sPAPRMachineState *spapr)
1335 {
1336 DeviceState *dev = qdev_create(NULL, TYPE_SPAPR_RTC);
1337
1338 qdev_init_nofail(dev);
1339 spapr->rtc = dev;
1340
1341 object_property_add_alias(qdev_get_machine(), "rtc-time",
1342 OBJECT(spapr->rtc), "date", NULL);
1343 }
1344
1345 /* Returns whether we want to use VGA or not */
1346 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp)
1347 {
1348 switch (vga_interface_type) {
1349 case VGA_NONE:
1350 return false;
1351 case VGA_DEVICE:
1352 return true;
1353 case VGA_STD:
1354 case VGA_VIRTIO:
1355 return pci_vga_init(pci_bus) != NULL;
1356 default:
1357 error_setg(errp,
1358 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1359 return false;
1360 }
1361 }
1362
1363 static int spapr_post_load(void *opaque, int version_id)
1364 {
1365 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque;
1366 int err = 0;
1367
1368 if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) {
1369 int i;
1370 for (i = 0; i < spapr->nr_servers; i++) {
1371 icp_resend(&spapr->icps[i]);
1372 }
1373 }
1374
1375 /* In earlier versions, there was no separate qdev for the PAPR
1376 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1377 * So when migrating from those versions, poke the incoming offset
1378 * value into the RTC device */
1379 if (version_id < 3) {
1380 err = spapr_rtc_import_offset(spapr->rtc, spapr->rtc_offset);
1381 }
1382
1383 return err;
1384 }
1385
1386 static bool version_before_3(void *opaque, int version_id)
1387 {
1388 return version_id < 3;
1389 }
1390
1391 static bool spapr_ov5_cas_needed(void *opaque)
1392 {
1393 sPAPRMachineState *spapr = opaque;
1394 sPAPROptionVector *ov5_mask = spapr_ovec_new();
1395 sPAPROptionVector *ov5_legacy = spapr_ovec_new();
1396 sPAPROptionVector *ov5_removed = spapr_ovec_new();
1397 bool cas_needed;
1398
1399 /* Prior to the introduction of sPAPROptionVector, we had two option
1400 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY.
1401 * Both of these options encode machine topology into the device-tree
1402 * in such a way that the now-booted OS should still be able to interact
1403 * appropriately with QEMU regardless of what options were actually
1404 * negotiatied on the source side.
1405 *
1406 * As such, we can avoid migrating the CAS-negotiated options if these
1407 * are the only options available on the current machine/platform.
1408 * Since these are the only options available for pseries-2.7 and
1409 * earlier, this allows us to maintain old->new/new->old migration
1410 * compatibility.
1411 *
1412 * For QEMU 2.8+, there are additional CAS-negotiatable options available
1413 * via default pseries-2.8 machines and explicit command-line parameters.
1414 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware
1415 * of the actual CAS-negotiated values to continue working properly. For
1416 * example, availability of memory unplug depends on knowing whether
1417 * OV5_HP_EVT was negotiated via CAS.
1418 *
1419 * Thus, for any cases where the set of available CAS-negotiatable
1420 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we
1421 * include the CAS-negotiated options in the migration stream.
1422 */
1423 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY);
1424 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY);
1425
1426 /* spapr_ovec_diff returns true if bits were removed. we avoid using
1427 * the mask itself since in the future it's possible "legacy" bits may be
1428 * removed via machine options, which could generate a false positive
1429 * that breaks migration.
1430 */
1431 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask);
1432 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy);
1433
1434 spapr_ovec_cleanup(ov5_mask);
1435 spapr_ovec_cleanup(ov5_legacy);
1436 spapr_ovec_cleanup(ov5_removed);
1437
1438 return cas_needed;
1439 }
1440
1441 static const VMStateDescription vmstate_spapr_ov5_cas = {
1442 .name = "spapr_option_vector_ov5_cas",
1443 .version_id = 1,
1444 .minimum_version_id = 1,
1445 .needed = spapr_ov5_cas_needed,
1446 .fields = (VMStateField[]) {
1447 VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1,
1448 vmstate_spapr_ovec, sPAPROptionVector),
1449 VMSTATE_END_OF_LIST()
1450 },
1451 };
1452
1453 static bool spapr_patb_entry_needed(void *opaque)
1454 {
1455 sPAPRMachineState *spapr = opaque;
1456
1457 return !!spapr->patb_entry;
1458 }
1459
1460 static const VMStateDescription vmstate_spapr_patb_entry = {
1461 .name = "spapr_patb_entry",
1462 .version_id = 1,
1463 .minimum_version_id = 1,
1464 .needed = spapr_patb_entry_needed,
1465 .fields = (VMStateField[]) {
1466 VMSTATE_UINT64(patb_entry, sPAPRMachineState),
1467 VMSTATE_END_OF_LIST()
1468 },
1469 };
1470
1471 static const VMStateDescription vmstate_spapr = {
1472 .name = "spapr",
1473 .version_id = 3,
1474 .minimum_version_id = 1,
1475 .post_load = spapr_post_load,
1476 .fields = (VMStateField[]) {
1477 /* used to be @next_irq */
1478 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4),
1479
1480 /* RTC offset */
1481 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3),
1482
1483 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2),
1484 VMSTATE_END_OF_LIST()
1485 },
1486 .subsections = (const VMStateDescription*[]) {
1487 &vmstate_spapr_ov5_cas,
1488 &vmstate_spapr_patb_entry,
1489 NULL
1490 }
1491 };
1492
1493 static int htab_save_setup(QEMUFile *f, void *opaque)
1494 {
1495 sPAPRMachineState *spapr = opaque;
1496
1497 /* "Iteration" header */
1498 qemu_put_be32(f, spapr->htab_shift);
1499
1500 if (spapr->htab) {
1501 spapr->htab_save_index = 0;
1502 spapr->htab_first_pass = true;
1503 } else {
1504 assert(kvm_enabled());
1505 }
1506
1507
1508 return 0;
1509 }
1510
1511 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr,
1512 int64_t max_ns)
1513 {
1514 bool has_timeout = max_ns != -1;
1515 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1516 int index = spapr->htab_save_index;
1517 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1518
1519 assert(spapr->htab_first_pass);
1520
1521 do {
1522 int chunkstart;
1523
1524 /* Consume invalid HPTEs */
1525 while ((index < htabslots)
1526 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1527 CLEAN_HPTE(HPTE(spapr->htab, index));
1528 index++;
1529 }
1530
1531 /* Consume valid HPTEs */
1532 chunkstart = index;
1533 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
1534 && HPTE_VALID(HPTE(spapr->htab, index))) {
1535 CLEAN_HPTE(HPTE(spapr->htab, index));
1536 index++;
1537 }
1538
1539 if (index > chunkstart) {
1540 int n_valid = index - chunkstart;
1541
1542 qemu_put_be32(f, chunkstart);
1543 qemu_put_be16(f, n_valid);
1544 qemu_put_be16(f, 0);
1545 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1546 HASH_PTE_SIZE_64 * n_valid);
1547
1548 if (has_timeout &&
1549 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1550 break;
1551 }
1552 }
1553 } while ((index < htabslots) && !qemu_file_rate_limit(f));
1554
1555 if (index >= htabslots) {
1556 assert(index == htabslots);
1557 index = 0;
1558 spapr->htab_first_pass = false;
1559 }
1560 spapr->htab_save_index = index;
1561 }
1562
1563 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr,
1564 int64_t max_ns)
1565 {
1566 bool final = max_ns < 0;
1567 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1568 int examined = 0, sent = 0;
1569 int index = spapr->htab_save_index;
1570 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1571
1572 assert(!spapr->htab_first_pass);
1573
1574 do {
1575 int chunkstart, invalidstart;
1576
1577 /* Consume non-dirty HPTEs */
1578 while ((index < htabslots)
1579 && !HPTE_DIRTY(HPTE(spapr->htab, index))) {
1580 index++;
1581 examined++;
1582 }
1583
1584 chunkstart = index;
1585 /* Consume valid dirty HPTEs */
1586 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
1587 && HPTE_DIRTY(HPTE(spapr->htab, index))
1588 && HPTE_VALID(HPTE(spapr->htab, index))) {
1589 CLEAN_HPTE(HPTE(spapr->htab, index));
1590 index++;
1591 examined++;
1592 }
1593
1594 invalidstart = index;
1595 /* Consume invalid dirty HPTEs */
1596 while ((index < htabslots) && (index - invalidstart < USHRT_MAX)
1597 && HPTE_DIRTY(HPTE(spapr->htab, index))
1598 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1599 CLEAN_HPTE(HPTE(spapr->htab, index));
1600 index++;
1601 examined++;
1602 }
1603
1604 if (index > chunkstart) {
1605 int n_valid = invalidstart - chunkstart;
1606 int n_invalid = index - invalidstart;
1607
1608 qemu_put_be32(f, chunkstart);
1609 qemu_put_be16(f, n_valid);
1610 qemu_put_be16(f, n_invalid);
1611 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1612 HASH_PTE_SIZE_64 * n_valid);
1613 sent += index - chunkstart;
1614
1615 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1616 break;
1617 }
1618 }
1619
1620 if (examined >= htabslots) {
1621 break;
1622 }
1623
1624 if (index >= htabslots) {
1625 assert(index == htabslots);
1626 index = 0;
1627 }
1628 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final));
1629
1630 if (index >= htabslots) {
1631 assert(index == htabslots);
1632 index = 0;
1633 }
1634
1635 spapr->htab_save_index = index;
1636
1637 return (examined >= htabslots) && (sent == 0) ? 1 : 0;
1638 }
1639
1640 #define MAX_ITERATION_NS 5000000 /* 5 ms */
1641 #define MAX_KVM_BUF_SIZE 2048
1642
1643 static int htab_save_iterate(QEMUFile *f, void *opaque)
1644 {
1645 sPAPRMachineState *spapr = opaque;
1646 int fd;
1647 int rc = 0;
1648
1649 /* Iteration header */
1650 qemu_put_be32(f, 0);
1651
1652 if (!spapr->htab) {
1653 assert(kvm_enabled());
1654
1655 fd = get_htab_fd(spapr);
1656 if (fd < 0) {
1657 return fd;
1658 }
1659
1660 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS);
1661 if (rc < 0) {
1662 return rc;
1663 }
1664 } else if (spapr->htab_first_pass) {
1665 htab_save_first_pass(f, spapr, MAX_ITERATION_NS);
1666 } else {
1667 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS);
1668 }
1669
1670 /* End marker */
1671 qemu_put_be32(f, 0);
1672 qemu_put_be16(f, 0);
1673 qemu_put_be16(f, 0);
1674
1675 return rc;
1676 }
1677
1678 static int htab_save_complete(QEMUFile *f, void *opaque)
1679 {
1680 sPAPRMachineState *spapr = opaque;
1681 int fd;
1682
1683 /* Iteration header */
1684 qemu_put_be32(f, 0);
1685
1686 if (!spapr->htab) {
1687 int rc;
1688
1689 assert(kvm_enabled());
1690
1691 fd = get_htab_fd(spapr);
1692 if (fd < 0) {
1693 return fd;
1694 }
1695
1696 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1);
1697 if (rc < 0) {
1698 return rc;
1699 }
1700 } else {
1701 if (spapr->htab_first_pass) {
1702 htab_save_first_pass(f, spapr, -1);
1703 }
1704 htab_save_later_pass(f, spapr, -1);
1705 }
1706
1707 /* End marker */
1708 qemu_put_be32(f, 0);
1709 qemu_put_be16(f, 0);
1710 qemu_put_be16(f, 0);
1711
1712 return 0;
1713 }
1714
1715 static int htab_load(QEMUFile *f, void *opaque, int version_id)
1716 {
1717 sPAPRMachineState *spapr = opaque;
1718 uint32_t section_hdr;
1719 int fd = -1;
1720
1721 if (version_id < 1 || version_id > 1) {
1722 error_report("htab_load() bad version");
1723 return -EINVAL;
1724 }
1725
1726 section_hdr = qemu_get_be32(f);
1727
1728 if (section_hdr) {
1729 Error *local_err = NULL;
1730
1731 /* First section gives the htab size */
1732 spapr_reallocate_hpt(spapr, section_hdr, &local_err);
1733 if (local_err) {
1734 error_report_err(local_err);
1735 return -EINVAL;
1736 }
1737 return 0;
1738 }
1739
1740 if (!spapr->htab) {
1741 assert(kvm_enabled());
1742
1743 fd = kvmppc_get_htab_fd(true);
1744 if (fd < 0) {
1745 error_report("Unable to open fd to restore KVM hash table: %s",
1746 strerror(errno));
1747 }
1748 }
1749
1750 while (true) {
1751 uint32_t index;
1752 uint16_t n_valid, n_invalid;
1753
1754 index = qemu_get_be32(f);
1755 n_valid = qemu_get_be16(f);
1756 n_invalid = qemu_get_be16(f);
1757
1758 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) {
1759 /* End of Stream */
1760 break;
1761 }
1762
1763 if ((index + n_valid + n_invalid) >
1764 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) {
1765 /* Bad index in stream */
1766 error_report(
1767 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
1768 index, n_valid, n_invalid, spapr->htab_shift);
1769 return -EINVAL;
1770 }
1771
1772 if (spapr->htab) {
1773 if (n_valid) {
1774 qemu_get_buffer(f, HPTE(spapr->htab, index),
1775 HASH_PTE_SIZE_64 * n_valid);
1776 }
1777 if (n_invalid) {
1778 memset(HPTE(spapr->htab, index + n_valid), 0,
1779 HASH_PTE_SIZE_64 * n_invalid);
1780 }
1781 } else {
1782 int rc;
1783
1784 assert(fd >= 0);
1785
1786 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid);
1787 if (rc < 0) {
1788 return rc;
1789 }
1790 }
1791 }
1792
1793 if (!spapr->htab) {
1794 assert(fd >= 0);
1795 close(fd);
1796 }
1797
1798 return 0;
1799 }
1800
1801 static void htab_cleanup(void *opaque)
1802 {
1803 sPAPRMachineState *spapr = opaque;
1804
1805 close_htab_fd(spapr);
1806 }
1807
1808 static SaveVMHandlers savevm_htab_handlers = {
1809 .save_live_setup = htab_save_setup,
1810 .save_live_iterate = htab_save_iterate,
1811 .save_live_complete_precopy = htab_save_complete,
1812 .cleanup = htab_cleanup,
1813 .load_state = htab_load,
1814 };
1815
1816 static void spapr_boot_set(void *opaque, const char *boot_device,
1817 Error **errp)
1818 {
1819 MachineState *machine = MACHINE(qdev_get_machine());
1820 machine->boot_order = g_strdup(boot_device);
1821 }
1822
1823 /*
1824 * Reset routine for LMB DR devices.
1825 *
1826 * Unlike PCI DR devices, LMB DR devices explicitly register this reset
1827 * routine. Reset for PCI DR devices will be handled by PHB reset routine
1828 * when it walks all its children devices. LMB devices reset occurs
1829 * as part of spapr_ppc_reset().
1830 */
1831 static void spapr_drc_reset(void *opaque)
1832 {
1833 sPAPRDRConnector *drc = opaque;
1834 DeviceState *d = DEVICE(drc);
1835
1836 if (d) {
1837 device_reset(d);
1838 }
1839 }
1840
1841 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr)
1842 {
1843 MachineState *machine = MACHINE(spapr);
1844 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
1845 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size;
1846 int i;
1847
1848 for (i = 0; i < nr_lmbs; i++) {
1849 sPAPRDRConnector *drc;
1850 uint64_t addr;
1851
1852 addr = i * lmb_size + spapr->hotplug_memory.base;
1853 drc = spapr_dr_connector_new(OBJECT(spapr), SPAPR_DR_CONNECTOR_TYPE_LMB,
1854 addr/lmb_size);
1855 qemu_register_reset(spapr_drc_reset, drc);
1856 }
1857 }
1858
1859 /*
1860 * If RAM size, maxmem size and individual node mem sizes aren't aligned
1861 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
1862 * since we can't support such unaligned sizes with DRCONF_MEMORY.
1863 */
1864 static void spapr_validate_node_memory(MachineState *machine, Error **errp)
1865 {
1866 int i;
1867
1868 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) {
1869 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT
1870 " is not aligned to %llu MiB",
1871 machine->ram_size,
1872 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1873 return;
1874 }
1875
1876 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) {
1877 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT
1878 " is not aligned to %llu MiB",
1879 machine->ram_size,
1880 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1881 return;
1882 }
1883
1884 for (i = 0; i < nb_numa_nodes; i++) {
1885 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) {
1886 error_setg(errp,
1887 "Node %d memory size 0x%" PRIx64
1888 " is not aligned to %llu MiB",
1889 i, numa_info[i].node_mem,
1890 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1891 return;
1892 }
1893 }
1894 }
1895
1896 /* find cpu slot in machine->possible_cpus by core_id */
1897 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
1898 {
1899 int index = id / smp_threads;
1900
1901 if (index >= ms->possible_cpus->len) {
1902 return NULL;
1903 }
1904 if (idx) {
1905 *idx = index;
1906 }
1907 return &ms->possible_cpus->cpus[index];
1908 }
1909
1910 static void spapr_init_cpus(sPAPRMachineState *spapr)
1911 {
1912 MachineState *machine = MACHINE(spapr);
1913 MachineClass *mc = MACHINE_GET_CLASS(machine);
1914 char *type = spapr_get_cpu_core_type(machine->cpu_model);
1915 int smt = kvmppc_smt_threads();
1916 const CPUArchIdList *possible_cpus;
1917 int boot_cores_nr = smp_cpus / smp_threads;
1918 int i;
1919
1920 if (!type) {
1921 error_report("Unable to find sPAPR CPU Core definition");
1922 exit(1);
1923 }
1924
1925 possible_cpus = mc->possible_cpu_arch_ids(machine);
1926 if (mc->has_hotpluggable_cpus) {
1927 if (smp_cpus % smp_threads) {
1928 error_report("smp_cpus (%u) must be multiple of threads (%u)",
1929 smp_cpus, smp_threads);
1930 exit(1);
1931 }
1932 if (max_cpus % smp_threads) {
1933 error_report("max_cpus (%u) must be multiple of threads (%u)",
1934 max_cpus, smp_threads);
1935 exit(1);
1936 }
1937 } else {
1938 if (max_cpus != smp_cpus) {
1939 error_report("This machine version does not support CPU hotplug");
1940 exit(1);
1941 }
1942 boot_cores_nr = possible_cpus->len;
1943 }
1944
1945 for (i = 0; i < possible_cpus->len; i++) {
1946 int core_id = i * smp_threads;
1947
1948 if (mc->has_hotpluggable_cpus) {
1949 sPAPRDRConnector *drc =
1950 spapr_dr_connector_new(OBJECT(spapr),
1951 SPAPR_DR_CONNECTOR_TYPE_CPU,
1952 (core_id / smp_threads) * smt);
1953
1954 qemu_register_reset(spapr_drc_reset, drc);
1955 }
1956
1957 if (i < boot_cores_nr) {
1958 Object *core = object_new(type);
1959 int nr_threads = smp_threads;
1960
1961 /* Handle the partially filled core for older machine types */
1962 if ((i + 1) * smp_threads >= smp_cpus) {
1963 nr_threads = smp_cpus - i * smp_threads;
1964 }
1965
1966 object_property_set_int(core, nr_threads, "nr-threads",
1967 &error_fatal);
1968 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID,
1969 &error_fatal);
1970 object_property_set_bool(core, true, "realized", &error_fatal);
1971 }
1972 }
1973 g_free(type);
1974 }
1975
1976 /* pSeries LPAR / sPAPR hardware init */
1977 static void ppc_spapr_init(MachineState *machine)
1978 {
1979 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
1980 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
1981 const char *kernel_filename = machine->kernel_filename;
1982 const char *initrd_filename = machine->initrd_filename;
1983 PCIHostState *phb;
1984 int i;
1985 MemoryRegion *sysmem = get_system_memory();
1986 MemoryRegion *ram = g_new(MemoryRegion, 1);
1987 MemoryRegion *rma_region;
1988 void *rma = NULL;
1989 hwaddr rma_alloc_size;
1990 hwaddr node0_size = spapr_node0_size();
1991 long load_limit, fw_size;
1992 char *filename;
1993 int smt = kvmppc_smt_threads();
1994
1995 msi_nonbroken = true;
1996
1997 QLIST_INIT(&spapr->phbs);
1998
1999 /* Allocate RMA if necessary */
2000 rma_alloc_size = kvmppc_alloc_rma(&rma);
2001
2002 if (rma_alloc_size == -1) {
2003 error_report("Unable to create RMA");
2004 exit(1);
2005 }
2006
2007 if (rma_alloc_size && (rma_alloc_size < node0_size)) {
2008 spapr->rma_size = rma_alloc_size;
2009 } else {
2010 spapr->rma_size = node0_size;
2011
2012 /* With KVM, we don't actually know whether KVM supports an
2013 * unbounded RMA (PR KVM) or is limited by the hash table size
2014 * (HV KVM using VRMA), so we always assume the latter
2015 *
2016 * In that case, we also limit the initial allocations for RTAS
2017 * etc... to 256M since we have no way to know what the VRMA size
2018 * is going to be as it depends on the size of the hash table
2019 * isn't determined yet.
2020 */
2021 if (kvm_enabled()) {
2022 spapr->vrma_adjust = 1;
2023 spapr->rma_size = MIN(spapr->rma_size, 0x10000000);
2024 }
2025
2026 /* Actually we don't support unbounded RMA anymore since we
2027 * added proper emulation of HV mode. The max we can get is
2028 * 16G which also happens to be what we configure for PAPR
2029 * mode so make sure we don't do anything bigger than that
2030 */
2031 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull);
2032 }
2033
2034 if (spapr->rma_size > node0_size) {
2035 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")",
2036 spapr->rma_size);
2037 exit(1);
2038 }
2039
2040 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
2041 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD;
2042
2043 /* Set up Interrupt Controller before we create the VCPUs */
2044 xics_system_init(machine, DIV_ROUND_UP(max_cpus * smt, smp_threads),
2045 XICS_IRQS_SPAPR, &error_fatal);
2046
2047 /* Set up containers for ibm,client-set-architecture negotiated options */
2048 spapr->ov5 = spapr_ovec_new();
2049 spapr->ov5_cas = spapr_ovec_new();
2050
2051 if (smc->dr_lmb_enabled) {
2052 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY);
2053 spapr_validate_node_memory(machine, &error_fatal);
2054 }
2055
2056 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY);
2057
2058 /* advertise support for dedicated HP event source to guests */
2059 if (spapr->use_hotplug_event_source) {
2060 spapr_ovec_set(spapr->ov5, OV5_HP_EVT);
2061 }
2062
2063 /* init CPUs */
2064 if (machine->cpu_model == NULL) {
2065 machine->cpu_model = kvm_enabled() ? "host" : smc->tcg_default_cpu;
2066 }
2067
2068 ppc_cpu_parse_features(machine->cpu_model);
2069
2070 spapr_init_cpus(spapr);
2071
2072 if (kvm_enabled()) {
2073 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
2074 kvmppc_enable_logical_ci_hcalls();
2075 kvmppc_enable_set_mode_hcall();
2076
2077 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */
2078 kvmppc_enable_clear_ref_mod_hcalls();
2079 }
2080
2081 /* allocate RAM */
2082 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram",
2083 machine->ram_size);
2084 memory_region_add_subregion(sysmem, 0, ram);
2085
2086 if (rma_alloc_size && rma) {
2087 rma_region = g_new(MemoryRegion, 1);
2088 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma",
2089 rma_alloc_size, rma);
2090 vmstate_register_ram_global(rma_region);
2091 memory_region_add_subregion(sysmem, 0, rma_region);
2092 }
2093
2094 /* initialize hotplug memory address space */
2095 if (machine->ram_size < machine->maxram_size) {
2096 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size;
2097 /*
2098 * Limit the number of hotpluggable memory slots to half the number
2099 * slots that KVM supports, leaving the other half for PCI and other
2100 * devices. However ensure that number of slots doesn't drop below 32.
2101 */
2102 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 :
2103 SPAPR_MAX_RAM_SLOTS;
2104
2105 if (max_memslots < SPAPR_MAX_RAM_SLOTS) {
2106 max_memslots = SPAPR_MAX_RAM_SLOTS;
2107 }
2108 if (machine->ram_slots > max_memslots) {
2109 error_report("Specified number of memory slots %"
2110 PRIu64" exceeds max supported %d",
2111 machine->ram_slots, max_memslots);
2112 exit(1);
2113 }
2114
2115 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size,
2116 SPAPR_HOTPLUG_MEM_ALIGN);
2117 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr),
2118 "hotplug-memory", hotplug_mem_size);
2119 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base,
2120 &spapr->hotplug_memory.mr);
2121 }
2122
2123 if (smc->dr_lmb_enabled) {
2124 spapr_create_lmb_dr_connectors(spapr);
2125 }
2126
2127 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
2128 if (!filename) {
2129 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin");
2130 exit(1);
2131 }
2132 spapr->rtas_size = get_image_size(filename);
2133 if (spapr->rtas_size < 0) {
2134 error_report("Could not get size of LPAR rtas '%s'", filename);
2135 exit(1);
2136 }
2137 spapr->rtas_blob = g_malloc(spapr->rtas_size);
2138 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) {
2139 error_report("Could not load LPAR rtas '%s'", filename);
2140 exit(1);
2141 }
2142 if (spapr->rtas_size > RTAS_MAX_SIZE) {
2143 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)",
2144 (size_t)spapr->rtas_size, RTAS_MAX_SIZE);
2145 exit(1);
2146 }
2147 g_free(filename);
2148
2149 /* Set up RTAS event infrastructure */
2150 spapr_events_init(spapr);
2151
2152 /* Set up the RTC RTAS interfaces */
2153 spapr_rtc_create(spapr);
2154
2155 /* Set up VIO bus */
2156 spapr->vio_bus = spapr_vio_bus_init();
2157
2158 for (i = 0; i < MAX_SERIAL_PORTS; i++) {
2159 if (serial_hds[i]) {
2160 spapr_vty_create(spapr->vio_bus, serial_hds[i]);
2161 }
2162 }
2163
2164 /* We always have at least the nvram device on VIO */
2165 spapr_create_nvram(spapr);
2166
2167 /* Set up PCI */
2168 spapr_pci_rtas_init();
2169
2170 phb = spapr_create_phb(spapr, 0);
2171
2172 for (i = 0; i < nb_nics; i++) {
2173 NICInfo *nd = &nd_table[i];
2174
2175 if (!nd->model) {
2176 nd->model = g_strdup("ibmveth");
2177 }
2178
2179 if (strcmp(nd->model, "ibmveth") == 0) {
2180 spapr_vlan_create(spapr->vio_bus, nd);
2181 } else {
2182 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL);
2183 }
2184 }
2185
2186 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
2187 spapr_vscsi_create(spapr->vio_bus);
2188 }
2189
2190 /* Graphics */
2191 if (spapr_vga_init(phb->bus, &error_fatal)) {
2192 spapr->has_graphics = true;
2193 machine->usb |= defaults_enabled() && !machine->usb_disabled;
2194 }
2195
2196 if (machine->usb) {
2197 if (smc->use_ohci_by_default) {
2198 pci_create_simple(phb->bus, -1, "pci-ohci");
2199 } else {
2200 pci_create_simple(phb->bus, -1, "nec-usb-xhci");
2201 }
2202
2203 if (spapr->has_graphics) {
2204 USBBus *usb_bus = usb_bus_find(-1);
2205
2206 usb_create_simple(usb_bus, "usb-kbd");
2207 usb_create_simple(usb_bus, "usb-mouse");
2208 }
2209 }
2210
2211 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) {
2212 error_report(
2213 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
2214 MIN_RMA_SLOF);
2215 exit(1);
2216 }
2217
2218 if (kernel_filename) {
2219 uint64_t lowaddr = 0;
2220
2221 spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address,
2222 NULL, NULL, &lowaddr, NULL, 1,
2223 PPC_ELF_MACHINE, 0, 0);
2224 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) {
2225 spapr->kernel_size = load_elf(kernel_filename,
2226 translate_kernel_address, NULL, NULL,
2227 &lowaddr, NULL, 0, PPC_ELF_MACHINE,
2228 0, 0);
2229 spapr->kernel_le = spapr->kernel_size > 0;
2230 }
2231 if (spapr->kernel_size < 0) {
2232 error_report("error loading %s: %s", kernel_filename,
2233 load_elf_strerror(spapr->kernel_size));
2234 exit(1);
2235 }
2236
2237 /* load initrd */
2238 if (initrd_filename) {
2239 /* Try to locate the initrd in the gap between the kernel
2240 * and the firmware. Add a bit of space just in case
2241 */
2242 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size
2243 + 0x1ffff) & ~0xffff;
2244 spapr->initrd_size = load_image_targphys(initrd_filename,
2245 spapr->initrd_base,
2246 load_limit
2247 - spapr->initrd_base);
2248 if (spapr->initrd_size < 0) {
2249 error_report("could not load initial ram disk '%s'",
2250 initrd_filename);
2251 exit(1);
2252 }
2253 }
2254 }
2255
2256 if (bios_name == NULL) {
2257 bios_name = FW_FILE_NAME;
2258 }
2259 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
2260 if (!filename) {
2261 error_report("Could not find LPAR firmware '%s'", bios_name);
2262 exit(1);
2263 }
2264 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
2265 if (fw_size <= 0) {
2266 error_report("Could not load LPAR firmware '%s'", filename);
2267 exit(1);
2268 }
2269 g_free(filename);
2270
2271 /* FIXME: Should register things through the MachineState's qdev
2272 * interface, this is a legacy from the sPAPREnvironment structure
2273 * which predated MachineState but had a similar function */
2274 vmstate_register(NULL, 0, &vmstate_spapr, spapr);
2275 register_savevm_live(NULL, "spapr/htab", -1, 1,
2276 &savevm_htab_handlers, spapr);
2277
2278 /* used by RTAS */
2279 QTAILQ_INIT(&spapr->ccs_list);
2280 qemu_register_reset(spapr_ccs_reset_hook, spapr);
2281
2282 qemu_register_boot_set(spapr_boot_set, spapr);
2283
2284 /* to stop and start vmclock */
2285 if (kvm_enabled()) {
2286 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change,
2287 &spapr->tb);
2288 }
2289 }
2290
2291 static int spapr_kvm_type(const char *vm_type)
2292 {
2293 if (!vm_type) {
2294 return 0;
2295 }
2296
2297 if (!strcmp(vm_type, "HV")) {
2298 return 1;
2299 }
2300
2301 if (!strcmp(vm_type, "PR")) {
2302 return 2;
2303 }
2304
2305 error_report("Unknown kvm-type specified '%s'", vm_type);
2306 exit(1);
2307 }
2308
2309 /*
2310 * Implementation of an interface to adjust firmware path
2311 * for the bootindex property handling.
2312 */
2313 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus,
2314 DeviceState *dev)
2315 {
2316 #define CAST(type, obj, name) \
2317 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
2318 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE);
2319 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE);
2320
2321 if (d) {
2322 void *spapr = CAST(void, bus->parent, "spapr-vscsi");
2323 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI);
2324 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE);
2325
2326 if (spapr) {
2327 /*
2328 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
2329 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun
2330 * in the top 16 bits of the 64-bit LUN
2331 */
2332 unsigned id = 0x8000 | (d->id << 8) | d->lun;
2333 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2334 (uint64_t)id << 48);
2335 } else if (virtio) {
2336 /*
2337 * We use SRP luns of the form 01000000 | (target << 8) | lun
2338 * in the top 32 bits of the 64-bit LUN
2339 * Note: the quote above is from SLOF and it is wrong,
2340 * the actual binding is:
2341 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
2342 */
2343 unsigned id = 0x1000000 | (d->id << 16) | d->lun;
2344 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2345 (uint64_t)id << 32);
2346 } else if (usb) {
2347 /*
2348 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
2349 * in the top 32 bits of the 64-bit LUN
2350 */
2351 unsigned usb_port = atoi(usb->port->path);
2352 unsigned id = 0x1000000 | (usb_port << 16) | d->lun;
2353 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2354 (uint64_t)id << 32);
2355 }
2356 }
2357
2358 /*
2359 * SLOF probes the USB devices, and if it recognizes that the device is a
2360 * storage device, it changes its name to "storage" instead of "usb-host",
2361 * and additionally adds a child node for the SCSI LUN, so the correct
2362 * boot path in SLOF is something like .../storage@1/disk@xxx" instead.
2363 */
2364 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) {
2365 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE);
2366 if (usb_host_dev_is_scsi_storage(usbdev)) {
2367 return g_strdup_printf("storage@%s/disk", usbdev->port->path);
2368 }
2369 }
2370
2371 if (phb) {
2372 /* Replace "pci" with "pci@800000020000000" */
2373 return g_strdup_printf("pci@%"PRIX64, phb->buid);
2374 }
2375
2376 return NULL;
2377 }
2378
2379 static char *spapr_get_kvm_type(Object *obj, Error **errp)
2380 {
2381 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2382
2383 return g_strdup(spapr->kvm_type);
2384 }
2385
2386 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp)
2387 {
2388 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2389
2390 g_free(spapr->kvm_type);
2391 spapr->kvm_type = g_strdup(value);
2392 }
2393
2394 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp)
2395 {
2396 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2397
2398 return spapr->use_hotplug_event_source;
2399 }
2400
2401 static void spapr_set_modern_hotplug_events(Object *obj, bool value,
2402 Error **errp)
2403 {
2404 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2405
2406 spapr->use_hotplug_event_source = value;
2407 }
2408
2409 static void spapr_machine_initfn(Object *obj)
2410 {
2411 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2412
2413 spapr->htab_fd = -1;
2414 spapr->use_hotplug_event_source = true;
2415 object_property_add_str(obj, "kvm-type",
2416 spapr_get_kvm_type, spapr_set_kvm_type, NULL);
2417 object_property_set_description(obj, "kvm-type",
2418 "Specifies the KVM virtualization mode (HV, PR)",
2419 NULL);
2420 object_property_add_bool(obj, "modern-hotplug-events",
2421 spapr_get_modern_hotplug_events,
2422 spapr_set_modern_hotplug_events,
2423 NULL);
2424 object_property_set_description(obj, "modern-hotplug-events",
2425 "Use dedicated hotplug event mechanism in"
2426 " place of standard EPOW events when possible"
2427 " (required for memory hot-unplug support)",
2428 NULL);
2429 }
2430
2431 static void spapr_machine_finalizefn(Object *obj)
2432 {
2433 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2434
2435 g_free(spapr->kvm_type);
2436 }
2437
2438 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg)
2439 {
2440 cpu_synchronize_state(cs);
2441 ppc_cpu_do_system_reset(cs);
2442 }
2443
2444 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp)
2445 {
2446 CPUState *cs;
2447
2448 CPU_FOREACH(cs) {
2449 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL);
2450 }
2451 }
2452
2453 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size,
2454 uint32_t node, bool dedicated_hp_event_source,
2455 Error **errp)
2456 {
2457 sPAPRDRConnector *drc;
2458 sPAPRDRConnectorClass *drck;
2459 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE;
2460 int i, fdt_offset, fdt_size;
2461 void *fdt;
2462 uint64_t addr = addr_start;
2463
2464 for (i = 0; i < nr_lmbs; i++) {
2465 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB,
2466 addr/SPAPR_MEMORY_BLOCK_SIZE);
2467 g_assert(drc);
2468
2469 fdt = create_device_tree(&fdt_size);
2470 fdt_offset = spapr_populate_memory_node(fdt, node, addr,
2471 SPAPR_MEMORY_BLOCK_SIZE);
2472
2473 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2474 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, errp);
2475 addr += SPAPR_MEMORY_BLOCK_SIZE;
2476 if (!dev->hotplugged) {
2477 /* guests expect coldplugged LMBs to be pre-allocated */
2478 drck->set_allocation_state(drc, SPAPR_DR_ALLOCATION_STATE_USABLE);
2479 drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED);
2480 }
2481 }
2482 /* send hotplug notification to the
2483 * guest only in case of hotplugged memory
2484 */
2485 if (dev->hotplugged) {
2486 if (dedicated_hp_event_source) {
2487 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB,
2488 addr_start / SPAPR_MEMORY_BLOCK_SIZE);
2489 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2490 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
2491 nr_lmbs,
2492 drck->get_index(drc));
2493 } else {
2494 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB,
2495 nr_lmbs);
2496 }
2497 }
2498 }
2499
2500 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2501 uint32_t node, Error **errp)
2502 {
2503 Error *local_err = NULL;
2504 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev);
2505 PCDIMMDevice *dimm = PC_DIMM(dev);
2506 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2507 MemoryRegion *mr = ddc->get_memory_region(dimm);
2508 uint64_t align = memory_region_get_alignment(mr);
2509 uint64_t size = memory_region_size(mr);
2510 uint64_t addr;
2511 char *mem_dev;
2512
2513 if (size % SPAPR_MEMORY_BLOCK_SIZE) {
2514 error_setg(&local_err, "Hotplugged memory size must be a multiple of "
2515 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE/M_BYTE);
2516 goto out;
2517 }
2518
2519 mem_dev = object_property_get_str(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, NULL);
2520 if (mem_dev && !kvmppc_is_mem_backend_page_size_ok(mem_dev)) {
2521 error_setg(&local_err, "Memory backend has bad page size. "
2522 "Use 'memory-backend-file' with correct mem-path.");
2523 goto out;
2524 }
2525
2526 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err);
2527 if (local_err) {
2528 goto out;
2529 }
2530
2531 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err);
2532 if (local_err) {
2533 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr);
2534 goto out;
2535 }
2536
2537 spapr_add_lmbs(dev, addr, size, node,
2538 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT),
2539 &error_abort);
2540
2541 out:
2542 error_propagate(errp, local_err);
2543 }
2544
2545 typedef struct sPAPRDIMMState {
2546 uint32_t nr_lmbs;
2547 } sPAPRDIMMState;
2548
2549 static void spapr_lmb_release(DeviceState *dev, void *opaque)
2550 {
2551 sPAPRDIMMState *ds = (sPAPRDIMMState *)opaque;
2552 HotplugHandler *hotplug_ctrl;
2553
2554 if (--ds->nr_lmbs) {
2555 return;
2556 }
2557
2558 g_free(ds);
2559
2560 /*
2561 * Now that all the LMBs have been removed by the guest, call the
2562 * pc-dimm unplug handler to cleanup up the pc-dimm device.
2563 */
2564 hotplug_ctrl = qdev_get_hotplug_handler(dev);
2565 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort);
2566 }
2567
2568 static void spapr_del_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size,
2569 Error **errp)
2570 {
2571 sPAPRDRConnector *drc;
2572 sPAPRDRConnectorClass *drck;
2573 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE;
2574 int i;
2575 sPAPRDIMMState *ds = g_malloc0(sizeof(sPAPRDIMMState));
2576 uint64_t addr = addr_start;
2577
2578 ds->nr_lmbs = nr_lmbs;
2579 for (i = 0; i < nr_lmbs; i++) {
2580 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB,
2581 addr / SPAPR_MEMORY_BLOCK_SIZE);
2582 g_assert(drc);
2583
2584 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2585 drck->detach(drc, dev, spapr_lmb_release, ds, errp);
2586 addr += SPAPR_MEMORY_BLOCK_SIZE;
2587 }
2588
2589 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB,
2590 addr_start / SPAPR_MEMORY_BLOCK_SIZE);
2591 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2592 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
2593 nr_lmbs,
2594 drck->get_index(drc));
2595 }
2596
2597 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev,
2598 Error **errp)
2599 {
2600 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev);
2601 PCDIMMDevice *dimm = PC_DIMM(dev);
2602 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2603 MemoryRegion *mr = ddc->get_memory_region(dimm);
2604
2605 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr);
2606 object_unparent(OBJECT(dev));
2607 }
2608
2609 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev,
2610 DeviceState *dev, Error **errp)
2611 {
2612 Error *local_err = NULL;
2613 PCDIMMDevice *dimm = PC_DIMM(dev);
2614 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2615 MemoryRegion *mr = ddc->get_memory_region(dimm);
2616 uint64_t size = memory_region_size(mr);
2617 uint64_t addr;
2618
2619 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err);
2620 if (local_err) {
2621 goto out;
2622 }
2623
2624 spapr_del_lmbs(dev, addr, size, &error_abort);
2625 out:
2626 error_propagate(errp, local_err);
2627 }
2628
2629 void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset,
2630 sPAPRMachineState *spapr)
2631 {
2632 PowerPCCPU *cpu = POWERPC_CPU(cs);
2633 DeviceClass *dc = DEVICE_GET_CLASS(cs);
2634 int id = ppc_get_vcpu_dt_id(cpu);
2635 void *fdt;
2636 int offset, fdt_size;
2637 char *nodename;
2638
2639 fdt = create_device_tree(&fdt_size);
2640 nodename = g_strdup_printf("%s@%x", dc->fw_name, id);
2641 offset = fdt_add_subnode(fdt, 0, nodename);
2642
2643 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
2644 g_free(nodename);
2645
2646 *fdt_offset = offset;
2647 return fdt;
2648 }
2649
2650 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev,
2651 Error **errp)
2652 {
2653 MachineState *ms = MACHINE(qdev_get_machine());
2654 CPUCore *cc = CPU_CORE(dev);
2655 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL);
2656
2657 core_slot->cpu = NULL;
2658 object_unparent(OBJECT(dev));
2659 }
2660
2661 static void spapr_core_release(DeviceState *dev, void *opaque)
2662 {
2663 HotplugHandler *hotplug_ctrl;
2664
2665 hotplug_ctrl = qdev_get_hotplug_handler(dev);
2666 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort);
2667 }
2668
2669 static
2670 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev,
2671 Error **errp)
2672 {
2673 int index;
2674 sPAPRDRConnector *drc;
2675 sPAPRDRConnectorClass *drck;
2676 Error *local_err = NULL;
2677 CPUCore *cc = CPU_CORE(dev);
2678 int smt = kvmppc_smt_threads();
2679
2680 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) {
2681 error_setg(errp, "Unable to find CPU core with core-id: %d",
2682 cc->core_id);
2683 return;
2684 }
2685 if (index == 0) {
2686 error_setg(errp, "Boot CPU core may not be unplugged");
2687 return;
2688 }
2689
2690 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt);
2691 g_assert(drc);
2692
2693 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2694 drck->detach(drc, dev, spapr_core_release, NULL, &local_err);
2695 if (local_err) {
2696 error_propagate(errp, local_err);
2697 return;
2698 }
2699
2700 spapr_hotplug_req_remove_by_index(drc);
2701 }
2702
2703 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2704 Error **errp)
2705 {
2706 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
2707 MachineClass *mc = MACHINE_GET_CLASS(spapr);
2708 sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev));
2709 CPUCore *cc = CPU_CORE(dev);
2710 CPUState *cs = CPU(core->threads);
2711 sPAPRDRConnector *drc;
2712 Error *local_err = NULL;
2713 void *fdt = NULL;
2714 int fdt_offset = 0;
2715 int smt = kvmppc_smt_threads();
2716 CPUArchId *core_slot;
2717 int index;
2718
2719 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
2720 if (!core_slot) {
2721 error_setg(errp, "Unable to find CPU core with core-id: %d",
2722 cc->core_id);
2723 return;
2724 }
2725 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt);
2726
2727 g_assert(drc || !mc->has_hotpluggable_cpus);
2728
2729 /*
2730 * Setup CPU DT entries only for hotplugged CPUs. For boot time or
2731 * coldplugged CPUs DT entries are setup in spapr_build_fdt().
2732 */
2733 if (dev->hotplugged) {
2734 fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr);
2735 }
2736
2737 if (drc) {
2738 sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2739 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, &local_err);
2740 if (local_err) {
2741 g_free(fdt);
2742 error_propagate(errp, local_err);
2743 return;
2744 }
2745 }
2746
2747 if (dev->hotplugged) {
2748 /*
2749 * Send hotplug notification interrupt to the guest only in case
2750 * of hotplugged CPUs.
2751 */
2752 spapr_hotplug_req_add_by_index(drc);
2753 } else {
2754 /*
2755 * Set the right DRC states for cold plugged CPU.
2756 */
2757 if (drc) {
2758 sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2759 drck->set_allocation_state(drc, SPAPR_DR_ALLOCATION_STATE_USABLE);
2760 drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED);
2761 }
2762 }
2763 core_slot->cpu = OBJECT(dev);
2764 }
2765
2766 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2767 Error **errp)
2768 {
2769 MachineState *machine = MACHINE(OBJECT(hotplug_dev));
2770 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev);
2771 Error *local_err = NULL;
2772 CPUCore *cc = CPU_CORE(dev);
2773 char *base_core_type = spapr_get_cpu_core_type(machine->cpu_model);
2774 const char *type = object_get_typename(OBJECT(dev));
2775 CPUArchId *core_slot;
2776 int index;
2777
2778 if (dev->hotplugged && !mc->has_hotpluggable_cpus) {
2779 error_setg(&local_err, "CPU hotplug not supported for this machine");
2780 goto out;
2781 }
2782
2783 if (strcmp(base_core_type, type)) {
2784 error_setg(&local_err, "CPU core type should be %s", base_core_type);
2785 goto out;
2786 }
2787
2788 if (cc->core_id % smp_threads) {
2789 error_setg(&local_err, "invalid core id %d", cc->core_id);
2790 goto out;
2791 }
2792
2793 if (cc->nr_threads != smp_threads) {
2794 error_setg(errp, "invalid nr-threads %d, must be %d",
2795 cc->nr_threads, smp_threads);
2796 return;
2797 }
2798
2799 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
2800 if (!core_slot) {
2801 error_setg(&local_err, "core id %d out of range", cc->core_id);
2802 goto out;
2803 }
2804
2805 if (core_slot->cpu) {
2806 error_setg(&local_err, "core %d already populated", cc->core_id);
2807 goto out;
2808 }
2809
2810 out:
2811 g_free(base_core_type);
2812 error_propagate(errp, local_err);
2813 }
2814
2815 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev,
2816 DeviceState *dev, Error **errp)
2817 {
2818 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine());
2819
2820 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2821 int node;
2822
2823 if (!smc->dr_lmb_enabled) {
2824 error_setg(errp, "Memory hotplug not supported for this machine");
2825 return;
2826 }
2827 node = object_property_get_int(OBJECT(dev), PC_DIMM_NODE_PROP, errp);
2828 if (*errp) {
2829 return;
2830 }
2831 if (node < 0 || node >= MAX_NODES) {
2832 error_setg(errp, "Invaild node %d", node);
2833 return;
2834 }
2835
2836 /*
2837 * Currently PowerPC kernel doesn't allow hot-adding memory to
2838 * memory-less node, but instead will silently add the memory
2839 * to the first node that has some memory. This causes two
2840 * unexpected behaviours for the user.
2841 *
2842 * - Memory gets hotplugged to a different node than what the user
2843 * specified.
2844 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs
2845 * to memory-less node, a reboot will set things accordingly
2846 * and the previously hotplugged memory now ends in the right node.
2847 * This appears as if some memory moved from one node to another.
2848 *
2849 * So until kernel starts supporting memory hotplug to memory-less
2850 * nodes, just prevent such attempts upfront in QEMU.
2851 */
2852 if (nb_numa_nodes && !numa_info[node].node_mem) {
2853 error_setg(errp, "Can't hotplug memory to memory-less node %d",
2854 node);
2855 return;
2856 }
2857
2858 spapr_memory_plug(hotplug_dev, dev, node, errp);
2859 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2860 spapr_core_plug(hotplug_dev, dev, errp);
2861 }
2862 }
2863
2864 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev,
2865 DeviceState *dev, Error **errp)
2866 {
2867 sPAPRMachineState *sms = SPAPR_MACHINE(qdev_get_machine());
2868 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
2869
2870 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2871 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) {
2872 spapr_memory_unplug(hotplug_dev, dev, errp);
2873 } else {
2874 error_setg(errp, "Memory hot unplug not supported for this guest");
2875 }
2876 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2877 if (!mc->has_hotpluggable_cpus) {
2878 error_setg(errp, "CPU hot unplug not supported on this machine");
2879 return;
2880 }
2881 spapr_core_unplug(hotplug_dev, dev, errp);
2882 }
2883 }
2884
2885 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev,
2886 DeviceState *dev, Error **errp)
2887 {
2888 sPAPRMachineState *sms = SPAPR_MACHINE(qdev_get_machine());
2889 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
2890
2891 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2892 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) {
2893 spapr_memory_unplug_request(hotplug_dev, dev, errp);
2894 } else {
2895 /* NOTE: this means there is a window after guest reset, prior to
2896 * CAS negotiation, where unplug requests will fail due to the
2897 * capability not being detected yet. This is a bit different than
2898 * the case with PCI unplug, where the events will be queued and
2899 * eventually handled by the guest after boot
2900 */
2901 error_setg(errp, "Memory hot unplug not supported for this guest");
2902 }
2903 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2904 if (!mc->has_hotpluggable_cpus) {
2905 error_setg(errp, "CPU hot unplug not supported on this machine");
2906 return;
2907 }
2908 spapr_core_unplug_request(hotplug_dev, dev, errp);
2909 }
2910 }
2911
2912 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev,
2913 DeviceState *dev, Error **errp)
2914 {
2915 if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2916 spapr_core_pre_plug(hotplug_dev, dev, errp);
2917 }
2918 }
2919
2920 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine,
2921 DeviceState *dev)
2922 {
2923 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
2924 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2925 return HOTPLUG_HANDLER(machine);
2926 }
2927 return NULL;
2928 }
2929
2930 static unsigned spapr_cpu_index_to_socket_id(unsigned cpu_index)
2931 {
2932 /* Allocate to NUMA nodes on a "socket" basis (not that concept of
2933 * socket means much for the paravirtualized PAPR platform) */
2934 return cpu_index / smp_threads / smp_cores;
2935 }
2936
2937 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine)
2938 {
2939 int i;
2940 int spapr_max_cores = max_cpus / smp_threads;
2941 MachineClass *mc = MACHINE_GET_CLASS(machine);
2942
2943 if (!mc->has_hotpluggable_cpus) {
2944 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads;
2945 }
2946 if (machine->possible_cpus) {
2947 assert(machine->possible_cpus->len == spapr_max_cores);
2948 return machine->possible_cpus;
2949 }
2950
2951 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
2952 sizeof(CPUArchId) * spapr_max_cores);
2953 machine->possible_cpus->len = spapr_max_cores;
2954 for (i = 0; i < machine->possible_cpus->len; i++) {
2955 int core_id = i * smp_threads;
2956
2957 machine->possible_cpus->cpus[i].vcpus_count = smp_threads;
2958 machine->possible_cpus->cpus[i].arch_id = core_id;
2959 machine->possible_cpus->cpus[i].props.has_core_id = true;
2960 machine->possible_cpus->cpus[i].props.core_id = core_id;
2961 /* TODO: add 'has_node/node' here to describe
2962 to which node core belongs */
2963 }
2964 return machine->possible_cpus;
2965 }
2966
2967 static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index,
2968 uint64_t *buid, hwaddr *pio,
2969 hwaddr *mmio32, hwaddr *mmio64,
2970 unsigned n_dma, uint32_t *liobns, Error **errp)
2971 {
2972 /*
2973 * New-style PHB window placement.
2974 *
2975 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window
2976 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO
2977 * windows.
2978 *
2979 * Some guest kernels can't work with MMIO windows above 1<<46
2980 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB
2981 *
2982 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each
2983 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the
2984 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the
2985 * 1TiB 64-bit MMIO windows for each PHB.
2986 */
2987 const uint64_t base_buid = 0x800000020000000ULL;
2988 #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \
2989 SPAPR_PCI_MEM64_WIN_SIZE - 1)
2990 int i;
2991
2992 /* Sanity check natural alignments */
2993 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
2994 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
2995 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0);
2996 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0);
2997 /* Sanity check bounds */
2998 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) >
2999 SPAPR_PCI_MEM32_WIN_SIZE);
3000 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) >
3001 SPAPR_PCI_MEM64_WIN_SIZE);
3002
3003 if (index >= SPAPR_MAX_PHBS) {
3004 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)",
3005 SPAPR_MAX_PHBS - 1);
3006 return;
3007 }
3008
3009 *buid = base_buid + index;
3010 for (i = 0; i < n_dma; ++i) {
3011 liobns[i] = SPAPR_PCI_LIOBN(index, i);
3012 }
3013
3014 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE;
3015 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE;
3016 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE;
3017 }
3018
3019 static ICSState *spapr_ics_get(XICSFabric *dev, int irq)
3020 {
3021 sPAPRMachineState *spapr = SPAPR_MACHINE(dev);
3022
3023 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL;
3024 }
3025
3026 static void spapr_ics_resend(XICSFabric *dev)
3027 {
3028 sPAPRMachineState *spapr = SPAPR_MACHINE(dev);
3029
3030 ics_resend(spapr->ics);
3031 }
3032
3033 static ICPState *spapr_icp_get(XICSFabric *xi, int server)
3034 {
3035 sPAPRMachineState *spapr = SPAPR_MACHINE(xi);
3036
3037 return (server < spapr->nr_servers) ? &spapr->icps[server] : NULL;
3038 }
3039
3040 static void spapr_pic_print_info(InterruptStatsProvider *obj,
3041 Monitor *mon)
3042 {
3043 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
3044 int i;
3045
3046 for (i = 0; i < spapr->nr_servers; i++) {
3047 icp_pic_print_info(&spapr->icps[i], mon);
3048 }
3049
3050 ics_pic_print_info(spapr->ics, mon);
3051 }
3052
3053 static void spapr_machine_class_init(ObjectClass *oc, void *data)
3054 {
3055 MachineClass *mc = MACHINE_CLASS(oc);
3056 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc);
3057 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
3058 NMIClass *nc = NMI_CLASS(oc);
3059 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
3060 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc);
3061 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
3062 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
3063
3064 mc->desc = "pSeries Logical Partition (PAPR compliant)";
3065
3066 /*
3067 * We set up the default / latest behaviour here. The class_init
3068 * functions for the specific versioned machine types can override
3069 * these details for backwards compatibility
3070 */
3071 mc->init = ppc_spapr_init;
3072 mc->reset = ppc_spapr_reset;
3073 mc->block_default_type = IF_SCSI;
3074 mc->max_cpus = 1024;
3075 mc->no_parallel = 1;
3076 mc->default_boot_order = "";
3077 mc->default_ram_size = 512 * M_BYTE;
3078 mc->kvm_type = spapr_kvm_type;
3079 mc->has_dynamic_sysbus = true;
3080 mc->pci_allow_0_address = true;
3081 mc->get_hotplug_handler = spapr_get_hotplug_handler;
3082 hc->pre_plug = spapr_machine_device_pre_plug;
3083 hc->plug = spapr_machine_device_plug;
3084 hc->unplug = spapr_machine_device_unplug;
3085 mc->cpu_index_to_socket_id = spapr_cpu_index_to_socket_id;
3086 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids;
3087 hc->unplug_request = spapr_machine_device_unplug_request;
3088
3089 smc->dr_lmb_enabled = true;
3090 smc->tcg_default_cpu = "POWER8";
3091 mc->has_hotpluggable_cpus = true;
3092 fwc->get_dev_path = spapr_get_fw_dev_path;
3093 nc->nmi_monitor_handler = spapr_nmi;
3094 smc->phb_placement = spapr_phb_placement;
3095 vhc->hypercall = emulate_spapr_hypercall;
3096 vhc->hpt_mask = spapr_hpt_mask;
3097 vhc->map_hptes = spapr_map_hptes;
3098 vhc->unmap_hptes = spapr_unmap_hptes;
3099 vhc->store_hpte = spapr_store_hpte;
3100 vhc->get_patbe = spapr_get_patbe;
3101 xic->ics_get = spapr_ics_get;
3102 xic->ics_resend = spapr_ics_resend;
3103 xic->icp_get = spapr_icp_get;
3104 ispc->print_info = spapr_pic_print_info;
3105 /* Force NUMA node memory size to be a multiple of
3106 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity
3107 * in which LMBs are represented and hot-added
3108 */
3109 mc->numa_mem_align_shift = 28;
3110 }
3111
3112 static const TypeInfo spapr_machine_info = {
3113 .name = TYPE_SPAPR_MACHINE,
3114 .parent = TYPE_MACHINE,
3115 .abstract = true,
3116 .instance_size = sizeof(sPAPRMachineState),
3117 .instance_init = spapr_machine_initfn,
3118 .instance_finalize = spapr_machine_finalizefn,
3119 .class_size = sizeof(sPAPRMachineClass),
3120 .class_init = spapr_machine_class_init,
3121 .interfaces = (InterfaceInfo[]) {
3122 { TYPE_FW_PATH_PROVIDER },
3123 { TYPE_NMI },
3124 { TYPE_HOTPLUG_HANDLER },
3125 { TYPE_PPC_VIRTUAL_HYPERVISOR },
3126 { TYPE_XICS_FABRIC },
3127 { TYPE_INTERRUPT_STATS_PROVIDER },
3128 { }
3129 },
3130 };
3131
3132 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
3133 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
3134 void *data) \
3135 { \
3136 MachineClass *mc = MACHINE_CLASS(oc); \
3137 spapr_machine_##suffix##_class_options(mc); \
3138 if (latest) { \
3139 mc->alias = "pseries"; \
3140 mc->is_default = 1; \
3141 } \
3142 } \
3143 static void spapr_machine_##suffix##_instance_init(Object *obj) \
3144 { \
3145 MachineState *machine = MACHINE(obj); \
3146 spapr_machine_##suffix##_instance_options(machine); \
3147 } \
3148 static const TypeInfo spapr_machine_##suffix##_info = { \
3149 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
3150 .parent = TYPE_SPAPR_MACHINE, \
3151 .class_init = spapr_machine_##suffix##_class_init, \
3152 .instance_init = spapr_machine_##suffix##_instance_init, \
3153 }; \
3154 static void spapr_machine_register_##suffix(void) \
3155 { \
3156 type_register(&spapr_machine_##suffix##_info); \
3157 } \
3158 type_init(spapr_machine_register_##suffix)
3159
3160 /*
3161 * pseries-2.10
3162 */
3163 static void spapr_machine_2_10_instance_options(MachineState *machine)
3164 {
3165 }
3166
3167 static void spapr_machine_2_10_class_options(MachineClass *mc)
3168 {
3169 /* Defaults for the latest behaviour inherited from the base class */
3170 }
3171
3172 DEFINE_SPAPR_MACHINE(2_10, "2.10", true);
3173
3174 /*
3175 * pseries-2.9
3176 */
3177 #define SPAPR_COMPAT_2_9 \
3178 HW_COMPAT_2_9
3179
3180 static void spapr_machine_2_9_instance_options(MachineState *machine)
3181 {
3182 spapr_machine_2_10_instance_options(machine);
3183 }
3184
3185 static void spapr_machine_2_9_class_options(MachineClass *mc)
3186 {
3187 spapr_machine_2_10_class_options(mc);
3188 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_9);
3189 }
3190
3191 DEFINE_SPAPR_MACHINE(2_9, "2.9", false);
3192
3193 /*
3194 * pseries-2.8
3195 */
3196 #define SPAPR_COMPAT_2_8 \
3197 HW_COMPAT_2_8 \
3198 { \
3199 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
3200 .property = "pcie-extended-configuration-space", \
3201 .value = "off", \
3202 },
3203
3204 static void spapr_machine_2_8_instance_options(MachineState *machine)
3205 {
3206 spapr_machine_2_9_instance_options(machine);
3207 }
3208
3209 static void spapr_machine_2_8_class_options(MachineClass *mc)
3210 {
3211 spapr_machine_2_9_class_options(mc);
3212 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8);
3213 mc->numa_mem_align_shift = 23;
3214 }
3215
3216 DEFINE_SPAPR_MACHINE(2_8, "2.8", false);
3217
3218 /*
3219 * pseries-2.7
3220 */
3221 #define SPAPR_COMPAT_2_7 \
3222 HW_COMPAT_2_7 \
3223 { \
3224 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
3225 .property = "mem_win_size", \
3226 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\
3227 }, \
3228 { \
3229 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
3230 .property = "mem64_win_size", \
3231 .value = "0", \
3232 }, \
3233 { \
3234 .driver = TYPE_POWERPC_CPU, \
3235 .property = "pre-2.8-migration", \
3236 .value = "on", \
3237 }, \
3238 { \
3239 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
3240 .property = "pre-2.8-migration", \
3241 .value = "on", \
3242 },
3243
3244 static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index,
3245 uint64_t *buid, hwaddr *pio,
3246 hwaddr *mmio32, hwaddr *mmio64,
3247 unsigned n_dma, uint32_t *liobns, Error **errp)
3248 {
3249 /* Legacy PHB placement for pseries-2.7 and earlier machine types */
3250 const uint64_t base_buid = 0x800000020000000ULL;
3251 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */
3252 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */
3253 const hwaddr pio_offset = 0x80000000; /* 2 GiB */
3254 const uint32_t max_index = 255;
3255 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */
3256
3257 uint64_t ram_top = MACHINE(spapr)->ram_size;
3258 hwaddr phb0_base, phb_base;
3259 int i;
3260
3261 /* Do we have hotpluggable memory? */
3262 if (MACHINE(spapr)->maxram_size > ram_top) {
3263 /* Can't just use maxram_size, because there may be an
3264 * alignment gap between normal and hotpluggable memory
3265 * regions */
3266 ram_top = spapr->hotplug_memory.base +
3267 memory_region_size(&spapr->hotplug_memory.mr);
3268 }
3269
3270 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment);
3271
3272 if (index > max_index) {
3273 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)",
3274 max_index);
3275 return;
3276 }
3277
3278 *buid = base_buid + index;
3279 for (i = 0; i < n_dma; ++i) {
3280 liobns[i] = SPAPR_PCI_LIOBN(index, i);
3281 }
3282
3283 phb_base = phb0_base + index * phb_spacing;
3284 *pio = phb_base + pio_offset;
3285 *mmio32 = phb_base + mmio_offset;
3286 /*
3287 * We don't set the 64-bit MMIO window, relying on the PHB's
3288 * fallback behaviour of automatically splitting a large "32-bit"
3289 * window into contiguous 32-bit and 64-bit windows
3290 */
3291 }
3292
3293 static void spapr_machine_2_7_instance_options(MachineState *machine)
3294 {
3295 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
3296
3297 spapr_machine_2_8_instance_options(machine);
3298 spapr->use_hotplug_event_source = false;
3299 }
3300
3301 static void spapr_machine_2_7_class_options(MachineClass *mc)
3302 {
3303 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3304
3305 spapr_machine_2_8_class_options(mc);
3306 smc->tcg_default_cpu = "POWER7";
3307 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7);
3308 smc->phb_placement = phb_placement_2_7;
3309 }
3310
3311 DEFINE_SPAPR_MACHINE(2_7, "2.7", false);
3312
3313 /*
3314 * pseries-2.6
3315 */
3316 #define SPAPR_COMPAT_2_6 \
3317 HW_COMPAT_2_6 \
3318 { \