Merge remote-tracking branch 'remotes/jsnow-gitlab/tags/python-pull-request' into...
[qemu.git] / hw / ppc / spapr_cpu_core.c
1 /*
2 * sPAPR CPU core device, acts as container of CPU thread devices.
3 *
4 * Copyright (C) 2016 Bharata B Rao <bharata@linux.vnet.ibm.com>
5 *
6 * This work is licensed under the terms of the GNU GPL, version 2 or later.
7 * See the COPYING file in the top-level directory.
8 */
9
10 #include "qemu/osdep.h"
11 #include "hw/cpu/core.h"
12 #include "hw/ppc/spapr_cpu_core.h"
13 #include "hw/qdev-properties.h"
14 #include "migration/vmstate.h"
15 #include "target/ppc/cpu.h"
16 #include "hw/ppc/spapr.h"
17 #include "qapi/error.h"
18 #include "sysemu/cpus.h"
19 #include "sysemu/kvm.h"
20 #include "target/ppc/kvm_ppc.h"
21 #include "hw/ppc/ppc.h"
22 #include "target/ppc/mmu-hash64.h"
23 #include "target/ppc/power8-pmu.h"
24 #include "sysemu/numa.h"
25 #include "sysemu/reset.h"
26 #include "sysemu/hw_accel.h"
27 #include "qemu/error-report.h"
28
29 static void spapr_reset_vcpu(PowerPCCPU *cpu)
30 {
31 CPUState *cs = CPU(cpu);
32 CPUPPCState *env = &cpu->env;
33 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
34 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
35 target_ulong lpcr;
36 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
37
38 cpu_reset(cs);
39
40 env->spr[SPR_HIOR] = 0;
41
42 lpcr = env->spr[SPR_LPCR];
43
44 /* Set emulated LPCR to not send interrupts to hypervisor. Note that
45 * under KVM, the actual HW LPCR will be set differently by KVM itself,
46 * the settings below ensure proper operations with TCG in absence of
47 * a real hypervisor.
48 *
49 * Disable Power-saving mode Exit Cause exceptions for the CPU, so
50 * we don't get spurious wakups before an RTAS start-cpu call.
51 * For the same reason, set PSSCR_EC.
52 */
53 lpcr &= ~(LPCR_VPM1 | LPCR_ISL | LPCR_KBV | pcc->lpcr_pm);
54 lpcr |= LPCR_LPES0 | LPCR_LPES1;
55 env->spr[SPR_PSSCR] |= PSSCR_EC;
56
57 ppc_store_lpcr(cpu, lpcr);
58
59 /* Set a full AMOR so guest can use the AMR as it sees fit */
60 env->spr[SPR_AMOR] = 0xffffffffffffffffull;
61
62 spapr_cpu->vpa_addr = 0;
63 spapr_cpu->slb_shadow_addr = 0;
64 spapr_cpu->slb_shadow_size = 0;
65 spapr_cpu->dtl_addr = 0;
66 spapr_cpu->dtl_size = 0;
67
68 spapr_caps_cpu_apply(spapr, cpu);
69
70 kvm_check_mmu(cpu, &error_fatal);
71
72 spapr_irq_cpu_intc_reset(spapr, cpu);
73 }
74
75 void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip,
76 target_ulong r1, target_ulong r3,
77 target_ulong r4)
78 {
79 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
80 CPUPPCState *env = &cpu->env;
81
82 env->nip = nip;
83 env->gpr[1] = r1;
84 env->gpr[3] = r3;
85 env->gpr[4] = r4;
86 kvmppc_set_reg_ppc_online(cpu, 1);
87 CPU(cpu)->halted = 0;
88 /* Enable Power-saving mode Exit Cause exceptions */
89 ppc_store_lpcr(cpu, env->spr[SPR_LPCR] | pcc->lpcr_pm);
90 }
91
92 /*
93 * Return the sPAPR CPU core type for @model which essentially is the CPU
94 * model specified with -cpu cmdline option.
95 */
96 const char *spapr_get_cpu_core_type(const char *cpu_type)
97 {
98 int len = strlen(cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX);
99 char *core_type = g_strdup_printf(SPAPR_CPU_CORE_TYPE_NAME("%.*s"),
100 len, cpu_type);
101 ObjectClass *oc = object_class_by_name(core_type);
102
103 g_free(core_type);
104 if (!oc) {
105 return NULL;
106 }
107
108 return object_class_get_name(oc);
109 }
110
111 static bool slb_shadow_needed(void *opaque)
112 {
113 SpaprCpuState *spapr_cpu = opaque;
114
115 return spapr_cpu->slb_shadow_addr != 0;
116 }
117
118 static const VMStateDescription vmstate_spapr_cpu_slb_shadow = {
119 .name = "spapr_cpu/vpa/slb_shadow",
120 .version_id = 1,
121 .minimum_version_id = 1,
122 .needed = slb_shadow_needed,
123 .fields = (VMStateField[]) {
124 VMSTATE_UINT64(slb_shadow_addr, SpaprCpuState),
125 VMSTATE_UINT64(slb_shadow_size, SpaprCpuState),
126 VMSTATE_END_OF_LIST()
127 }
128 };
129
130 static bool dtl_needed(void *opaque)
131 {
132 SpaprCpuState *spapr_cpu = opaque;
133
134 return spapr_cpu->dtl_addr != 0;
135 }
136
137 static const VMStateDescription vmstate_spapr_cpu_dtl = {
138 .name = "spapr_cpu/vpa/dtl",
139 .version_id = 1,
140 .minimum_version_id = 1,
141 .needed = dtl_needed,
142 .fields = (VMStateField[]) {
143 VMSTATE_UINT64(dtl_addr, SpaprCpuState),
144 VMSTATE_UINT64(dtl_size, SpaprCpuState),
145 VMSTATE_END_OF_LIST()
146 }
147 };
148
149 static bool vpa_needed(void *opaque)
150 {
151 SpaprCpuState *spapr_cpu = opaque;
152
153 return spapr_cpu->vpa_addr != 0;
154 }
155
156 static const VMStateDescription vmstate_spapr_cpu_vpa = {
157 .name = "spapr_cpu/vpa",
158 .version_id = 1,
159 .minimum_version_id = 1,
160 .needed = vpa_needed,
161 .fields = (VMStateField[]) {
162 VMSTATE_UINT64(vpa_addr, SpaprCpuState),
163 VMSTATE_END_OF_LIST()
164 },
165 .subsections = (const VMStateDescription * []) {
166 &vmstate_spapr_cpu_slb_shadow,
167 &vmstate_spapr_cpu_dtl,
168 NULL
169 }
170 };
171
172 static const VMStateDescription vmstate_spapr_cpu_state = {
173 .name = "spapr_cpu",
174 .version_id = 1,
175 .minimum_version_id = 1,
176 .fields = (VMStateField[]) {
177 VMSTATE_END_OF_LIST()
178 },
179 .subsections = (const VMStateDescription * []) {
180 &vmstate_spapr_cpu_vpa,
181 NULL
182 }
183 };
184
185 static void spapr_unrealize_vcpu(PowerPCCPU *cpu, SpaprCpuCore *sc)
186 {
187 if (!sc->pre_3_0_migration) {
188 vmstate_unregister(NULL, &vmstate_spapr_cpu_state, cpu->machine_data);
189 }
190 spapr_irq_cpu_intc_destroy(SPAPR_MACHINE(qdev_get_machine()), cpu);
191 qdev_unrealize(DEVICE(cpu));
192 }
193
194 /*
195 * Called when CPUs are hot-plugged.
196 */
197 static void spapr_cpu_core_reset(DeviceState *dev)
198 {
199 CPUCore *cc = CPU_CORE(dev);
200 SpaprCpuCore *sc = SPAPR_CPU_CORE(dev);
201 int i;
202
203 for (i = 0; i < cc->nr_threads; i++) {
204 spapr_reset_vcpu(sc->threads[i]);
205 }
206 }
207
208 /*
209 * Called by the machine reset.
210 */
211 static void spapr_cpu_core_reset_handler(void *opaque)
212 {
213 spapr_cpu_core_reset(opaque);
214 }
215
216 static void spapr_delete_vcpu(PowerPCCPU *cpu)
217 {
218 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
219
220 cpu->machine_data = NULL;
221 g_free(spapr_cpu);
222 object_unparent(OBJECT(cpu));
223 }
224
225 static void spapr_cpu_core_unrealize(DeviceState *dev)
226 {
227 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
228 CPUCore *cc = CPU_CORE(dev);
229 int i;
230
231 for (i = 0; i < cc->nr_threads; i++) {
232 if (sc->threads[i]) {
233 /*
234 * Since this we can get here from the error path of
235 * spapr_cpu_core_realize(), make sure we only unrealize
236 * vCPUs that have already been realized.
237 */
238 if (object_property_get_bool(OBJECT(sc->threads[i]), "realized",
239 &error_abort)) {
240 spapr_unrealize_vcpu(sc->threads[i], sc);
241 }
242 spapr_delete_vcpu(sc->threads[i]);
243 }
244 }
245 g_free(sc->threads);
246 qemu_unregister_reset(spapr_cpu_core_reset_handler, sc);
247 }
248
249 static bool spapr_realize_vcpu(PowerPCCPU *cpu, SpaprMachineState *spapr,
250 SpaprCpuCore *sc, Error **errp)
251 {
252 CPUPPCState *env = &cpu->env;
253 CPUState *cs = CPU(cpu);
254
255 if (!qdev_realize(DEVICE(cpu), NULL, errp)) {
256 return false;
257 }
258
259 /* Set time-base frequency to 512 MHz */
260 cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ);
261
262 cpu_ppc_set_vhyp(cpu, PPC_VIRTUAL_HYPERVISOR(spapr));
263 kvmppc_set_papr(cpu);
264
265 if (spapr_irq_cpu_intc_create(spapr, cpu, errp) < 0) {
266 qdev_unrealize(DEVICE(cpu));
267 return false;
268 }
269
270 if (!sc->pre_3_0_migration) {
271 vmstate_register(NULL, cs->cpu_index, &vmstate_spapr_cpu_state,
272 cpu->machine_data);
273 }
274 return true;
275 }
276
277 static PowerPCCPU *spapr_create_vcpu(SpaprCpuCore *sc, int i, Error **errp)
278 {
279 SpaprCpuCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(sc);
280 CPUCore *cc = CPU_CORE(sc);
281 g_autoptr(Object) obj = NULL;
282 g_autofree char *id = NULL;
283 CPUState *cs;
284 PowerPCCPU *cpu;
285
286 obj = object_new(scc->cpu_type);
287
288 cs = CPU(obj);
289 cpu = POWERPC_CPU(obj);
290 /*
291 * All CPUs start halted. CPU0 is unhalted from the machine level reset code
292 * and the rest are explicitly started up by the guest using an RTAS call.
293 */
294 cs->start_powered_off = true;
295 cs->cpu_index = cc->core_id + i;
296 if (!spapr_set_vcpu_id(cpu, cs->cpu_index, errp)) {
297 return NULL;
298 }
299
300 cpu->node_id = sc->node_id;
301
302 id = g_strdup_printf("thread[%d]", i);
303 object_property_add_child(OBJECT(sc), id, obj);
304
305 cpu->machine_data = g_new0(SpaprCpuState, 1);
306
307 return cpu;
308 }
309
310 static void spapr_cpu_core_realize(DeviceState *dev, Error **errp)
311 {
312 /* We don't use SPAPR_MACHINE() in order to exit gracefully if the user
313 * tries to add a sPAPR CPU core to a non-pseries machine.
314 */
315 SpaprMachineState *spapr =
316 (SpaprMachineState *) object_dynamic_cast(qdev_get_machine(),
317 TYPE_SPAPR_MACHINE);
318 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
319 CPUCore *cc = CPU_CORE(OBJECT(dev));
320 int i;
321
322 if (!spapr) {
323 error_setg(errp, TYPE_SPAPR_CPU_CORE " needs a pseries machine");
324 return;
325 }
326
327 qemu_register_reset(spapr_cpu_core_reset_handler, sc);
328 sc->threads = g_new0(PowerPCCPU *, cc->nr_threads);
329 for (i = 0; i < cc->nr_threads; i++) {
330 sc->threads[i] = spapr_create_vcpu(sc, i, errp);
331 if (!sc->threads[i] ||
332 !spapr_realize_vcpu(sc->threads[i], spapr, sc, errp)) {
333 spapr_cpu_core_unrealize(dev);
334 return;
335 }
336 }
337 }
338
339 static Property spapr_cpu_core_properties[] = {
340 DEFINE_PROP_INT32("node-id", SpaprCpuCore, node_id, CPU_UNSET_NUMA_NODE_ID),
341 DEFINE_PROP_BOOL("pre-3.0-migration", SpaprCpuCore, pre_3_0_migration,
342 false),
343 DEFINE_PROP_END_OF_LIST()
344 };
345
346 static void spapr_cpu_core_class_init(ObjectClass *oc, void *data)
347 {
348 DeviceClass *dc = DEVICE_CLASS(oc);
349 SpaprCpuCoreClass *scc = SPAPR_CPU_CORE_CLASS(oc);
350
351 dc->realize = spapr_cpu_core_realize;
352 dc->unrealize = spapr_cpu_core_unrealize;
353 dc->reset = spapr_cpu_core_reset;
354 device_class_set_props(dc, spapr_cpu_core_properties);
355 scc->cpu_type = data;
356 }
357
358 #define DEFINE_SPAPR_CPU_CORE_TYPE(cpu_model) \
359 { \
360 .parent = TYPE_SPAPR_CPU_CORE, \
361 .class_data = (void *) POWERPC_CPU_TYPE_NAME(cpu_model), \
362 .class_init = spapr_cpu_core_class_init, \
363 .name = SPAPR_CPU_CORE_TYPE_NAME(cpu_model), \
364 }
365
366 static const TypeInfo spapr_cpu_core_type_infos[] = {
367 {
368 .name = TYPE_SPAPR_CPU_CORE,
369 .parent = TYPE_CPU_CORE,
370 .abstract = true,
371 .instance_size = sizeof(SpaprCpuCore),
372 .class_size = sizeof(SpaprCpuCoreClass),
373 },
374 DEFINE_SPAPR_CPU_CORE_TYPE("970_v2.2"),
375 DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.0"),
376 DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.1"),
377 DEFINE_SPAPR_CPU_CORE_TYPE("power5+_v2.1"),
378 DEFINE_SPAPR_CPU_CORE_TYPE("power7_v2.3"),
379 DEFINE_SPAPR_CPU_CORE_TYPE("power7+_v2.1"),
380 DEFINE_SPAPR_CPU_CORE_TYPE("power8_v2.0"),
381 DEFINE_SPAPR_CPU_CORE_TYPE("power8e_v2.1"),
382 DEFINE_SPAPR_CPU_CORE_TYPE("power8nvl_v1.0"),
383 DEFINE_SPAPR_CPU_CORE_TYPE("power9_v1.0"),
384 DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"),
385 DEFINE_SPAPR_CPU_CORE_TYPE("power10_v1.0"),
386 DEFINE_SPAPR_CPU_CORE_TYPE("power10_v2.0"),
387 #ifdef CONFIG_KVM
388 DEFINE_SPAPR_CPU_CORE_TYPE("host"),
389 #endif
390 };
391
392 DEFINE_TYPES(spapr_cpu_core_type_infos)