Merge tag 'net-pull-request' of https://github.com/jasowang/qemu into staging
[qemu.git] / hw / ppc / virtex_ml507.c
1 /*
2 * Model of Xilinx Virtex5 ML507 PPC-440 refdesign.
3 *
4 * Copyright (c) 2010 Edgar E. Iglesias.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/datadir.h"
27 #include "qemu/units.h"
28 #include "cpu.h"
29 #include "hw/sysbus.h"
30 #include "hw/char/serial.h"
31 #include "hw/block/flash.h"
32 #include "sysemu/sysemu.h"
33 #include "sysemu/reset.h"
34 #include "hw/boards.h"
35 #include "sysemu/device_tree.h"
36 #include "hw/loader.h"
37 #include "elf.h"
38 #include "qapi/error.h"
39 #include "qemu/error-report.h"
40 #include "qemu/option.h"
41
42 #include "hw/intc/ppc-uic.h"
43 #include "hw/ppc/ppc.h"
44 #include "hw/ppc/ppc4xx.h"
45 #include "hw/qdev-properties.h"
46 #include "ppc405.h"
47
48 #define EPAPR_MAGIC (0x45504150)
49 #define FLASH_SIZE (16 * MiB)
50
51 #define INTC_BASEADDR 0x81800000
52 #define UART16550_BASEADDR 0x83e01003
53 #define TIMER_BASEADDR 0x83c00000
54 #define PFLASH_BASEADDR 0xfc000000
55
56 #define TIMER_IRQ 3
57 #define UART16550_IRQ 9
58
59 static struct boot_info
60 {
61 uint32_t bootstrap_pc;
62 uint32_t cmdline;
63 uint32_t fdt;
64 uint32_t ima_size;
65 void *vfdt;
66 } boot_info;
67
68 /* Create reset TLB entries for BookE, spanning the 32bit addr space. */
69 static void mmubooke_create_initial_mapping(CPUPPCState *env,
70 target_ulong va,
71 hwaddr pa)
72 {
73 ppcemb_tlb_t *tlb = &env->tlb.tlbe[0];
74
75 tlb->attr = 0;
76 tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
77 tlb->size = 1U << 31; /* up to 0x80000000 */
78 tlb->EPN = va & TARGET_PAGE_MASK;
79 tlb->RPN = pa & TARGET_PAGE_MASK;
80 tlb->PID = 0;
81
82 tlb = &env->tlb.tlbe[1];
83 tlb->attr = 0;
84 tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
85 tlb->size = 1U << 31; /* up to 0xffffffff */
86 tlb->EPN = 0x80000000 & TARGET_PAGE_MASK;
87 tlb->RPN = 0x80000000 & TARGET_PAGE_MASK;
88 tlb->PID = 0;
89 }
90
91 static PowerPCCPU *ppc440_init_xilinx(const char *cpu_type, uint32_t sysclk)
92 {
93 PowerPCCPU *cpu;
94 CPUPPCState *env;
95 DeviceState *uicdev;
96 SysBusDevice *uicsbd;
97
98 cpu = POWERPC_CPU(cpu_create(cpu_type));
99 env = &cpu->env;
100
101 ppc_booke_timers_init(cpu, sysclk, 0/* no flags */);
102
103 ppc_dcr_init(env, NULL, NULL);
104
105 /* interrupt controller */
106 uicdev = qdev_new(TYPE_PPC_UIC);
107 uicsbd = SYS_BUS_DEVICE(uicdev);
108
109 object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(cpu),
110 &error_fatal);
111 sysbus_realize_and_unref(uicsbd, &error_fatal);
112
113 sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT,
114 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]);
115 sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT,
116 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]);
117
118 /* This board doesn't wire anything up to the inputs of the UIC. */
119 return cpu;
120 }
121
122 static void main_cpu_reset(void *opaque)
123 {
124 PowerPCCPU *cpu = opaque;
125 CPUPPCState *env = &cpu->env;
126 struct boot_info *bi = env->load_info;
127
128 cpu_reset(CPU(cpu));
129 /* Linux Kernel Parameters (passing device tree):
130 * r3: pointer to the fdt
131 * r4: 0
132 * r5: 0
133 * r6: epapr magic
134 * r7: size of IMA in bytes
135 * r8: 0
136 * r9: 0
137 */
138 env->gpr[1] = (16 * MiB) - 8;
139 /* Provide a device-tree. */
140 env->gpr[3] = bi->fdt;
141 env->nip = bi->bootstrap_pc;
142
143 /* Create a mapping for the kernel. */
144 mmubooke_create_initial_mapping(env, 0, 0);
145 env->gpr[6] = tswap32(EPAPR_MAGIC);
146 env->gpr[7] = bi->ima_size;
147 }
148
149 #define BINARY_DEVICE_TREE_FILE "virtex-ml507.dtb"
150 static int xilinx_load_device_tree(hwaddr addr,
151 uint32_t ramsize,
152 hwaddr initrd_base,
153 hwaddr initrd_size,
154 const char *kernel_cmdline)
155 {
156 char *path;
157 int fdt_size;
158 void *fdt = NULL;
159 int r;
160 const char *dtb_filename;
161
162 dtb_filename = current_machine->dtb;
163 if (dtb_filename) {
164 fdt = load_device_tree(dtb_filename, &fdt_size);
165 if (!fdt) {
166 error_report("Error while loading device tree file '%s'",
167 dtb_filename);
168 }
169 } else {
170 /* Try the local "ppc.dtb" override. */
171 fdt = load_device_tree("ppc.dtb", &fdt_size);
172 if (!fdt) {
173 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE);
174 if (path) {
175 fdt = load_device_tree(path, &fdt_size);
176 g_free(path);
177 }
178 }
179 }
180 if (!fdt) {
181 return 0;
182 }
183
184 r = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
185 initrd_base);
186 if (r < 0) {
187 error_report("couldn't set /chosen/linux,initrd-start");
188 }
189
190 r = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
191 (initrd_base + initrd_size));
192 if (r < 0) {
193 error_report("couldn't set /chosen/linux,initrd-end");
194 }
195
196 r = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", kernel_cmdline);
197 if (r < 0)
198 fprintf(stderr, "couldn't set /chosen/bootargs\n");
199 cpu_physical_memory_write(addr, fdt, fdt_size);
200 g_free(fdt);
201 return fdt_size;
202 }
203
204 static void virtex_init(MachineState *machine)
205 {
206 const char *kernel_filename = machine->kernel_filename;
207 const char *kernel_cmdline = machine->kernel_cmdline;
208 hwaddr initrd_base = 0;
209 int initrd_size = 0;
210 MemoryRegion *address_space_mem = get_system_memory();
211 DeviceState *dev;
212 PowerPCCPU *cpu;
213 CPUPPCState *env;
214 hwaddr ram_base = 0;
215 DriveInfo *dinfo;
216 qemu_irq irq[32], *cpu_irq;
217 int kernel_size;
218 int i;
219
220 /* init CPUs */
221 cpu = ppc440_init_xilinx(machine->cpu_type, 400000000);
222 env = &cpu->env;
223
224 if (env->mmu_model != POWERPC_MMU_BOOKE) {
225 error_report("MMU model %i not supported by this machine",
226 env->mmu_model);
227 exit(1);
228 }
229
230 qemu_register_reset(main_cpu_reset, cpu);
231
232 memory_region_add_subregion(address_space_mem, ram_base, machine->ram);
233
234 dinfo = drive_get(IF_PFLASH, 0, 0);
235 pflash_cfi01_register(PFLASH_BASEADDR, "virtex.flash", FLASH_SIZE,
236 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
237 64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1);
238
239 cpu_irq = (qemu_irq *) &env->irq_inputs[PPC40x_INPUT_INT];
240 dev = qdev_new("xlnx.xps-intc");
241 qdev_prop_set_uint32(dev, "kind-of-intr", 0);
242 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
243 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);
244 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irq[0]);
245 for (i = 0; i < 32; i++) {
246 irq[i] = qdev_get_gpio_in(dev, i);
247 }
248
249 serial_mm_init(address_space_mem, UART16550_BASEADDR, 2, irq[UART16550_IRQ],
250 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN);
251
252 /* 2 timers at irq 2 @ 62 Mhz. */
253 dev = qdev_new("xlnx.xps-timer");
254 qdev_prop_set_uint32(dev, "one-timer-only", 0);
255 qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000);
256 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
257 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR);
258 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]);
259
260 if (kernel_filename) {
261 uint64_t entry, high;
262 hwaddr boot_offset;
263
264 /* Boots a kernel elf binary. */
265 kernel_size = load_elf(kernel_filename, NULL, NULL, NULL,
266 &entry, NULL, &high, NULL, 1, PPC_ELF_MACHINE,
267 0, 0);
268 boot_info.bootstrap_pc = entry & 0x00ffffff;
269
270 if (kernel_size < 0) {
271 boot_offset = 0x1200000;
272 /* If we failed loading ELF's try a raw image. */
273 kernel_size = load_image_targphys(kernel_filename,
274 boot_offset,
275 machine->ram_size);
276 boot_info.bootstrap_pc = boot_offset;
277 high = boot_info.bootstrap_pc + kernel_size + 8192;
278 }
279
280 boot_info.ima_size = kernel_size;
281
282 /* Load initrd. */
283 if (machine->initrd_filename) {
284 initrd_base = high = ROUND_UP(high, 4);
285 initrd_size = load_image_targphys(machine->initrd_filename,
286 high, machine->ram_size - high);
287
288 if (initrd_size < 0) {
289 error_report("couldn't load ram disk '%s'",
290 machine->initrd_filename);
291 exit(1);
292 }
293 high = ROUND_UP(high + initrd_size, 4);
294 }
295
296 /* Provide a device-tree. */
297 boot_info.fdt = high + (8192 * 2);
298 boot_info.fdt &= ~8191;
299
300 xilinx_load_device_tree(boot_info.fdt, machine->ram_size,
301 initrd_base, initrd_size,
302 kernel_cmdline);
303 }
304 env->load_info = &boot_info;
305 }
306
307 static void virtex_machine_init(MachineClass *mc)
308 {
309 mc->desc = "Xilinx Virtex ML507 reference design";
310 mc->init = virtex_init;
311 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("440-xilinx");
312 mc->default_ram_id = "ram";
313 }
314
315 DEFINE_MACHINE("virtex-ml507", virtex_machine_init)