PPC: e500mc: add missing IVORs to bitmap
[qemu.git] / hw / ppc4xx_pci.c
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, see <http://www.gnu.org/licenses/>.
13 *
14 * Copyright IBM Corp. 2008
15 *
16 * Authors: Hollis Blanchard <hollisb@us.ibm.com>
17 */
18
19 /* This file implements emulation of the 32-bit PCI controller found in some
20 * 4xx SoCs, such as the 440EP. */
21
22 #include "hw.h"
23 #include "ppc.h"
24 #include "ppc4xx.h"
25 #include "pci.h"
26 #include "pci_host.h"
27 #include "exec-memory.h"
28
29 #undef DEBUG
30 #ifdef DEBUG
31 #define DPRINTF(fmt, ...) do { printf(fmt, ## __VA_ARGS__); } while (0)
32 #else
33 #define DPRINTF(fmt, ...)
34 #endif /* DEBUG */
35
36 struct PCIMasterMap {
37 uint32_t la;
38 uint32_t ma;
39 uint32_t pcila;
40 uint32_t pciha;
41 };
42
43 struct PCITargetMap {
44 uint32_t ms;
45 uint32_t la;
46 };
47
48 #define PPC4xx_PCI_NR_PMMS 3
49 #define PPC4xx_PCI_NR_PTMS 2
50
51 struct PPC4xxPCIState {
52 PCIHostState pci_state;
53
54 struct PCIMasterMap pmm[PPC4xx_PCI_NR_PMMS];
55 struct PCITargetMap ptm[PPC4xx_PCI_NR_PTMS];
56 qemu_irq irq[4];
57
58 MemoryRegion container;
59 MemoryRegion iomem;
60 };
61 typedef struct PPC4xxPCIState PPC4xxPCIState;
62
63 #define PCIC0_CFGADDR 0x0
64 #define PCIC0_CFGDATA 0x4
65
66 /* PLB Memory Map (PMM) registers specify which PLB addresses are translated to
67 * PCI accesses. */
68 #define PCIL0_PMM0LA 0x0
69 #define PCIL0_PMM0MA 0x4
70 #define PCIL0_PMM0PCILA 0x8
71 #define PCIL0_PMM0PCIHA 0xc
72 #define PCIL0_PMM1LA 0x10
73 #define PCIL0_PMM1MA 0x14
74 #define PCIL0_PMM1PCILA 0x18
75 #define PCIL0_PMM1PCIHA 0x1c
76 #define PCIL0_PMM2LA 0x20
77 #define PCIL0_PMM2MA 0x24
78 #define PCIL0_PMM2PCILA 0x28
79 #define PCIL0_PMM2PCIHA 0x2c
80
81 /* PCI Target Map (PTM) registers specify which PCI addresses are translated to
82 * PLB accesses. */
83 #define PCIL0_PTM1MS 0x30
84 #define PCIL0_PTM1LA 0x34
85 #define PCIL0_PTM2MS 0x38
86 #define PCIL0_PTM2LA 0x3c
87 #define PCI_REG_BASE 0x800000
88 #define PCI_REG_SIZE 0x40
89
90 #define PCI_ALL_SIZE (PCI_REG_BASE + PCI_REG_SIZE)
91
92 static uint64_t pci4xx_cfgaddr_read(void *opaque, target_phys_addr_t addr,
93 unsigned size)
94 {
95 PPC4xxPCIState *ppc4xx_pci = opaque;
96
97 return ppc4xx_pci->pci_state.config_reg;
98 }
99
100 static void pci4xx_cfgaddr_write(void *opaque, target_phys_addr_t addr,
101 uint64_t value, unsigned size)
102 {
103 PPC4xxPCIState *ppc4xx_pci = opaque;
104
105 ppc4xx_pci->pci_state.config_reg = value & ~0x3;
106 }
107
108 static const MemoryRegionOps pci4xx_cfgaddr_ops = {
109 .read = pci4xx_cfgaddr_read,
110 .write = pci4xx_cfgaddr_write,
111 .endianness = DEVICE_LITTLE_ENDIAN,
112 };
113
114 static void ppc4xx_pci_reg_write4(void *opaque, target_phys_addr_t offset,
115 uint64_t value, unsigned size)
116 {
117 struct PPC4xxPCIState *pci = opaque;
118
119 /* We ignore all target attempts at PCI configuration, effectively
120 * assuming a bidirectional 1:1 mapping of PLB and PCI space. */
121
122 switch (offset) {
123 case PCIL0_PMM0LA:
124 pci->pmm[0].la = value;
125 break;
126 case PCIL0_PMM0MA:
127 pci->pmm[0].ma = value;
128 break;
129 case PCIL0_PMM0PCIHA:
130 pci->pmm[0].pciha = value;
131 break;
132 case PCIL0_PMM0PCILA:
133 pci->pmm[0].pcila = value;
134 break;
135
136 case PCIL0_PMM1LA:
137 pci->pmm[1].la = value;
138 break;
139 case PCIL0_PMM1MA:
140 pci->pmm[1].ma = value;
141 break;
142 case PCIL0_PMM1PCIHA:
143 pci->pmm[1].pciha = value;
144 break;
145 case PCIL0_PMM1PCILA:
146 pci->pmm[1].pcila = value;
147 break;
148
149 case PCIL0_PMM2LA:
150 pci->pmm[2].la = value;
151 break;
152 case PCIL0_PMM2MA:
153 pci->pmm[2].ma = value;
154 break;
155 case PCIL0_PMM2PCIHA:
156 pci->pmm[2].pciha = value;
157 break;
158 case PCIL0_PMM2PCILA:
159 pci->pmm[2].pcila = value;
160 break;
161
162 case PCIL0_PTM1MS:
163 pci->ptm[0].ms = value;
164 break;
165 case PCIL0_PTM1LA:
166 pci->ptm[0].la = value;
167 break;
168 case PCIL0_PTM2MS:
169 pci->ptm[1].ms = value;
170 break;
171 case PCIL0_PTM2LA:
172 pci->ptm[1].la = value;
173 break;
174
175 default:
176 printf("%s: unhandled PCI internal register 0x%lx\n", __func__,
177 (unsigned long)offset);
178 break;
179 }
180 }
181
182 static uint64_t ppc4xx_pci_reg_read4(void *opaque, target_phys_addr_t offset,
183 unsigned size)
184 {
185 struct PPC4xxPCIState *pci = opaque;
186 uint32_t value;
187
188 switch (offset) {
189 case PCIL0_PMM0LA:
190 value = pci->pmm[0].la;
191 break;
192 case PCIL0_PMM0MA:
193 value = pci->pmm[0].ma;
194 break;
195 case PCIL0_PMM0PCIHA:
196 value = pci->pmm[0].pciha;
197 break;
198 case PCIL0_PMM0PCILA:
199 value = pci->pmm[0].pcila;
200 break;
201
202 case PCIL0_PMM1LA:
203 value = pci->pmm[1].la;
204 break;
205 case PCIL0_PMM1MA:
206 value = pci->pmm[1].ma;
207 break;
208 case PCIL0_PMM1PCIHA:
209 value = pci->pmm[1].pciha;
210 break;
211 case PCIL0_PMM1PCILA:
212 value = pci->pmm[1].pcila;
213 break;
214
215 case PCIL0_PMM2LA:
216 value = pci->pmm[2].la;
217 break;
218 case PCIL0_PMM2MA:
219 value = pci->pmm[2].ma;
220 break;
221 case PCIL0_PMM2PCIHA:
222 value = pci->pmm[2].pciha;
223 break;
224 case PCIL0_PMM2PCILA:
225 value = pci->pmm[2].pcila;
226 break;
227
228 case PCIL0_PTM1MS:
229 value = pci->ptm[0].ms;
230 break;
231 case PCIL0_PTM1LA:
232 value = pci->ptm[0].la;
233 break;
234 case PCIL0_PTM2MS:
235 value = pci->ptm[1].ms;
236 break;
237 case PCIL0_PTM2LA:
238 value = pci->ptm[1].la;
239 break;
240
241 default:
242 printf("%s: invalid PCI internal register 0x%lx\n", __func__,
243 (unsigned long)offset);
244 value = 0;
245 }
246
247 return value;
248 }
249
250 static const MemoryRegionOps pci_reg_ops = {
251 .read = ppc4xx_pci_reg_read4,
252 .write = ppc4xx_pci_reg_write4,
253 .endianness = DEVICE_LITTLE_ENDIAN,
254 };
255
256 static void ppc4xx_pci_reset(void *opaque)
257 {
258 struct PPC4xxPCIState *pci = opaque;
259
260 memset(pci->pmm, 0, sizeof(pci->pmm));
261 memset(pci->ptm, 0, sizeof(pci->ptm));
262 }
263
264 /* On Bamboo, all pins from each slot are tied to a single board IRQ. This
265 * may need further refactoring for other boards. */
266 static int ppc4xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
267 {
268 int slot = pci_dev->devfn >> 3;
269
270 DPRINTF("%s: devfn %x irq %d -> %d\n", __func__,
271 pci_dev->devfn, irq_num, slot);
272
273 return slot - 1;
274 }
275
276 static void ppc4xx_pci_set_irq(void *opaque, int irq_num, int level)
277 {
278 qemu_irq *pci_irqs = opaque;
279
280 DPRINTF("%s: PCI irq %d\n", __func__, irq_num);
281 if (irq_num < 0) {
282 fprintf(stderr, "%s: PCI irq %d\n", __func__, irq_num);
283 return;
284 }
285 qemu_set_irq(pci_irqs[irq_num], level);
286 }
287
288 static const VMStateDescription vmstate_pci_master_map = {
289 .name = "pci_master_map",
290 .version_id = 0,
291 .minimum_version_id = 0,
292 .minimum_version_id_old = 0,
293 .fields = (VMStateField[]) {
294 VMSTATE_UINT32(la, struct PCIMasterMap),
295 VMSTATE_UINT32(ma, struct PCIMasterMap),
296 VMSTATE_UINT32(pcila, struct PCIMasterMap),
297 VMSTATE_UINT32(pciha, struct PCIMasterMap),
298 VMSTATE_END_OF_LIST()
299 }
300 };
301
302 static const VMStateDescription vmstate_pci_target_map = {
303 .name = "pci_target_map",
304 .version_id = 0,
305 .minimum_version_id = 0,
306 .minimum_version_id_old = 0,
307 .fields = (VMStateField[]) {
308 VMSTATE_UINT32(ms, struct PCITargetMap),
309 VMSTATE_UINT32(la, struct PCITargetMap),
310 VMSTATE_END_OF_LIST()
311 }
312 };
313
314 static const VMStateDescription vmstate_ppc4xx_pci = {
315 .name = "ppc4xx_pci",
316 .version_id = 1,
317 .minimum_version_id = 1,
318 .minimum_version_id_old = 1,
319 .fields = (VMStateField[]) {
320 VMSTATE_STRUCT_ARRAY(pmm, PPC4xxPCIState, PPC4xx_PCI_NR_PMMS, 1,
321 vmstate_pci_master_map,
322 struct PCIMasterMap),
323 VMSTATE_STRUCT_ARRAY(ptm, PPC4xxPCIState, PPC4xx_PCI_NR_PTMS, 1,
324 vmstate_pci_target_map,
325 struct PCITargetMap),
326 VMSTATE_END_OF_LIST()
327 }
328 };
329
330 /* XXX Interrupt acknowledge cycles not supported. */
331 static int ppc4xx_pcihost_initfn(SysBusDevice *dev)
332 {
333 PPC4xxPCIState *s;
334 PCIHostState *h;
335 PCIBus *b;
336 int i;
337
338 h = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev));
339 s = DO_UPCAST(PPC4xxPCIState, pci_state, h);
340
341 for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
342 sysbus_init_irq(dev, &s->irq[i]);
343 }
344
345 b = pci_register_bus(&s->pci_state.busdev.qdev, NULL, ppc4xx_pci_set_irq,
346 ppc4xx_pci_map_irq, s->irq, get_system_memory(),
347 get_system_io(), 0, 4);
348 s->pci_state.bus = b;
349
350 pci_create_simple(b, 0, "ppc4xx-host-bridge");
351
352 /* XXX split into 2 memory regions, one for config space, one for regs */
353 memory_region_init(&s->container, "pci-container", PCI_ALL_SIZE);
354 memory_region_init_io(&h->conf_mem, &pci_host_conf_le_ops, h,
355 "pci-conf-idx", 4);
356 memory_region_init_io(&h->data_mem, &pci_host_data_le_ops, h,
357 "pci-conf-data", 4);
358 memory_region_init_io(&s->iomem, &pci_reg_ops, s,
359 "pci.reg", PCI_REG_SIZE);
360 memory_region_add_subregion(&s->container, PCIC0_CFGADDR, &h->conf_mem);
361 memory_region_add_subregion(&s->container, PCIC0_CFGDATA, &h->data_mem);
362 memory_region_add_subregion(&s->container, PCI_REG_BASE, &s->iomem);
363 sysbus_init_mmio(dev, &s->container);
364 qemu_register_reset(ppc4xx_pci_reset, s);
365
366 return 0;
367 }
368
369 static void ppc4xx_host_bridge_class_init(ObjectClass *klass, void *data)
370 {
371 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
372
373 k->vendor_id = PCI_VENDOR_ID_IBM;
374 k->device_id = PCI_DEVICE_ID_IBM_440GX;
375 k->class_id = PCI_CLASS_BRIDGE_OTHER;
376 }
377
378 static DeviceInfo ppc4xx_host_bridge_info = {
379 .name = "ppc4xx-host-bridge",
380 .desc = "Host bridge",
381 .size = sizeof(PCIDevice),
382 .class_init = ppc4xx_host_bridge_class_init,
383 };
384
385 static void ppc4xx_pcihost_class_init(ObjectClass *klass, void *data)
386 {
387 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
388
389 k->init = ppc4xx_pcihost_initfn;
390 }
391
392 static DeviceInfo ppc4xx_pcihost_info = {
393 .name = "ppc4xx-pcihost",
394 .size = sizeof(PPC4xxPCIState),
395 .vmsd = &vmstate_ppc4xx_pci,
396 .class_init = ppc4xx_pcihost_class_init,
397 };
398
399 static void ppc4xx_pci_register(void)
400 {
401 sysbus_register_withprop(&ppc4xx_pcihost_info);
402 pci_qdev_register(&ppc4xx_host_bridge_info);
403 }
404 device_init(ppc4xx_pci_register);