PPC: e500: msync is 440 only, e500 has real sync
[qemu.git] / hw / ppc_booke.c
1 /*
2 * QEMU PowerPC Booke hardware System Emulator
3 *
4 * Copyright (c) 2011 AdaCore
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "ppc.h"
26 #include "qemu-timer.h"
27 #include "sysemu.h"
28 #include "nvram.h"
29 #include "qemu-log.h"
30 #include "loader.h"
31
32
33 /* Timer Control Register */
34
35 #define TCR_WP_SHIFT 30 /* Watchdog Timer Period */
36 #define TCR_WP_MASK (0x3 << TCR_WP_SHIFT)
37 #define TCR_WRC_SHIFT 28 /* Watchdog Timer Reset Control */
38 #define TCR_WRC_MASK (0x3 << TCR_WRC_SHIFT)
39 #define TCR_WIE (1 << 27) /* Watchdog Timer Interrupt Enable */
40 #define TCR_DIE (1 << 26) /* Decrementer Interrupt Enable */
41 #define TCR_FP_SHIFT 24 /* Fixed-Interval Timer Period */
42 #define TCR_FP_MASK (0x3 << TCR_FP_SHIFT)
43 #define TCR_FIE (1 << 23) /* Fixed-Interval Timer Interrupt Enable */
44 #define TCR_ARE (1 << 22) /* Auto-Reload Enable */
45
46 /* Timer Control Register (e500 specific fields) */
47
48 #define TCR_E500_FPEXT_SHIFT 13 /* Fixed-Interval Timer Period Extension */
49 #define TCR_E500_FPEXT_MASK (0xf << TCR_E500_FPEXT_SHIFT)
50 #define TCR_E500_WPEXT_SHIFT 17 /* Watchdog Timer Period Extension */
51 #define TCR_E500_WPEXT_MASK (0xf << TCR_E500_WPEXT_SHIFT)
52
53 /* Timer Status Register */
54
55 #define TSR_FIS (1 << 26) /* Fixed-Interval Timer Interrupt Status */
56 #define TSR_DIS (1 << 27) /* Decrementer Interrupt Status */
57 #define TSR_WRS_SHIFT 28 /* Watchdog Timer Reset Status */
58 #define TSR_WRS_MASK (0x3 << TSR_WRS_SHIFT)
59 #define TSR_WIS (1 << 30) /* Watchdog Timer Interrupt Status */
60 #define TSR_ENW (1 << 31) /* Enable Next Watchdog Timer */
61
62 typedef struct booke_timer_t booke_timer_t;
63 struct booke_timer_t {
64
65 uint64_t fit_next;
66 struct QEMUTimer *fit_timer;
67
68 uint64_t wdt_next;
69 struct QEMUTimer *wdt_timer;
70
71 uint32_t flags;
72 };
73
74 static void booke_update_irq(CPUState *env)
75 {
76 ppc_set_irq(env, PPC_INTERRUPT_DECR,
77 (env->spr[SPR_BOOKE_TSR] & TSR_DIS
78 && env->spr[SPR_BOOKE_TCR] & TCR_DIE));
79
80 ppc_set_irq(env, PPC_INTERRUPT_WDT,
81 (env->spr[SPR_BOOKE_TSR] & TSR_WIS
82 && env->spr[SPR_BOOKE_TCR] & TCR_WIE));
83
84 ppc_set_irq(env, PPC_INTERRUPT_FIT,
85 (env->spr[SPR_BOOKE_TSR] & TSR_FIS
86 && env->spr[SPR_BOOKE_TCR] & TCR_FIE));
87 }
88
89 /* Return the location of the bit of time base at which the FIT will raise an
90 interrupt */
91 static uint8_t booke_get_fit_target(CPUState *env, ppc_tb_t *tb_env)
92 {
93 uint8_t fp = (env->spr[SPR_BOOKE_TCR] & TCR_FP_MASK) >> TCR_FP_SHIFT;
94
95 if (tb_env->flags & PPC_TIMER_E500) {
96 /* e500 Fixed-interval timer period extension */
97 uint32_t fpext = (env->spr[SPR_BOOKE_TCR] & TCR_E500_FPEXT_MASK)
98 >> TCR_E500_FPEXT_SHIFT;
99 fp = 63 - (fp | fpext << 2);
100 } else {
101 fp = env->fit_period[fp];
102 }
103
104 return fp;
105 }
106
107 /* Return the location of the bit of time base at which the WDT will raise an
108 interrupt */
109 static uint8_t booke_get_wdt_target(CPUState *env, ppc_tb_t *tb_env)
110 {
111 uint8_t wp = (env->spr[SPR_BOOKE_TCR] & TCR_WP_MASK) >> TCR_WP_SHIFT;
112
113 if (tb_env->flags & PPC_TIMER_E500) {
114 /* e500 Watchdog timer period extension */
115 uint32_t wpext = (env->spr[SPR_BOOKE_TCR] & TCR_E500_WPEXT_MASK)
116 >> TCR_E500_WPEXT_SHIFT;
117 wp = 63 - (wp | wpext << 2);
118 } else {
119 wp = env->wdt_period[wp];
120 }
121
122 return wp;
123 }
124
125 static void booke_update_fixed_timer(CPUState *env,
126 uint8_t target_bit,
127 uint64_t *next,
128 struct QEMUTimer *timer)
129 {
130 ppc_tb_t *tb_env = env->tb_env;
131 uint64_t lapse;
132 uint64_t tb;
133 uint64_t period = 1 << (target_bit + 1);
134 uint64_t now;
135
136 now = qemu_get_clock_ns(vm_clock);
137 tb = cpu_ppc_get_tb(tb_env, now, tb_env->tb_offset);
138
139 lapse = period - ((tb - (1 << target_bit)) & (period - 1));
140
141 *next = now + muldiv64(lapse, get_ticks_per_sec(), tb_env->tb_freq);
142
143 /* XXX: If expire time is now. We can't run the callback because we don't
144 * have access to it. So we just set the timer one nanosecond later.
145 */
146
147 if (*next == now) {
148 (*next)++;
149 }
150
151 qemu_mod_timer(timer, *next);
152 }
153
154 static void booke_decr_cb(void *opaque)
155 {
156 CPUState *env = opaque;
157
158 env->spr[SPR_BOOKE_TSR] |= TSR_DIS;
159 booke_update_irq(env);
160
161 if (env->spr[SPR_BOOKE_TCR] & TCR_ARE) {
162 /* Auto Reload */
163 cpu_ppc_store_decr(env, env->spr[SPR_BOOKE_DECAR]);
164 }
165 }
166
167 static void booke_fit_cb(void *opaque)
168 {
169 CPUState *env;
170 ppc_tb_t *tb_env;
171 booke_timer_t *booke_timer;
172
173 env = opaque;
174 tb_env = env->tb_env;
175 booke_timer = tb_env->opaque;
176 env->spr[SPR_BOOKE_TSR] |= TSR_FIS;
177
178 booke_update_irq(env);
179
180 booke_update_fixed_timer(env,
181 booke_get_fit_target(env, tb_env),
182 &booke_timer->fit_next,
183 booke_timer->fit_timer);
184 }
185
186 static void booke_wdt_cb(void *opaque)
187 {
188 CPUState *env;
189 ppc_tb_t *tb_env;
190 booke_timer_t *booke_timer;
191
192 env = opaque;
193 tb_env = env->tb_env;
194 booke_timer = tb_env->opaque;
195
196 /* TODO: There's lots of complicated stuff to do here */
197
198 booke_update_irq(env);
199
200 booke_update_fixed_timer(env,
201 booke_get_wdt_target(env, tb_env),
202 &booke_timer->wdt_next,
203 booke_timer->wdt_timer);
204 }
205
206 void store_booke_tsr(CPUState *env, target_ulong val)
207 {
208 env->spr[SPR_BOOKE_TSR] &= ~val;
209 booke_update_irq(env);
210 }
211
212 void store_booke_tcr(CPUState *env, target_ulong val)
213 {
214 ppc_tb_t *tb_env = env->tb_env;
215 booke_timer_t *booke_timer = tb_env->opaque;
216
217 tb_env = env->tb_env;
218 env->spr[SPR_BOOKE_TCR] = val;
219
220 booke_update_irq(env);
221
222 booke_update_fixed_timer(env,
223 booke_get_fit_target(env, tb_env),
224 &booke_timer->fit_next,
225 booke_timer->fit_timer);
226
227 booke_update_fixed_timer(env,
228 booke_get_wdt_target(env, tb_env),
229 &booke_timer->wdt_next,
230 booke_timer->wdt_timer);
231
232 }
233
234 void ppc_booke_timers_init(CPUState *env, uint32_t freq, uint32_t flags)
235 {
236 ppc_tb_t *tb_env;
237 booke_timer_t *booke_timer;
238
239 tb_env = g_malloc0(sizeof(ppc_tb_t));
240 booke_timer = g_malloc0(sizeof(booke_timer_t));
241
242 env->tb_env = tb_env;
243 tb_env->flags = flags | PPC_TIMER_BOOKE | PPC_DECR_ZERO_TRIGGERED;
244
245 tb_env->tb_freq = freq;
246 tb_env->decr_freq = freq;
247 tb_env->opaque = booke_timer;
248 tb_env->decr_timer = qemu_new_timer_ns(vm_clock, &booke_decr_cb, env);
249
250 booke_timer->fit_timer =
251 qemu_new_timer_ns(vm_clock, &booke_fit_cb, env);
252 booke_timer->wdt_timer =
253 qemu_new_timer_ns(vm_clock, &booke_wdt_cb, env);
254 }