PPC: Qdev'ify e500 pci
[qemu.git] / hw / ppce500_pci.c
1 /*
2 * QEMU PowerPC E500 embedded processors pci controller emulation
3 *
4 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
5 *
6 * Author: Yu Liu, <yu.liu@freescale.com>
7 *
8 * This file is derived from hw/ppc4xx_pci.c,
9 * the copyright for that material belongs to the original owners.
10 *
11 * This is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
17 #include "hw.h"
18 #include "pci.h"
19 #include "pci_host.h"
20 #include "bswap.h"
21
22 #ifdef DEBUG_PCI
23 #define pci_debug(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__)
24 #else
25 #define pci_debug(fmt, ...)
26 #endif
27
28 #define PCIE500_CFGADDR 0x0
29 #define PCIE500_CFGDATA 0x4
30 #define PCIE500_REG_BASE 0xC00
31 #define PCIE500_ALL_SIZE 0x1000
32 #define PCIE500_REG_SIZE (PCIE500_ALL_SIZE - PCIE500_REG_BASE)
33
34 #define PPCE500_PCI_CONFIG_ADDR 0x0
35 #define PPCE500_PCI_CONFIG_DATA 0x4
36 #define PPCE500_PCI_INTACK 0x8
37
38 #define PPCE500_PCI_OW1 (0xC20 - PCIE500_REG_BASE)
39 #define PPCE500_PCI_OW2 (0xC40 - PCIE500_REG_BASE)
40 #define PPCE500_PCI_OW3 (0xC60 - PCIE500_REG_BASE)
41 #define PPCE500_PCI_OW4 (0xC80 - PCIE500_REG_BASE)
42 #define PPCE500_PCI_IW3 (0xDA0 - PCIE500_REG_BASE)
43 #define PPCE500_PCI_IW2 (0xDC0 - PCIE500_REG_BASE)
44 #define PPCE500_PCI_IW1 (0xDE0 - PCIE500_REG_BASE)
45
46 #define PPCE500_PCI_GASKET_TIMR (0xE20 - PCIE500_REG_BASE)
47
48 #define PCI_POTAR 0x0
49 #define PCI_POTEAR 0x4
50 #define PCI_POWBAR 0x8
51 #define PCI_POWAR 0x10
52
53 #define PCI_PITAR 0x0
54 #define PCI_PIWBAR 0x8
55 #define PCI_PIWBEAR 0xC
56 #define PCI_PIWAR 0x10
57
58 #define PPCE500_PCI_NR_POBS 5
59 #define PPCE500_PCI_NR_PIBS 3
60
61 struct pci_outbound {
62 uint32_t potar;
63 uint32_t potear;
64 uint32_t powbar;
65 uint32_t powar;
66 };
67
68 struct pci_inbound {
69 uint32_t pitar;
70 uint32_t piwbar;
71 uint32_t piwbear;
72 uint32_t piwar;
73 };
74
75 struct PPCE500PCIState {
76 PCIHostState pci_state;
77 struct pci_outbound pob[PPCE500_PCI_NR_POBS];
78 struct pci_inbound pib[PPCE500_PCI_NR_PIBS];
79 uint32_t gasket_time;
80 qemu_irq irq[4];
81 /* mmio maps */
82 int cfgaddr;
83 int cfgdata;
84 int reg;
85 };
86
87 typedef struct PPCE500PCIState PPCE500PCIState;
88
89 static uint32_t pci_reg_read4(void *opaque, target_phys_addr_t addr)
90 {
91 PPCE500PCIState *pci = opaque;
92 unsigned long win;
93 uint32_t value = 0;
94
95 win = addr & 0xfe0;
96
97 switch (win) {
98 case PPCE500_PCI_OW1:
99 case PPCE500_PCI_OW2:
100 case PPCE500_PCI_OW3:
101 case PPCE500_PCI_OW4:
102 switch (addr & 0xC) {
103 case PCI_POTAR: value = pci->pob[(addr >> 5) & 0x7].potar; break;
104 case PCI_POTEAR: value = pci->pob[(addr >> 5) & 0x7].potear; break;
105 case PCI_POWBAR: value = pci->pob[(addr >> 5) & 0x7].powbar; break;
106 case PCI_POWAR: value = pci->pob[(addr >> 5) & 0x7].powar; break;
107 default: break;
108 }
109 break;
110
111 case PPCE500_PCI_IW3:
112 case PPCE500_PCI_IW2:
113 case PPCE500_PCI_IW1:
114 switch (addr & 0xC) {
115 case PCI_PITAR: value = pci->pib[(addr >> 5) & 0x3].pitar; break;
116 case PCI_PIWBAR: value = pci->pib[(addr >> 5) & 0x3].piwbar; break;
117 case PCI_PIWBEAR: value = pci->pib[(addr >> 5) & 0x3].piwbear; break;
118 case PCI_PIWAR: value = pci->pib[(addr >> 5) & 0x3].piwar; break;
119 default: break;
120 };
121 break;
122
123 case PPCE500_PCI_GASKET_TIMR:
124 value = pci->gasket_time;
125 break;
126
127 default:
128 break;
129 }
130
131 pci_debug("%s: win:%lx(addr:" TARGET_FMT_plx ") -> value:%x\n", __func__,
132 win, addr, value);
133 return value;
134 }
135
136 static CPUReadMemoryFunc * const e500_pci_reg_read[] = {
137 &pci_reg_read4,
138 &pci_reg_read4,
139 &pci_reg_read4,
140 };
141
142 static void pci_reg_write4(void *opaque, target_phys_addr_t addr,
143 uint32_t value)
144 {
145 PPCE500PCIState *pci = opaque;
146 unsigned long win;
147
148 win = addr & 0xfe0;
149
150 pci_debug("%s: value:%x -> win:%lx(addr:" TARGET_FMT_plx ")\n",
151 __func__, value, win, addr);
152
153 switch (win) {
154 case PPCE500_PCI_OW1:
155 case PPCE500_PCI_OW2:
156 case PPCE500_PCI_OW3:
157 case PPCE500_PCI_OW4:
158 switch (addr & 0xC) {
159 case PCI_POTAR: pci->pob[(addr >> 5) & 0x7].potar = value; break;
160 case PCI_POTEAR: pci->pob[(addr >> 5) & 0x7].potear = value; break;
161 case PCI_POWBAR: pci->pob[(addr >> 5) & 0x7].powbar = value; break;
162 case PCI_POWAR: pci->pob[(addr >> 5) & 0x7].powar = value; break;
163 default: break;
164 };
165 break;
166
167 case PPCE500_PCI_IW3:
168 case PPCE500_PCI_IW2:
169 case PPCE500_PCI_IW1:
170 switch (addr & 0xC) {
171 case PCI_PITAR: pci->pib[(addr >> 5) & 0x3].pitar = value; break;
172 case PCI_PIWBAR: pci->pib[(addr >> 5) & 0x3].piwbar = value; break;
173 case PCI_PIWBEAR: pci->pib[(addr >> 5) & 0x3].piwbear = value; break;
174 case PCI_PIWAR: pci->pib[(addr >> 5) & 0x3].piwar = value; break;
175 default: break;
176 };
177 break;
178
179 case PPCE500_PCI_GASKET_TIMR:
180 pci->gasket_time = value;
181 break;
182
183 default:
184 break;
185 };
186 }
187
188 static CPUWriteMemoryFunc * const e500_pci_reg_write[] = {
189 &pci_reg_write4,
190 &pci_reg_write4,
191 &pci_reg_write4,
192 };
193
194 static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
195 {
196 int devno = pci_dev->devfn >> 3, ret = 0;
197
198 switch (devno) {
199 /* Two PCI slot */
200 case 0x11:
201 case 0x12:
202 ret = (irq_num + devno - 0x10) % 4;
203 break;
204 default:
205 printf("Error:%s:unknown dev number\n", __func__);
206 }
207
208 pci_debug("%s: devfn %x irq %d -> %d devno:%x\n", __func__,
209 pci_dev->devfn, irq_num, ret, devno);
210
211 return ret;
212 }
213
214 static void mpc85xx_pci_set_irq(void *opaque, int irq_num, int level)
215 {
216 qemu_irq *pic = opaque;
217
218 pci_debug("%s: PCI irq %d, level:%d\n", __func__, irq_num, level);
219
220 qemu_set_irq(pic[irq_num], level);
221 }
222
223 static const VMStateDescription vmstate_pci_outbound = {
224 .name = "pci_outbound",
225 .version_id = 0,
226 .minimum_version_id = 0,
227 .minimum_version_id_old = 0,
228 .fields = (VMStateField[]) {
229 VMSTATE_UINT32(potar, struct pci_outbound),
230 VMSTATE_UINT32(potear, struct pci_outbound),
231 VMSTATE_UINT32(powbar, struct pci_outbound),
232 VMSTATE_UINT32(powar, struct pci_outbound),
233 VMSTATE_END_OF_LIST()
234 }
235 };
236
237 static const VMStateDescription vmstate_pci_inbound = {
238 .name = "pci_inbound",
239 .version_id = 0,
240 .minimum_version_id = 0,
241 .minimum_version_id_old = 0,
242 .fields = (VMStateField[]) {
243 VMSTATE_UINT32(pitar, struct pci_inbound),
244 VMSTATE_UINT32(piwbar, struct pci_inbound),
245 VMSTATE_UINT32(piwbear, struct pci_inbound),
246 VMSTATE_UINT32(piwar, struct pci_inbound),
247 VMSTATE_END_OF_LIST()
248 }
249 };
250
251 static const VMStateDescription vmstate_ppce500_pci = {
252 .name = "ppce500_pci",
253 .version_id = 1,
254 .minimum_version_id = 1,
255 .minimum_version_id_old = 1,
256 .fields = (VMStateField[]) {
257 VMSTATE_STRUCT_ARRAY(pob, PPCE500PCIState, PPCE500_PCI_NR_POBS, 1,
258 vmstate_pci_outbound, struct pci_outbound),
259 VMSTATE_STRUCT_ARRAY(pib, PPCE500PCIState, PPCE500_PCI_NR_PIBS, 1,
260 vmstate_pci_outbound, struct pci_inbound),
261 VMSTATE_UINT32(gasket_time, PPCE500PCIState),
262 VMSTATE_END_OF_LIST()
263 }
264 };
265
266 static void e500_pci_map(SysBusDevice *dev, target_phys_addr_t base)
267 {
268 PCIHostState *h = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev));
269 PPCE500PCIState *s = DO_UPCAST(PPCE500PCIState, pci_state, h);
270
271 cpu_register_physical_memory(base + PCIE500_CFGADDR, 4, s->cfgaddr);
272 cpu_register_physical_memory(base + PCIE500_CFGDATA, 4, s->cfgdata);
273 cpu_register_physical_memory(base + PCIE500_REG_BASE, PCIE500_REG_SIZE,
274 s->reg);
275 }
276
277 static int e500_pcihost_initfn(SysBusDevice *dev)
278 {
279 PCIHostState *h;
280 PPCE500PCIState *s;
281 PCIBus *b;
282 int i;
283
284 h = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev));
285 s = DO_UPCAST(PPCE500PCIState, pci_state, h);
286
287 for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
288 sysbus_init_irq(dev, &s->irq[i]);
289 }
290
291 b = pci_register_bus(&s->pci_state.busdev.qdev, NULL, mpc85xx_pci_set_irq,
292 mpc85xx_pci_map_irq, s->irq, PCI_DEVFN(0x11, 0), 4);
293 s->pci_state.bus = b;
294
295 pci_create_simple(b, 0, "e500-host-bridge");
296
297 s->cfgaddr = pci_host_conf_register_mmio(&s->pci_state, DEVICE_BIG_ENDIAN);
298 s->cfgdata = pci_host_data_register_mmio(&s->pci_state,
299 DEVICE_LITTLE_ENDIAN);
300 s->reg = cpu_register_io_memory(e500_pci_reg_read, e500_pci_reg_write, s,
301 DEVICE_BIG_ENDIAN);
302 sysbus_init_mmio_cb(dev, PCIE500_ALL_SIZE, e500_pci_map);
303
304 return 0;
305 }
306
307 static int e500_host_bridge_initfn(PCIDevice *dev)
308 {
309 pci_config_set_vendor_id(dev->config, PCI_VENDOR_ID_FREESCALE);
310 pci_config_set_device_id(dev->config, PCI_DEVICE_ID_MPC8533E);
311 pci_config_set_class(dev->config, PCI_CLASS_PROCESSOR_POWERPC);
312
313 return 0;
314 }
315
316 static PCIDeviceInfo e500_host_bridge_info = {
317 .qdev.name = "e500-host-bridge",
318 .qdev.desc = "Host bridge",
319 .qdev.size = sizeof(PCIDevice),
320 .init = e500_host_bridge_initfn,
321 };
322
323 static SysBusDeviceInfo e500_pcihost_info = {
324 .init = e500_pcihost_initfn,
325 .qdev.name = "e500-pcihost",
326 .qdev.size = sizeof(PPCE500PCIState),
327 .qdev.vmsd = &vmstate_ppce500_pci,
328 };
329
330 static void e500_pci_register(void)
331 {
332 sysbus_register_withprop(&e500_pcihost_info);
333 pci_qdev_register(&e500_host_bridge_info);
334 }
335 device_init(e500_pci_register);