Add access control support to qemu bridge helper
[qemu.git] / hw / ppce500_pci.c
1 /*
2 * QEMU PowerPC E500 embedded processors pci controller emulation
3 *
4 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
5 *
6 * Author: Yu Liu, <yu.liu@freescale.com>
7 *
8 * This file is derived from hw/ppc4xx_pci.c,
9 * the copyright for that material belongs to the original owners.
10 *
11 * This is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
17 #include "hw.h"
18 #include "pci.h"
19 #include "pci_host.h"
20 #include "bswap.h"
21
22 #ifdef DEBUG_PCI
23 #define pci_debug(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__)
24 #else
25 #define pci_debug(fmt, ...)
26 #endif
27
28 #define PCIE500_CFGADDR 0x0
29 #define PCIE500_CFGDATA 0x4
30 #define PCIE500_REG_BASE 0xC00
31 #define PCIE500_ALL_SIZE 0x1000
32 #define PCIE500_REG_SIZE (PCIE500_ALL_SIZE - PCIE500_REG_BASE)
33
34 #define PPCE500_PCI_CONFIG_ADDR 0x0
35 #define PPCE500_PCI_CONFIG_DATA 0x4
36 #define PPCE500_PCI_INTACK 0x8
37
38 #define PPCE500_PCI_OW1 (0xC20 - PCIE500_REG_BASE)
39 #define PPCE500_PCI_OW2 (0xC40 - PCIE500_REG_BASE)
40 #define PPCE500_PCI_OW3 (0xC60 - PCIE500_REG_BASE)
41 #define PPCE500_PCI_OW4 (0xC80 - PCIE500_REG_BASE)
42 #define PPCE500_PCI_IW3 (0xDA0 - PCIE500_REG_BASE)
43 #define PPCE500_PCI_IW2 (0xDC0 - PCIE500_REG_BASE)
44 #define PPCE500_PCI_IW1 (0xDE0 - PCIE500_REG_BASE)
45
46 #define PPCE500_PCI_GASKET_TIMR (0xE20 - PCIE500_REG_BASE)
47
48 #define PCI_POTAR 0x0
49 #define PCI_POTEAR 0x4
50 #define PCI_POWBAR 0x8
51 #define PCI_POWAR 0x10
52
53 #define PCI_PITAR 0x0
54 #define PCI_PIWBAR 0x8
55 #define PCI_PIWBEAR 0xC
56 #define PCI_PIWAR 0x10
57
58 #define PPCE500_PCI_NR_POBS 5
59 #define PPCE500_PCI_NR_PIBS 3
60
61 struct pci_outbound {
62 uint32_t potar;
63 uint32_t potear;
64 uint32_t powbar;
65 uint32_t powar;
66 };
67
68 struct pci_inbound {
69 uint32_t pitar;
70 uint32_t piwbar;
71 uint32_t piwbear;
72 uint32_t piwar;
73 };
74
75 struct PPCE500PCIState {
76 PCIHostState pci_state;
77 struct pci_outbound pob[PPCE500_PCI_NR_POBS];
78 struct pci_inbound pib[PPCE500_PCI_NR_PIBS];
79 uint32_t gasket_time;
80 qemu_irq irq[4];
81 /* mmio maps */
82 MemoryRegion container;
83 MemoryRegion iomem;
84 };
85
86 typedef struct PPCE500PCIState PPCE500PCIState;
87
88 static uint64_t pci_reg_read4(void *opaque, target_phys_addr_t addr,
89 unsigned size)
90 {
91 PPCE500PCIState *pci = opaque;
92 unsigned long win;
93 uint32_t value = 0;
94 int idx;
95
96 win = addr & 0xfe0;
97
98 switch (win) {
99 case PPCE500_PCI_OW1:
100 case PPCE500_PCI_OW2:
101 case PPCE500_PCI_OW3:
102 case PPCE500_PCI_OW4:
103 idx = (addr >> 5) & 0x7;
104 switch (addr & 0xC) {
105 case PCI_POTAR:
106 value = pci->pob[idx].potar;
107 break;
108 case PCI_POTEAR:
109 value = pci->pob[idx].potear;
110 break;
111 case PCI_POWBAR:
112 value = pci->pob[idx].powbar;
113 break;
114 case PCI_POWAR:
115 value = pci->pob[idx].powar;
116 break;
117 default:
118 break;
119 }
120 break;
121
122 case PPCE500_PCI_IW3:
123 case PPCE500_PCI_IW2:
124 case PPCE500_PCI_IW1:
125 idx = ((addr >> 5) & 0x3) - 1;
126 switch (addr & 0xC) {
127 case PCI_PITAR:
128 value = pci->pib[idx].pitar;
129 break;
130 case PCI_PIWBAR:
131 value = pci->pib[idx].piwbar;
132 break;
133 case PCI_PIWBEAR:
134 value = pci->pib[idx].piwbear;
135 break;
136 case PCI_PIWAR:
137 value = pci->pib[idx].piwar;
138 break;
139 default:
140 break;
141 };
142 break;
143
144 case PPCE500_PCI_GASKET_TIMR:
145 value = pci->gasket_time;
146 break;
147
148 default:
149 break;
150 }
151
152 pci_debug("%s: win:%lx(addr:" TARGET_FMT_plx ") -> value:%x\n", __func__,
153 win, addr, value);
154 return value;
155 }
156
157 static void pci_reg_write4(void *opaque, target_phys_addr_t addr,
158 uint64_t value, unsigned size)
159 {
160 PPCE500PCIState *pci = opaque;
161 unsigned long win;
162 int idx;
163
164 win = addr & 0xfe0;
165
166 pci_debug("%s: value:%x -> win:%lx(addr:" TARGET_FMT_plx ")\n",
167 __func__, (unsigned)value, win, addr);
168
169 switch (win) {
170 case PPCE500_PCI_OW1:
171 case PPCE500_PCI_OW2:
172 case PPCE500_PCI_OW3:
173 case PPCE500_PCI_OW4:
174 idx = (addr >> 5) & 0x7;
175 switch (addr & 0xC) {
176 case PCI_POTAR:
177 pci->pob[idx].potar = value;
178 break;
179 case PCI_POTEAR:
180 pci->pob[idx].potear = value;
181 break;
182 case PCI_POWBAR:
183 pci->pob[idx].powbar = value;
184 break;
185 case PCI_POWAR:
186 pci->pob[idx].powar = value;
187 break;
188 default:
189 break;
190 };
191 break;
192
193 case PPCE500_PCI_IW3:
194 case PPCE500_PCI_IW2:
195 case PPCE500_PCI_IW1:
196 idx = ((addr >> 5) & 0x3) - 1;
197 switch (addr & 0xC) {
198 case PCI_PITAR:
199 pci->pib[idx].pitar = value;
200 break;
201 case PCI_PIWBAR:
202 pci->pib[idx].piwbar = value;
203 break;
204 case PCI_PIWBEAR:
205 pci->pib[idx].piwbear = value;
206 break;
207 case PCI_PIWAR:
208 pci->pib[idx].piwar = value;
209 break;
210 default:
211 break;
212 };
213 break;
214
215 case PPCE500_PCI_GASKET_TIMR:
216 pci->gasket_time = value;
217 break;
218
219 default:
220 break;
221 };
222 }
223
224 static const MemoryRegionOps e500_pci_reg_ops = {
225 .read = pci_reg_read4,
226 .write = pci_reg_write4,
227 .endianness = DEVICE_BIG_ENDIAN,
228 };
229
230 static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
231 {
232 int devno = pci_dev->devfn >> 3, ret = 0;
233
234 switch (devno) {
235 /* Two PCI slot */
236 case 0x11:
237 case 0x12:
238 ret = (irq_num + devno - 0x10) % 4;
239 break;
240 default:
241 printf("Error:%s:unknown dev number\n", __func__);
242 }
243
244 pci_debug("%s: devfn %x irq %d -> %d devno:%x\n", __func__,
245 pci_dev->devfn, irq_num, ret, devno);
246
247 return ret;
248 }
249
250 static void mpc85xx_pci_set_irq(void *opaque, int irq_num, int level)
251 {
252 qemu_irq *pic = opaque;
253
254 pci_debug("%s: PCI irq %d, level:%d\n", __func__, irq_num, level);
255
256 qemu_set_irq(pic[irq_num], level);
257 }
258
259 static const VMStateDescription vmstate_pci_outbound = {
260 .name = "pci_outbound",
261 .version_id = 0,
262 .minimum_version_id = 0,
263 .minimum_version_id_old = 0,
264 .fields = (VMStateField[]) {
265 VMSTATE_UINT32(potar, struct pci_outbound),
266 VMSTATE_UINT32(potear, struct pci_outbound),
267 VMSTATE_UINT32(powbar, struct pci_outbound),
268 VMSTATE_UINT32(powar, struct pci_outbound),
269 VMSTATE_END_OF_LIST()
270 }
271 };
272
273 static const VMStateDescription vmstate_pci_inbound = {
274 .name = "pci_inbound",
275 .version_id = 0,
276 .minimum_version_id = 0,
277 .minimum_version_id_old = 0,
278 .fields = (VMStateField[]) {
279 VMSTATE_UINT32(pitar, struct pci_inbound),
280 VMSTATE_UINT32(piwbar, struct pci_inbound),
281 VMSTATE_UINT32(piwbear, struct pci_inbound),
282 VMSTATE_UINT32(piwar, struct pci_inbound),
283 VMSTATE_END_OF_LIST()
284 }
285 };
286
287 static const VMStateDescription vmstate_ppce500_pci = {
288 .name = "ppce500_pci",
289 .version_id = 1,
290 .minimum_version_id = 1,
291 .minimum_version_id_old = 1,
292 .fields = (VMStateField[]) {
293 VMSTATE_STRUCT_ARRAY(pob, PPCE500PCIState, PPCE500_PCI_NR_POBS, 1,
294 vmstate_pci_outbound, struct pci_outbound),
295 VMSTATE_STRUCT_ARRAY(pib, PPCE500PCIState, PPCE500_PCI_NR_PIBS, 1,
296 vmstate_pci_outbound, struct pci_inbound),
297 VMSTATE_UINT32(gasket_time, PPCE500PCIState),
298 VMSTATE_END_OF_LIST()
299 }
300 };
301
302 #include "exec-memory.h"
303
304 static int e500_pcihost_initfn(SysBusDevice *dev)
305 {
306 PCIHostState *h;
307 PPCE500PCIState *s;
308 PCIBus *b;
309 int i;
310 MemoryRegion *address_space_mem = get_system_memory();
311 MemoryRegion *address_space_io = get_system_io();
312
313 h = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev));
314 s = DO_UPCAST(PPCE500PCIState, pci_state, h);
315
316 for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
317 sysbus_init_irq(dev, &s->irq[i]);
318 }
319
320 b = pci_register_bus(&s->pci_state.busdev.qdev, NULL, mpc85xx_pci_set_irq,
321 mpc85xx_pci_map_irq, s->irq, address_space_mem,
322 address_space_io, PCI_DEVFN(0x11, 0), 4);
323 s->pci_state.bus = b;
324
325 pci_create_simple(b, 0, "e500-host-bridge");
326
327 memory_region_init(&s->container, "pci-container", PCIE500_ALL_SIZE);
328 memory_region_init_io(&h->conf_mem, &pci_host_conf_be_ops, h,
329 "pci-conf-idx", 4);
330 memory_region_init_io(&h->data_mem, &pci_host_data_le_ops, h,
331 "pci-conf-data", 4);
332 memory_region_init_io(&s->iomem, &e500_pci_reg_ops, s,
333 "pci.reg", PCIE500_REG_SIZE);
334 memory_region_add_subregion(&s->container, PCIE500_CFGADDR, &h->conf_mem);
335 memory_region_add_subregion(&s->container, PCIE500_CFGDATA, &h->data_mem);
336 memory_region_add_subregion(&s->container, PCIE500_REG_BASE, &s->iomem);
337 sysbus_init_mmio(dev, &s->container);
338
339 return 0;
340 }
341
342 static void e500_host_bridge_class_init(ObjectClass *klass, void *data)
343 {
344 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
345
346 k->vendor_id = PCI_VENDOR_ID_FREESCALE;
347 k->device_id = PCI_DEVICE_ID_MPC8533E;
348 k->class_id = PCI_CLASS_PROCESSOR_POWERPC;
349 }
350
351 static DeviceInfo e500_host_bridge_info = {
352 .name = "e500-host-bridge",
353 .desc = "Host bridge",
354 .size = sizeof(PCIDevice),
355 .class_init = e500_host_bridge_class_init,
356 };
357
358 static void e500_pcihost_class_init(ObjectClass *klass, void *data)
359 {
360 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
361
362 k->init = e500_pcihost_initfn;
363 }
364
365 static DeviceInfo e500_pcihost_info = {
366 .name = "e500-pcihost",
367 .size = sizeof(PPCE500PCIState),
368 .vmsd = &vmstate_ppce500_pci,
369 .class_init = e500_pcihost_class_init,
370 };
371
372 static void e500_pci_register(void)
373 {
374 sysbus_register_withprop(&e500_pcihost_info);
375 pci_qdev_register(&e500_host_bridge_info);
376 }
377 device_init(e500_pci_register);