linux-user: stack_base is now mandatory on all targets
[qemu.git] / hw / ppce500_spin.c
1 /*
2 * QEMU PowerPC e500v2 ePAPR spinning code
3 *
4 * Copyright (C) 2011 Freescale Semiconductor, Inc. All rights reserved.
5 *
6 * Author: Alexander Graf, <agraf@suse.de>
7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 *
21 * This code is not really a device, but models an interface that usually
22 * firmware takes care of. It's used when QEMU plays the role of firmware.
23 *
24 * Specification:
25 *
26 * https://www.power.org/resources/downloads/Power_ePAPR_APPROVED_v1.1.pdf
27 *
28 */
29
30 #include "hw.h"
31 #include "sysemu.h"
32 #include "sysbus.h"
33 #include "kvm.h"
34
35 #define MAX_CPUS 32
36
37 typedef struct spin_info {
38 uint64_t addr;
39 uint64_t r3;
40 uint32_t resv;
41 uint32_t pir;
42 uint64_t reserved;
43 } __attribute__ ((packed)) SpinInfo;
44
45 typedef struct spin_state {
46 SysBusDevice busdev;
47 MemoryRegion iomem;
48 SpinInfo spin[MAX_CPUS];
49 } SpinState;
50
51 typedef struct spin_kick {
52 CPUState *env;
53 SpinInfo *spin;
54 } SpinKick;
55
56 static void spin_reset(void *opaque)
57 {
58 SpinState *s = opaque;
59 int i;
60
61 for (i = 0; i < MAX_CPUS; i++) {
62 SpinInfo *info = &s->spin[i];
63
64 info->pir = i;
65 info->r3 = i;
66 info->addr = 1;
67 }
68 }
69
70 /* Create -kernel TLB entries for BookE, linearly spanning 256MB. */
71 static inline target_phys_addr_t booke206_page_size_to_tlb(uint64_t size)
72 {
73 return (ffs(size >> 10) - 1) >> 1;
74 }
75
76 static void mmubooke_create_initial_mapping(CPUState *env,
77 target_ulong va,
78 target_phys_addr_t pa,
79 target_phys_addr_t len)
80 {
81 ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 1);
82 target_phys_addr_t size;
83
84 size = (booke206_page_size_to_tlb(len) << MAS1_TSIZE_SHIFT);
85 tlb->mas1 = MAS1_VALID | size;
86 tlb->mas2 = (va & TARGET_PAGE_MASK) | MAS2_M;
87 tlb->mas7_3 = pa & TARGET_PAGE_MASK;
88 tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX;
89 }
90
91 static void spin_kick(void *data)
92 {
93 SpinKick *kick = data;
94 CPUState *env = kick->env;
95 SpinInfo *curspin = kick->spin;
96 target_phys_addr_t map_size = 64 * 1024 * 1024;
97 target_phys_addr_t map_start;
98
99 cpu_synchronize_state(env);
100 stl_p(&curspin->pir, env->spr[SPR_PIR]);
101 env->nip = ldq_p(&curspin->addr) & (map_size - 1);
102 env->gpr[3] = ldq_p(&curspin->r3);
103 env->gpr[4] = 0;
104 env->gpr[5] = 0;
105 env->gpr[6] = 0;
106 env->gpr[7] = map_size;
107 env->gpr[8] = 0;
108 env->gpr[9] = 0;
109
110 map_start = ldq_p(&curspin->addr) & ~(map_size - 1);
111 mmubooke_create_initial_mapping(env, 0, map_start, map_size);
112
113 env->halted = 0;
114 env->exception_index = -1;
115 env->stopped = 0;
116 qemu_cpu_kick(env);
117 }
118
119 static void spin_write(void *opaque, target_phys_addr_t addr, uint64_t value,
120 unsigned len)
121 {
122 SpinState *s = opaque;
123 int env_idx = addr / sizeof(SpinInfo);
124 CPUState *env;
125 SpinInfo *curspin = &s->spin[env_idx];
126 uint8_t *curspin_p = (uint8_t*)curspin;
127
128 for (env = first_cpu; env != NULL; env = env->next_cpu) {
129 if (env->cpu_index == env_idx) {
130 break;
131 }
132 }
133
134 if (!env) {
135 /* Unknown CPU */
136 return;
137 }
138
139 if (!env->cpu_index) {
140 /* primary CPU doesn't spin */
141 return;
142 }
143
144 curspin_p = &curspin_p[addr % sizeof(SpinInfo)];
145 switch (len) {
146 case 1:
147 stb_p(curspin_p, value);
148 break;
149 case 2:
150 stw_p(curspin_p, value);
151 break;
152 case 4:
153 stl_p(curspin_p, value);
154 break;
155 }
156
157 if (!(ldq_p(&curspin->addr) & 1)) {
158 /* run CPU */
159 SpinKick kick = {
160 .env = env,
161 .spin = curspin,
162 };
163
164 run_on_cpu(env, spin_kick, &kick);
165 }
166 }
167
168 static uint64_t spin_read(void *opaque, target_phys_addr_t addr, unsigned len)
169 {
170 SpinState *s = opaque;
171 uint8_t *spin_p = &((uint8_t*)s->spin)[addr];
172
173 switch (len) {
174 case 1:
175 return ldub_p(spin_p);
176 case 2:
177 return lduw_p(spin_p);
178 case 4:
179 return ldl_p(spin_p);
180 default:
181 assert(0);
182 }
183 }
184
185 const MemoryRegionOps spin_rw_ops = {
186 .read = spin_read,
187 .write = spin_write,
188 .endianness = DEVICE_BIG_ENDIAN,
189 };
190
191 static int ppce500_spin_initfn(SysBusDevice *dev)
192 {
193 SpinState *s;
194
195 s = FROM_SYSBUS(SpinState, sysbus_from_qdev(dev));
196
197 memory_region_init_io(&s->iomem, &spin_rw_ops, s, "e500 spin pv device",
198 sizeof(SpinInfo) * MAX_CPUS);
199 sysbus_init_mmio(dev, &s->iomem);
200
201 qemu_register_reset(spin_reset, s);
202
203 return 0;
204 }
205
206 static void ppce500_spin_class_init(ObjectClass *klass, void *data)
207 {
208 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
209
210 k->init = ppce500_spin_initfn;
211 }
212
213 static DeviceInfo ppce500_spin_info = {
214 .name = "e500-spin",
215 .size = sizeof(SpinState),
216 .class_init = ppce500_spin_class_init,
217 };
218
219 static void ppce500_spin_register(void)
220 {
221 sysbus_register_withprop(&ppce500_spin_info);
222 }
223 device_init(ppce500_spin_register);