Add access control support to qemu bridge helper
[qemu.git] / hw / pxa.h
1 /*
2 * Intel XScale PXA255/270 processor support.
3 *
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
6 *
7 * This code is licensed under the GNU GPL v2.
8 */
9 #ifndef PXA_H
10 # define PXA_H "pxa.h"
11
12 #include "memory.h"
13
14 /* Interrupt numbers */
15 # define PXA2XX_PIC_SSP3 0
16 # define PXA2XX_PIC_USBH2 2
17 # define PXA2XX_PIC_USBH1 3
18 # define PXA2XX_PIC_KEYPAD 4
19 # define PXA2XX_PIC_PWRI2C 6
20 # define PXA25X_PIC_HWUART 7
21 # define PXA27X_PIC_OST_4_11 7
22 # define PXA2XX_PIC_GPIO_0 8
23 # define PXA2XX_PIC_GPIO_1 9
24 # define PXA2XX_PIC_GPIO_X 10
25 # define PXA2XX_PIC_I2S 13
26 # define PXA26X_PIC_ASSP 15
27 # define PXA25X_PIC_NSSP 16
28 # define PXA27X_PIC_SSP2 16
29 # define PXA2XX_PIC_LCD 17
30 # define PXA2XX_PIC_I2C 18
31 # define PXA2XX_PIC_ICP 19
32 # define PXA2XX_PIC_STUART 20
33 # define PXA2XX_PIC_BTUART 21
34 # define PXA2XX_PIC_FFUART 22
35 # define PXA2XX_PIC_MMC 23
36 # define PXA2XX_PIC_SSP 24
37 # define PXA2XX_PIC_DMA 25
38 # define PXA2XX_PIC_OST_0 26
39 # define PXA2XX_PIC_RTC1HZ 30
40 # define PXA2XX_PIC_RTCALARM 31
41
42 /* DMA requests */
43 # define PXA2XX_RX_RQ_I2S 2
44 # define PXA2XX_TX_RQ_I2S 3
45 # define PXA2XX_RX_RQ_BTUART 4
46 # define PXA2XX_TX_RQ_BTUART 5
47 # define PXA2XX_RX_RQ_FFUART 6
48 # define PXA2XX_TX_RQ_FFUART 7
49 # define PXA2XX_RX_RQ_SSP1 13
50 # define PXA2XX_TX_RQ_SSP1 14
51 # define PXA2XX_RX_RQ_SSP2 15
52 # define PXA2XX_TX_RQ_SSP2 16
53 # define PXA2XX_RX_RQ_ICP 17
54 # define PXA2XX_TX_RQ_ICP 18
55 # define PXA2XX_RX_RQ_STUART 19
56 # define PXA2XX_TX_RQ_STUART 20
57 # define PXA2XX_RX_RQ_MMCI 21
58 # define PXA2XX_TX_RQ_MMCI 22
59 # define PXA2XX_USB_RQ(x) ((x) + 24)
60 # define PXA2XX_RX_RQ_SSP3 66
61 # define PXA2XX_TX_RQ_SSP3 67
62
63 # define PXA2XX_SDRAM_BASE 0xa0000000
64 # define PXA2XX_INTERNAL_BASE 0x5c000000
65 # define PXA2XX_INTERNAL_SIZE 0x40000
66
67 /* pxa2xx_pic.c */
68 DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env);
69
70 /* pxa2xx_gpio.c */
71 DeviceState *pxa2xx_gpio_init(target_phys_addr_t base,
72 CPUState *env, DeviceState *pic, int lines);
73 void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler);
74
75 /* pxa2xx_dma.c */
76 DeviceState *pxa255_dma_init(target_phys_addr_t base, qemu_irq irq);
77 DeviceState *pxa27x_dma_init(target_phys_addr_t base, qemu_irq irq);
78
79 /* pxa2xx_lcd.c */
80 typedef struct PXA2xxLCDState PXA2xxLCDState;
81 PXA2xxLCDState *pxa2xx_lcdc_init(MemoryRegion *sysmem,
82 target_phys_addr_t base, qemu_irq irq);
83 void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler);
84 void pxa2xx_lcdc_oritentation(void *opaque, int angle);
85
86 /* pxa2xx_mmci.c */
87 typedef struct PXA2xxMMCIState PXA2xxMMCIState;
88 PXA2xxMMCIState *pxa2xx_mmci_init(MemoryRegion *sysmem,
89 target_phys_addr_t base,
90 BlockDriverState *bd, qemu_irq irq,
91 qemu_irq rx_dma, qemu_irq tx_dma);
92 void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly,
93 qemu_irq coverswitch);
94
95 /* pxa2xx_pcmcia.c */
96 typedef struct PXA2xxPCMCIAState PXA2xxPCMCIAState;
97 PXA2xxPCMCIAState *pxa2xx_pcmcia_init(MemoryRegion *sysmem,
98 target_phys_addr_t base);
99 int pxa2xx_pcmcia_attach(void *opaque, PCMCIACardState *card);
100 int pxa2xx_pcmcia_dettach(void *opaque);
101 void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq);
102
103 /* pxa2xx_keypad.c */
104 struct keymap {
105 int column;
106 int row;
107 };
108 typedef struct PXA2xxKeyPadState PXA2xxKeyPadState;
109 PXA2xxKeyPadState *pxa27x_keypad_init(MemoryRegion *sysmem,
110 target_phys_addr_t base,
111 qemu_irq irq);
112 void pxa27x_register_keypad(PXA2xxKeyPadState *kp, struct keymap *map,
113 int size);
114
115 /* pxa2xx.c */
116 typedef struct PXA2xxI2CState PXA2xxI2CState;
117 PXA2xxI2CState *pxa2xx_i2c_init(target_phys_addr_t base,
118 qemu_irq irq, uint32_t page_size);
119 i2c_bus *pxa2xx_i2c_bus(PXA2xxI2CState *s);
120
121 typedef struct PXA2xxI2SState PXA2xxI2SState;
122 typedef struct PXA2xxFIrState PXA2xxFIrState;
123
124 typedef struct {
125 CPUState *env;
126 DeviceState *pic;
127 qemu_irq reset;
128 MemoryRegion sdram;
129 MemoryRegion internal;
130 MemoryRegion cm_iomem;
131 MemoryRegion mm_iomem;
132 MemoryRegion pm_iomem;
133 DeviceState *dma;
134 DeviceState *gpio;
135 PXA2xxLCDState *lcd;
136 SSIBus **ssp;
137 PXA2xxI2CState *i2c[2];
138 PXA2xxMMCIState *mmc;
139 PXA2xxPCMCIAState *pcmcia[2];
140 PXA2xxI2SState *i2s;
141 PXA2xxFIrState *fir;
142 PXA2xxKeyPadState *kp;
143
144 /* Power management */
145 target_phys_addr_t pm_base;
146 uint32_t pm_regs[0x40];
147
148 /* Clock management */
149 target_phys_addr_t cm_base;
150 uint32_t cm_regs[4];
151 uint32_t clkcfg;
152
153 /* Memory management */
154 target_phys_addr_t mm_base;
155 uint32_t mm_regs[0x1a];
156
157 /* Performance monitoring */
158 uint32_t pmnc;
159 } PXA2xxState;
160
161 struct PXA2xxI2SState {
162 MemoryRegion iomem;
163 qemu_irq irq;
164 qemu_irq rx_dma;
165 qemu_irq tx_dma;
166 void (*data_req)(void *, int, int);
167
168 uint32_t control[2];
169 uint32_t status;
170 uint32_t mask;
171 uint32_t clk;
172
173 int enable;
174 int rx_len;
175 int tx_len;
176 void (*codec_out)(void *, uint32_t);
177 uint32_t (*codec_in)(void *);
178 void *opaque;
179
180 int fifo_len;
181 uint32_t fifo[16];
182 };
183
184 # define PA_FMT "0x%08lx"
185 # define REG_FMT "0x" TARGET_FMT_plx
186
187 PXA2xxState *pxa270_init(MemoryRegion *address_space, unsigned int sdram_size,
188 const char *revision);
189 PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size);
190
191 #endif /* PXA_H */