PPC: e500mc: add missing IVORs to bitmap
[qemu.git] / hw / pxa2xx_pic.c
1 /*
2 * Intel XScale PXA Programmable Interrupt Controller.
3 *
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Copyright (c) 2006 Thorsten Zitterell
6 * Written by Andrzej Zaborowski <balrog@zabor.org>
7 *
8 * This code is licensed under the GPL.
9 */
10
11 #include "hw.h"
12 #include "pxa.h"
13 #include "sysbus.h"
14
15 #define ICIP 0x00 /* Interrupt Controller IRQ Pending register */
16 #define ICMR 0x04 /* Interrupt Controller Mask register */
17 #define ICLR 0x08 /* Interrupt Controller Level register */
18 #define ICFP 0x0c /* Interrupt Controller FIQ Pending register */
19 #define ICPR 0x10 /* Interrupt Controller Pending register */
20 #define ICCR 0x14 /* Interrupt Controller Control register */
21 #define ICHP 0x18 /* Interrupt Controller Highest Priority register */
22 #define IPR0 0x1c /* Interrupt Controller Priority register 0 */
23 #define IPR31 0x98 /* Interrupt Controller Priority register 31 */
24 #define ICIP2 0x9c /* Interrupt Controller IRQ Pending register 2 */
25 #define ICMR2 0xa0 /* Interrupt Controller Mask register 2 */
26 #define ICLR2 0xa4 /* Interrupt Controller Level register 2 */
27 #define ICFP2 0xa8 /* Interrupt Controller FIQ Pending register 2 */
28 #define ICPR2 0xac /* Interrupt Controller Pending register 2 */
29 #define IPR32 0xb0 /* Interrupt Controller Priority register 32 */
30 #define IPR39 0xcc /* Interrupt Controller Priority register 39 */
31
32 #define PXA2XX_PIC_SRCS 40
33
34 typedef struct {
35 SysBusDevice busdev;
36 MemoryRegion iomem;
37 CPUState *cpu_env;
38 uint32_t int_enabled[2];
39 uint32_t int_pending[2];
40 uint32_t is_fiq[2];
41 uint32_t int_idle;
42 uint32_t priority[PXA2XX_PIC_SRCS];
43 } PXA2xxPICState;
44
45 static void pxa2xx_pic_update(void *opaque)
46 {
47 uint32_t mask[2];
48 PXA2xxPICState *s = (PXA2xxPICState *) opaque;
49
50 if (s->cpu_env->halted) {
51 mask[0] = s->int_pending[0] & (s->int_enabled[0] | s->int_idle);
52 mask[1] = s->int_pending[1] & (s->int_enabled[1] | s->int_idle);
53 if (mask[0] || mask[1])
54 cpu_interrupt(s->cpu_env, CPU_INTERRUPT_EXITTB);
55 }
56
57 mask[0] = s->int_pending[0] & s->int_enabled[0];
58 mask[1] = s->int_pending[1] & s->int_enabled[1];
59
60 if ((mask[0] & s->is_fiq[0]) || (mask[1] & s->is_fiq[1]))
61 cpu_interrupt(s->cpu_env, CPU_INTERRUPT_FIQ);
62 else
63 cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_FIQ);
64
65 if ((mask[0] & ~s->is_fiq[0]) || (mask[1] & ~s->is_fiq[1]))
66 cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
67 else
68 cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
69 }
70
71 /* Note: Here level means state of the signal on a pin, not
72 * IRQ/FIQ distinction as in PXA Developer Manual. */
73 static void pxa2xx_pic_set_irq(void *opaque, int irq, int level)
74 {
75 PXA2xxPICState *s = (PXA2xxPICState *) opaque;
76 int int_set = (irq >= 32);
77 irq &= 31;
78
79 if (level)
80 s->int_pending[int_set] |= 1 << irq;
81 else
82 s->int_pending[int_set] &= ~(1 << irq);
83
84 pxa2xx_pic_update(opaque);
85 }
86
87 static inline uint32_t pxa2xx_pic_highest(PXA2xxPICState *s) {
88 int i, int_set, irq;
89 uint32_t bit, mask[2];
90 uint32_t ichp = 0x003f003f; /* Both IDs invalid */
91
92 mask[0] = s->int_pending[0] & s->int_enabled[0];
93 mask[1] = s->int_pending[1] & s->int_enabled[1];
94
95 for (i = PXA2XX_PIC_SRCS - 1; i >= 0; i --) {
96 irq = s->priority[i] & 0x3f;
97 if ((s->priority[i] & (1 << 31)) && irq < PXA2XX_PIC_SRCS) {
98 /* Source peripheral ID is valid. */
99 bit = 1 << (irq & 31);
100 int_set = (irq >= 32);
101
102 if (mask[int_set] & bit & s->is_fiq[int_set]) {
103 /* FIQ asserted */
104 ichp &= 0xffff0000;
105 ichp |= (1 << 15) | irq;
106 }
107
108 if (mask[int_set] & bit & ~s->is_fiq[int_set]) {
109 /* IRQ asserted */
110 ichp &= 0x0000ffff;
111 ichp |= (1 << 31) | (irq << 16);
112 }
113 }
114 }
115
116 return ichp;
117 }
118
119 static uint64_t pxa2xx_pic_mem_read(void *opaque, target_phys_addr_t offset,
120 unsigned size)
121 {
122 PXA2xxPICState *s = (PXA2xxPICState *) opaque;
123
124 switch (offset) {
125 case ICIP: /* IRQ Pending register */
126 return s->int_pending[0] & ~s->is_fiq[0] & s->int_enabled[0];
127 case ICIP2: /* IRQ Pending register 2 */
128 return s->int_pending[1] & ~s->is_fiq[1] & s->int_enabled[1];
129 case ICMR: /* Mask register */
130 return s->int_enabled[0];
131 case ICMR2: /* Mask register 2 */
132 return s->int_enabled[1];
133 case ICLR: /* Level register */
134 return s->is_fiq[0];
135 case ICLR2: /* Level register 2 */
136 return s->is_fiq[1];
137 case ICCR: /* Idle mask */
138 return (s->int_idle == 0);
139 case ICFP: /* FIQ Pending register */
140 return s->int_pending[0] & s->is_fiq[0] & s->int_enabled[0];
141 case ICFP2: /* FIQ Pending register 2 */
142 return s->int_pending[1] & s->is_fiq[1] & s->int_enabled[1];
143 case ICPR: /* Pending register */
144 return s->int_pending[0];
145 case ICPR2: /* Pending register 2 */
146 return s->int_pending[1];
147 case IPR0 ... IPR31:
148 return s->priority[0 + ((offset - IPR0 ) >> 2)];
149 case IPR32 ... IPR39:
150 return s->priority[32 + ((offset - IPR32) >> 2)];
151 case ICHP: /* Highest Priority register */
152 return pxa2xx_pic_highest(s);
153 default:
154 printf("%s: Bad register offset " REG_FMT "\n", __FUNCTION__, offset);
155 return 0;
156 }
157 }
158
159 static void pxa2xx_pic_mem_write(void *opaque, target_phys_addr_t offset,
160 uint64_t value, unsigned size)
161 {
162 PXA2xxPICState *s = (PXA2xxPICState *) opaque;
163
164 switch (offset) {
165 case ICMR: /* Mask register */
166 s->int_enabled[0] = value;
167 break;
168 case ICMR2: /* Mask register 2 */
169 s->int_enabled[1] = value;
170 break;
171 case ICLR: /* Level register */
172 s->is_fiq[0] = value;
173 break;
174 case ICLR2: /* Level register 2 */
175 s->is_fiq[1] = value;
176 break;
177 case ICCR: /* Idle mask */
178 s->int_idle = (value & 1) ? 0 : ~0;
179 break;
180 case IPR0 ... IPR31:
181 s->priority[0 + ((offset - IPR0 ) >> 2)] = value & 0x8000003f;
182 break;
183 case IPR32 ... IPR39:
184 s->priority[32 + ((offset - IPR32) >> 2)] = value & 0x8000003f;
185 break;
186 default:
187 printf("%s: Bad register offset " REG_FMT "\n", __FUNCTION__, offset);
188 return;
189 }
190 pxa2xx_pic_update(opaque);
191 }
192
193 /* Interrupt Controller Coprocessor Space Register Mapping */
194 static const int pxa2xx_cp_reg_map[0x10] = {
195 [0x0 ... 0xf] = -1,
196 [0x0] = ICIP,
197 [0x1] = ICMR,
198 [0x2] = ICLR,
199 [0x3] = ICFP,
200 [0x4] = ICPR,
201 [0x5] = ICHP,
202 [0x6] = ICIP2,
203 [0x7] = ICMR2,
204 [0x8] = ICLR2,
205 [0x9] = ICFP2,
206 [0xa] = ICPR2,
207 };
208
209 static uint32_t pxa2xx_pic_cp_read(void *opaque, int op2, int reg, int crm)
210 {
211 target_phys_addr_t offset;
212
213 if (pxa2xx_cp_reg_map[reg] == -1) {
214 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
215 return 0;
216 }
217
218 offset = pxa2xx_cp_reg_map[reg];
219 return pxa2xx_pic_mem_read(opaque, offset, 4);
220 }
221
222 static void pxa2xx_pic_cp_write(void *opaque, int op2, int reg, int crm,
223 uint32_t value)
224 {
225 target_phys_addr_t offset;
226
227 if (pxa2xx_cp_reg_map[reg] == -1) {
228 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
229 return;
230 }
231
232 offset = pxa2xx_cp_reg_map[reg];
233 pxa2xx_pic_mem_write(opaque, offset, value, 4);
234 }
235
236 static const MemoryRegionOps pxa2xx_pic_ops = {
237 .read = pxa2xx_pic_mem_read,
238 .write = pxa2xx_pic_mem_write,
239 .endianness = DEVICE_NATIVE_ENDIAN,
240 };
241
242 static int pxa2xx_pic_post_load(void *opaque, int version_id)
243 {
244 pxa2xx_pic_update(opaque);
245 return 0;
246 }
247
248 DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env)
249 {
250 DeviceState *dev = qdev_create(NULL, "pxa2xx_pic");
251 PXA2xxPICState *s = FROM_SYSBUS(PXA2xxPICState, sysbus_from_qdev(dev));
252
253 s->cpu_env = env;
254
255 s->int_pending[0] = 0;
256 s->int_pending[1] = 0;
257 s->int_enabled[0] = 0;
258 s->int_enabled[1] = 0;
259 s->is_fiq[0] = 0;
260 s->is_fiq[1] = 0;
261
262 qdev_init_nofail(dev);
263
264 qdev_init_gpio_in(dev, pxa2xx_pic_set_irq, PXA2XX_PIC_SRCS);
265
266 /* Enable IC memory-mapped registers access. */
267 memory_region_init_io(&s->iomem, &pxa2xx_pic_ops, s,
268 "pxa2xx-pic", 0x00100000);
269 sysbus_init_mmio(sysbus_from_qdev(dev), &s->iomem);
270 sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
271
272 /* Enable IC coprocessor access. */
273 cpu_arm_set_cp_io(env, 6, pxa2xx_pic_cp_read, pxa2xx_pic_cp_write, s);
274
275 return dev;
276 }
277
278 static VMStateDescription vmstate_pxa2xx_pic_regs = {
279 .name = "pxa2xx_pic",
280 .version_id = 0,
281 .minimum_version_id = 0,
282 .minimum_version_id_old = 0,
283 .post_load = pxa2xx_pic_post_load,
284 .fields = (VMStateField[]) {
285 VMSTATE_UINT32_ARRAY(int_enabled, PXA2xxPICState, 2),
286 VMSTATE_UINT32_ARRAY(int_pending, PXA2xxPICState, 2),
287 VMSTATE_UINT32_ARRAY(is_fiq, PXA2xxPICState, 2),
288 VMSTATE_UINT32(int_idle, PXA2xxPICState),
289 VMSTATE_UINT32_ARRAY(priority, PXA2xxPICState, PXA2XX_PIC_SRCS),
290 VMSTATE_END_OF_LIST(),
291 },
292 };
293
294 static int pxa2xx_pic_initfn(SysBusDevice *dev)
295 {
296 return 0;
297 }
298
299 static void pxa2xx_pic_class_init(ObjectClass *klass, void *data)
300 {
301 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
302
303 k->init = pxa2xx_pic_initfn;
304 }
305
306 static DeviceInfo pxa2xx_pic_info = {
307 .name = "pxa2xx_pic",
308 .desc = "PXA2xx PIC",
309 .size = sizeof(PXA2xxPICState),
310 .vmsd = &vmstate_pxa2xx_pic_regs,
311 .class_init = pxa2xx_pic_class_init,
312 };
313
314 static void pxa2xx_pic_register(void)
315 {
316 sysbus_register_withprop(&pxa2xx_pic_info);
317 }
318 device_init(pxa2xx_pic_register);