PPC: e500: msync is 440 only, e500 has real sync
[qemu.git] / hw / qxl.c
1 /*
2 * Copyright (C) 2010 Red Hat, Inc.
3 *
4 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann
5 * maintained by Gerd Hoffmann <kraxel@redhat.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu-common.h"
22 #include "qemu-timer.h"
23 #include "qemu-queue.h"
24 #include "monitor.h"
25 #include "sysemu.h"
26
27 #include "qxl.h"
28
29 #undef SPICE_RING_PROD_ITEM
30 #define SPICE_RING_PROD_ITEM(r, ret) { \
31 typeof(r) start = r; \
32 typeof(r) end = r + 1; \
33 uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \
34 typeof(&(r)->items[prod]) m_item = &(r)->items[prod]; \
35 if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \
36 abort(); \
37 } \
38 ret = &m_item->el; \
39 }
40
41 #undef SPICE_RING_CONS_ITEM
42 #define SPICE_RING_CONS_ITEM(r, ret) { \
43 typeof(r) start = r; \
44 typeof(r) end = r + 1; \
45 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \
46 typeof(&(r)->items[cons]) m_item = &(r)->items[cons]; \
47 if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \
48 abort(); \
49 } \
50 ret = &m_item->el; \
51 }
52
53 #undef ALIGN
54 #define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1))
55
56 #define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9"
57
58 #define QXL_MODE(_x, _y, _b, _o) \
59 { .x_res = _x, \
60 .y_res = _y, \
61 .bits = _b, \
62 .stride = (_x) * (_b) / 8, \
63 .x_mili = PIXEL_SIZE * (_x), \
64 .y_mili = PIXEL_SIZE * (_y), \
65 .orientation = _o, \
66 }
67
68 #define QXL_MODE_16_32(x_res, y_res, orientation) \
69 QXL_MODE(x_res, y_res, 16, orientation), \
70 QXL_MODE(x_res, y_res, 32, orientation)
71
72 #define QXL_MODE_EX(x_res, y_res) \
73 QXL_MODE_16_32(x_res, y_res, 0), \
74 QXL_MODE_16_32(y_res, x_res, 1), \
75 QXL_MODE_16_32(x_res, y_res, 2), \
76 QXL_MODE_16_32(y_res, x_res, 3)
77
78 static QXLMode qxl_modes[] = {
79 QXL_MODE_EX(640, 480),
80 QXL_MODE_EX(800, 480),
81 QXL_MODE_EX(800, 600),
82 QXL_MODE_EX(832, 624),
83 QXL_MODE_EX(960, 640),
84 QXL_MODE_EX(1024, 600),
85 QXL_MODE_EX(1024, 768),
86 QXL_MODE_EX(1152, 864),
87 QXL_MODE_EX(1152, 870),
88 QXL_MODE_EX(1280, 720),
89 QXL_MODE_EX(1280, 760),
90 QXL_MODE_EX(1280, 768),
91 QXL_MODE_EX(1280, 800),
92 QXL_MODE_EX(1280, 960),
93 QXL_MODE_EX(1280, 1024),
94 QXL_MODE_EX(1360, 768),
95 QXL_MODE_EX(1366, 768),
96 QXL_MODE_EX(1400, 1050),
97 QXL_MODE_EX(1440, 900),
98 QXL_MODE_EX(1600, 900),
99 QXL_MODE_EX(1600, 1200),
100 QXL_MODE_EX(1680, 1050),
101 QXL_MODE_EX(1920, 1080),
102 #if VGA_RAM_SIZE >= (16 * 1024 * 1024)
103 /* these modes need more than 8 MB video memory */
104 QXL_MODE_EX(1920, 1200),
105 QXL_MODE_EX(1920, 1440),
106 QXL_MODE_EX(2048, 1536),
107 QXL_MODE_EX(2560, 1440),
108 QXL_MODE_EX(2560, 1600),
109 #endif
110 #if VGA_RAM_SIZE >= (32 * 1024 * 1024)
111 /* these modes need more than 16 MB video memory */
112 QXL_MODE_EX(2560, 2048),
113 QXL_MODE_EX(2800, 2100),
114 QXL_MODE_EX(3200, 2400),
115 #endif
116 };
117
118 static PCIQXLDevice *qxl0;
119
120 static void qxl_send_events(PCIQXLDevice *d, uint32_t events);
121 static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async);
122 static void qxl_reset_memslots(PCIQXLDevice *d);
123 static void qxl_reset_surfaces(PCIQXLDevice *d);
124 static void qxl_ring_set_dirty(PCIQXLDevice *qxl);
125
126 void qxl_guest_bug(PCIQXLDevice *qxl, const char *msg, ...)
127 {
128 #if SPICE_INTERFACE_QXL_MINOR >= 1
129 qxl_send_events(qxl, QXL_INTERRUPT_ERROR);
130 #endif
131 if (qxl->guestdebug) {
132 va_list ap;
133 va_start(ap, msg);
134 fprintf(stderr, "qxl-%d: guest bug: ", qxl->id);
135 vfprintf(stderr, msg, ap);
136 fprintf(stderr, "\n");
137 va_end(ap);
138 }
139 }
140
141
142 void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id,
143 struct QXLRect *area, struct QXLRect *dirty_rects,
144 uint32_t num_dirty_rects,
145 uint32_t clear_dirty_region,
146 qxl_async_io async)
147 {
148 if (async == QXL_SYNC) {
149 qxl->ssd.worker->update_area(qxl->ssd.worker, surface_id, area,
150 dirty_rects, num_dirty_rects, clear_dirty_region);
151 } else {
152 #if SPICE_INTERFACE_QXL_MINOR >= 1
153 spice_qxl_update_area_async(&qxl->ssd.qxl, surface_id, area,
154 clear_dirty_region, 0);
155 #else
156 abort();
157 #endif
158 }
159 }
160
161 static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice *qxl,
162 uint32_t id)
163 {
164 qemu_mutex_lock(&qxl->track_lock);
165 qxl->guest_surfaces.cmds[id] = 0;
166 qxl->guest_surfaces.count--;
167 qemu_mutex_unlock(&qxl->track_lock);
168 }
169
170 static void qxl_spice_destroy_surface_wait(PCIQXLDevice *qxl, uint32_t id,
171 qxl_async_io async)
172 {
173 if (async) {
174 #if SPICE_INTERFACE_QXL_MINOR < 1
175 abort();
176 #else
177 spice_qxl_destroy_surface_async(&qxl->ssd.qxl, id,
178 (uint64_t)id);
179 #endif
180 } else {
181 qxl->ssd.worker->destroy_surface_wait(qxl->ssd.worker, id);
182 qxl_spice_destroy_surface_wait_complete(qxl, id);
183 }
184 }
185
186 #if SPICE_INTERFACE_QXL_MINOR >= 1
187 static void qxl_spice_flush_surfaces_async(PCIQXLDevice *qxl)
188 {
189 spice_qxl_flush_surfaces_async(&qxl->ssd.qxl, 0);
190 }
191 #endif
192
193 void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext,
194 uint32_t count)
195 {
196 qxl->ssd.worker->loadvm_commands(qxl->ssd.worker, ext, count);
197 }
198
199 void qxl_spice_oom(PCIQXLDevice *qxl)
200 {
201 qxl->ssd.worker->oom(qxl->ssd.worker);
202 }
203
204 void qxl_spice_reset_memslots(PCIQXLDevice *qxl)
205 {
206 qxl->ssd.worker->reset_memslots(qxl->ssd.worker);
207 }
208
209 static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice *qxl)
210 {
211 qemu_mutex_lock(&qxl->track_lock);
212 memset(&qxl->guest_surfaces.cmds, 0, sizeof(qxl->guest_surfaces.cmds));
213 qxl->guest_surfaces.count = 0;
214 qemu_mutex_unlock(&qxl->track_lock);
215 }
216
217 static void qxl_spice_destroy_surfaces(PCIQXLDevice *qxl, qxl_async_io async)
218 {
219 if (async) {
220 #if SPICE_INTERFACE_QXL_MINOR < 1
221 abort();
222 #else
223 spice_qxl_destroy_surfaces_async(&qxl->ssd.qxl, 0);
224 #endif
225 } else {
226 qxl->ssd.worker->destroy_surfaces(qxl->ssd.worker);
227 qxl_spice_destroy_surfaces_complete(qxl);
228 }
229 }
230
231 void qxl_spice_reset_image_cache(PCIQXLDevice *qxl)
232 {
233 qxl->ssd.worker->reset_image_cache(qxl->ssd.worker);
234 }
235
236 void qxl_spice_reset_cursor(PCIQXLDevice *qxl)
237 {
238 qxl->ssd.worker->reset_cursor(qxl->ssd.worker);
239 qemu_mutex_lock(&qxl->track_lock);
240 qxl->guest_cursor = 0;
241 qemu_mutex_unlock(&qxl->track_lock);
242 }
243
244
245 static inline uint32_t msb_mask(uint32_t val)
246 {
247 uint32_t mask;
248
249 do {
250 mask = ~(val - 1) & val;
251 val &= ~mask;
252 } while (mask < val);
253
254 return mask;
255 }
256
257 static ram_addr_t qxl_rom_size(void)
258 {
259 uint32_t rom_size = sizeof(QXLRom) + sizeof(QXLModes) + sizeof(qxl_modes);
260 rom_size = MAX(rom_size, TARGET_PAGE_SIZE);
261 rom_size = msb_mask(rom_size * 2 - 1);
262 return rom_size;
263 }
264
265 static void init_qxl_rom(PCIQXLDevice *d)
266 {
267 QXLRom *rom = memory_region_get_ram_ptr(&d->rom_bar);
268 QXLModes *modes = (QXLModes *)(rom + 1);
269 uint32_t ram_header_size;
270 uint32_t surface0_area_size;
271 uint32_t num_pages;
272 uint32_t fb, maxfb = 0;
273 int i;
274
275 memset(rom, 0, d->rom_size);
276
277 rom->magic = cpu_to_le32(QXL_ROM_MAGIC);
278 rom->id = cpu_to_le32(d->id);
279 rom->log_level = cpu_to_le32(d->guestdebug);
280 rom->modes_offset = cpu_to_le32(sizeof(QXLRom));
281
282 rom->slot_gen_bits = MEMSLOT_GENERATION_BITS;
283 rom->slot_id_bits = MEMSLOT_SLOT_BITS;
284 rom->slots_start = 1;
285 rom->slots_end = NUM_MEMSLOTS - 1;
286 rom->n_surfaces = cpu_to_le32(NUM_SURFACES);
287
288 modes->n_modes = cpu_to_le32(ARRAY_SIZE(qxl_modes));
289 for (i = 0; i < modes->n_modes; i++) {
290 fb = qxl_modes[i].y_res * qxl_modes[i].stride;
291 if (maxfb < fb) {
292 maxfb = fb;
293 }
294 modes->modes[i].id = cpu_to_le32(i);
295 modes->modes[i].x_res = cpu_to_le32(qxl_modes[i].x_res);
296 modes->modes[i].y_res = cpu_to_le32(qxl_modes[i].y_res);
297 modes->modes[i].bits = cpu_to_le32(qxl_modes[i].bits);
298 modes->modes[i].stride = cpu_to_le32(qxl_modes[i].stride);
299 modes->modes[i].x_mili = cpu_to_le32(qxl_modes[i].x_mili);
300 modes->modes[i].y_mili = cpu_to_le32(qxl_modes[i].y_mili);
301 modes->modes[i].orientation = cpu_to_le32(qxl_modes[i].orientation);
302 }
303 if (maxfb < VGA_RAM_SIZE && d->id == 0)
304 maxfb = VGA_RAM_SIZE;
305
306 ram_header_size = ALIGN(sizeof(QXLRam), 4096);
307 surface0_area_size = ALIGN(maxfb, 4096);
308 num_pages = d->vga.vram_size;
309 num_pages -= ram_header_size;
310 num_pages -= surface0_area_size;
311 num_pages = num_pages / TARGET_PAGE_SIZE;
312
313 rom->draw_area_offset = cpu_to_le32(0);
314 rom->surface0_area_size = cpu_to_le32(surface0_area_size);
315 rom->pages_offset = cpu_to_le32(surface0_area_size);
316 rom->num_pages = cpu_to_le32(num_pages);
317 rom->ram_header_offset = cpu_to_le32(d->vga.vram_size - ram_header_size);
318
319 d->shadow_rom = *rom;
320 d->rom = rom;
321 d->modes = modes;
322 }
323
324 static void init_qxl_ram(PCIQXLDevice *d)
325 {
326 uint8_t *buf;
327 uint64_t *item;
328
329 buf = d->vga.vram_ptr;
330 d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset));
331 d->ram->magic = cpu_to_le32(QXL_RAM_MAGIC);
332 d->ram->int_pending = cpu_to_le32(0);
333 d->ram->int_mask = cpu_to_le32(0);
334 d->ram->update_surface = 0;
335 SPICE_RING_INIT(&d->ram->cmd_ring);
336 SPICE_RING_INIT(&d->ram->cursor_ring);
337 SPICE_RING_INIT(&d->ram->release_ring);
338 SPICE_RING_PROD_ITEM(&d->ram->release_ring, item);
339 *item = 0;
340 qxl_ring_set_dirty(d);
341 }
342
343 /* can be called from spice server thread context */
344 static void qxl_set_dirty(MemoryRegion *mr, ram_addr_t addr, ram_addr_t end)
345 {
346 memory_region_set_dirty(mr, addr, end - addr);
347 }
348
349 static void qxl_rom_set_dirty(PCIQXLDevice *qxl)
350 {
351 qxl_set_dirty(&qxl->rom_bar, 0, qxl->rom_size);
352 }
353
354 /* called from spice server thread context only */
355 static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr)
356 {
357 void *base = qxl->vga.vram_ptr;
358 intptr_t offset;
359
360 offset = ptr - base;
361 offset &= ~(TARGET_PAGE_SIZE-1);
362 assert(offset < qxl->vga.vram_size);
363 qxl_set_dirty(&qxl->vga.vram, offset, offset + TARGET_PAGE_SIZE);
364 }
365
366 /* can be called from spice server thread context */
367 static void qxl_ring_set_dirty(PCIQXLDevice *qxl)
368 {
369 ram_addr_t addr = qxl->shadow_rom.ram_header_offset;
370 ram_addr_t end = qxl->vga.vram_size;
371 qxl_set_dirty(&qxl->vga.vram, addr, end);
372 }
373
374 /*
375 * keep track of some command state, for savevm/loadvm.
376 * called from spice server thread context only
377 */
378 static void qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext)
379 {
380 switch (le32_to_cpu(ext->cmd.type)) {
381 case QXL_CMD_SURFACE:
382 {
383 QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
384 uint32_t id = le32_to_cpu(cmd->surface_id);
385 PANIC_ON(id >= NUM_SURFACES);
386 qemu_mutex_lock(&qxl->track_lock);
387 if (cmd->type == QXL_SURFACE_CMD_CREATE) {
388 qxl->guest_surfaces.cmds[id] = ext->cmd.data;
389 qxl->guest_surfaces.count++;
390 if (qxl->guest_surfaces.max < qxl->guest_surfaces.count)
391 qxl->guest_surfaces.max = qxl->guest_surfaces.count;
392 }
393 if (cmd->type == QXL_SURFACE_CMD_DESTROY) {
394 qxl->guest_surfaces.cmds[id] = 0;
395 qxl->guest_surfaces.count--;
396 }
397 qemu_mutex_unlock(&qxl->track_lock);
398 break;
399 }
400 case QXL_CMD_CURSOR:
401 {
402 QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
403 if (cmd->type == QXL_CURSOR_SET) {
404 qemu_mutex_lock(&qxl->track_lock);
405 qxl->guest_cursor = ext->cmd.data;
406 qemu_mutex_unlock(&qxl->track_lock);
407 }
408 break;
409 }
410 }
411 }
412
413 /* spice display interface callbacks */
414
415 static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker)
416 {
417 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
418
419 dprint(qxl, 1, "%s:\n", __FUNCTION__);
420 qxl->ssd.worker = qxl_worker;
421 }
422
423 static void interface_set_compression_level(QXLInstance *sin, int level)
424 {
425 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
426
427 dprint(qxl, 1, "%s: %d\n", __FUNCTION__, level);
428 qxl->shadow_rom.compression_level = cpu_to_le32(level);
429 qxl->rom->compression_level = cpu_to_le32(level);
430 qxl_rom_set_dirty(qxl);
431 }
432
433 static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time)
434 {
435 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
436
437 qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time);
438 qxl->rom->mm_clock = cpu_to_le32(mm_time);
439 qxl_rom_set_dirty(qxl);
440 }
441
442 static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info)
443 {
444 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
445
446 dprint(qxl, 1, "%s:\n", __FUNCTION__);
447 info->memslot_gen_bits = MEMSLOT_GENERATION_BITS;
448 info->memslot_id_bits = MEMSLOT_SLOT_BITS;
449 info->num_memslots = NUM_MEMSLOTS;
450 info->num_memslots_groups = NUM_MEMSLOTS_GROUPS;
451 info->internal_groupslot_id = 0;
452 info->qxl_ram_size = le32_to_cpu(qxl->shadow_rom.num_pages) << TARGET_PAGE_BITS;
453 info->n_surfaces = NUM_SURFACES;
454 }
455
456 static const char *qxl_mode_to_string(int mode)
457 {
458 switch (mode) {
459 case QXL_MODE_COMPAT:
460 return "compat";
461 case QXL_MODE_NATIVE:
462 return "native";
463 case QXL_MODE_UNDEFINED:
464 return "undefined";
465 case QXL_MODE_VGA:
466 return "vga";
467 }
468 return "INVALID";
469 }
470
471 static const char *io_port_to_string(uint32_t io_port)
472 {
473 if (io_port >= QXL_IO_RANGE_SIZE) {
474 return "out of range";
475 }
476 static const char *io_port_to_string[QXL_IO_RANGE_SIZE + 1] = {
477 [QXL_IO_NOTIFY_CMD] = "QXL_IO_NOTIFY_CMD",
478 [QXL_IO_NOTIFY_CURSOR] = "QXL_IO_NOTIFY_CURSOR",
479 [QXL_IO_UPDATE_AREA] = "QXL_IO_UPDATE_AREA",
480 [QXL_IO_UPDATE_IRQ] = "QXL_IO_UPDATE_IRQ",
481 [QXL_IO_NOTIFY_OOM] = "QXL_IO_NOTIFY_OOM",
482 [QXL_IO_RESET] = "QXL_IO_RESET",
483 [QXL_IO_SET_MODE] = "QXL_IO_SET_MODE",
484 [QXL_IO_LOG] = "QXL_IO_LOG",
485 [QXL_IO_MEMSLOT_ADD] = "QXL_IO_MEMSLOT_ADD",
486 [QXL_IO_MEMSLOT_DEL] = "QXL_IO_MEMSLOT_DEL",
487 [QXL_IO_DETACH_PRIMARY] = "QXL_IO_DETACH_PRIMARY",
488 [QXL_IO_ATTACH_PRIMARY] = "QXL_IO_ATTACH_PRIMARY",
489 [QXL_IO_CREATE_PRIMARY] = "QXL_IO_CREATE_PRIMARY",
490 [QXL_IO_DESTROY_PRIMARY] = "QXL_IO_DESTROY_PRIMARY",
491 [QXL_IO_DESTROY_SURFACE_WAIT] = "QXL_IO_DESTROY_SURFACE_WAIT",
492 [QXL_IO_DESTROY_ALL_SURFACES] = "QXL_IO_DESTROY_ALL_SURFACES",
493 #if SPICE_INTERFACE_QXL_MINOR >= 1
494 [QXL_IO_UPDATE_AREA_ASYNC] = "QXL_IO_UPDATE_AREA_ASYNC",
495 [QXL_IO_MEMSLOT_ADD_ASYNC] = "QXL_IO_MEMSLOT_ADD_ASYNC",
496 [QXL_IO_CREATE_PRIMARY_ASYNC] = "QXL_IO_CREATE_PRIMARY_ASYNC",
497 [QXL_IO_DESTROY_PRIMARY_ASYNC] = "QXL_IO_DESTROY_PRIMARY_ASYNC",
498 [QXL_IO_DESTROY_SURFACE_ASYNC] = "QXL_IO_DESTROY_SURFACE_ASYNC",
499 [QXL_IO_DESTROY_ALL_SURFACES_ASYNC]
500 = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC",
501 [QXL_IO_FLUSH_SURFACES_ASYNC] = "QXL_IO_FLUSH_SURFACES_ASYNC",
502 [QXL_IO_FLUSH_RELEASE] = "QXL_IO_FLUSH_RELEASE",
503 #endif
504 };
505 return io_port_to_string[io_port];
506 }
507
508 /* called from spice server thread context only */
509 static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext)
510 {
511 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
512 SimpleSpiceUpdate *update;
513 QXLCommandRing *ring;
514 QXLCommand *cmd;
515 int notify, ret;
516
517 switch (qxl->mode) {
518 case QXL_MODE_VGA:
519 dprint(qxl, 2, "%s: vga\n", __FUNCTION__);
520 ret = false;
521 qemu_mutex_lock(&qxl->ssd.lock);
522 if (qxl->ssd.update != NULL) {
523 update = qxl->ssd.update;
524 qxl->ssd.update = NULL;
525 *ext = update->ext;
526 ret = true;
527 }
528 qemu_mutex_unlock(&qxl->ssd.lock);
529 if (ret) {
530 dprint(qxl, 2, "%s %s\n", __FUNCTION__, qxl_mode_to_string(qxl->mode));
531 qxl_log_command(qxl, "vga", ext);
532 }
533 return ret;
534 case QXL_MODE_COMPAT:
535 case QXL_MODE_NATIVE:
536 case QXL_MODE_UNDEFINED:
537 dprint(qxl, 4, "%s: %s\n", __FUNCTION__, qxl_mode_to_string(qxl->mode));
538 ring = &qxl->ram->cmd_ring;
539 if (SPICE_RING_IS_EMPTY(ring)) {
540 return false;
541 }
542 dprint(qxl, 2, "%s: %s\n", __FUNCTION__, qxl_mode_to_string(qxl->mode));
543 SPICE_RING_CONS_ITEM(ring, cmd);
544 ext->cmd = *cmd;
545 ext->group_id = MEMSLOT_GROUP_GUEST;
546 ext->flags = qxl->cmdflags;
547 SPICE_RING_POP(ring, notify);
548 qxl_ring_set_dirty(qxl);
549 if (notify) {
550 qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY);
551 }
552 qxl->guest_primary.commands++;
553 qxl_track_command(qxl, ext);
554 qxl_log_command(qxl, "cmd", ext);
555 return true;
556 default:
557 return false;
558 }
559 }
560
561 /* called from spice server thread context only */
562 static int interface_req_cmd_notification(QXLInstance *sin)
563 {
564 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
565 int wait = 1;
566
567 switch (qxl->mode) {
568 case QXL_MODE_COMPAT:
569 case QXL_MODE_NATIVE:
570 case QXL_MODE_UNDEFINED:
571 SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait);
572 qxl_ring_set_dirty(qxl);
573 break;
574 default:
575 /* nothing */
576 break;
577 }
578 return wait;
579 }
580
581 /* called from spice server thread context only */
582 static inline void qxl_push_free_res(PCIQXLDevice *d, int flush)
583 {
584 QXLReleaseRing *ring = &d->ram->release_ring;
585 uint64_t *item;
586 int notify;
587
588 #define QXL_FREE_BUNCH_SIZE 32
589
590 if (ring->prod - ring->cons + 1 == ring->num_items) {
591 /* ring full -- can't push */
592 return;
593 }
594 if (!flush && d->oom_running) {
595 /* collect everything from oom handler before pushing */
596 return;
597 }
598 if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) {
599 /* collect a bit more before pushing */
600 return;
601 }
602
603 SPICE_RING_PUSH(ring, notify);
604 dprint(d, 2, "free: push %d items, notify %s, ring %d/%d [%d,%d]\n",
605 d->num_free_res, notify ? "yes" : "no",
606 ring->prod - ring->cons, ring->num_items,
607 ring->prod, ring->cons);
608 if (notify) {
609 qxl_send_events(d, QXL_INTERRUPT_DISPLAY);
610 }
611 SPICE_RING_PROD_ITEM(ring, item);
612 *item = 0;
613 d->num_free_res = 0;
614 d->last_release = NULL;
615 qxl_ring_set_dirty(d);
616 }
617
618 /* called from spice server thread context only */
619 static void interface_release_resource(QXLInstance *sin,
620 struct QXLReleaseInfoExt ext)
621 {
622 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
623 QXLReleaseRing *ring;
624 uint64_t *item, id;
625
626 if (ext.group_id == MEMSLOT_GROUP_HOST) {
627 /* host group -> vga mode update request */
628 qemu_spice_destroy_update(&qxl->ssd, (void*)ext.info->id);
629 return;
630 }
631
632 /*
633 * ext->info points into guest-visible memory
634 * pci bar 0, $command.release_info
635 */
636 ring = &qxl->ram->release_ring;
637 SPICE_RING_PROD_ITEM(ring, item);
638 if (*item == 0) {
639 /* stick head into the ring */
640 id = ext.info->id;
641 ext.info->next = 0;
642 qxl_ram_set_dirty(qxl, &ext.info->next);
643 *item = id;
644 qxl_ring_set_dirty(qxl);
645 } else {
646 /* append item to the list */
647 qxl->last_release->next = ext.info->id;
648 qxl_ram_set_dirty(qxl, &qxl->last_release->next);
649 ext.info->next = 0;
650 qxl_ram_set_dirty(qxl, &ext.info->next);
651 }
652 qxl->last_release = ext.info;
653 qxl->num_free_res++;
654 dprint(qxl, 3, "%4d\r", qxl->num_free_res);
655 qxl_push_free_res(qxl, 0);
656 }
657
658 /* called from spice server thread context only */
659 static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext)
660 {
661 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
662 QXLCursorRing *ring;
663 QXLCommand *cmd;
664 int notify;
665
666 switch (qxl->mode) {
667 case QXL_MODE_COMPAT:
668 case QXL_MODE_NATIVE:
669 case QXL_MODE_UNDEFINED:
670 ring = &qxl->ram->cursor_ring;
671 if (SPICE_RING_IS_EMPTY(ring)) {
672 return false;
673 }
674 SPICE_RING_CONS_ITEM(ring, cmd);
675 ext->cmd = *cmd;
676 ext->group_id = MEMSLOT_GROUP_GUEST;
677 ext->flags = qxl->cmdflags;
678 SPICE_RING_POP(ring, notify);
679 qxl_ring_set_dirty(qxl);
680 if (notify) {
681 qxl_send_events(qxl, QXL_INTERRUPT_CURSOR);
682 }
683 qxl->guest_primary.commands++;
684 qxl_track_command(qxl, ext);
685 qxl_log_command(qxl, "csr", ext);
686 if (qxl->id == 0) {
687 qxl_render_cursor(qxl, ext);
688 }
689 return true;
690 default:
691 return false;
692 }
693 }
694
695 /* called from spice server thread context only */
696 static int interface_req_cursor_notification(QXLInstance *sin)
697 {
698 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
699 int wait = 1;
700
701 switch (qxl->mode) {
702 case QXL_MODE_COMPAT:
703 case QXL_MODE_NATIVE:
704 case QXL_MODE_UNDEFINED:
705 SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait);
706 qxl_ring_set_dirty(qxl);
707 break;
708 default:
709 /* nothing */
710 break;
711 }
712 return wait;
713 }
714
715 /* called from spice server thread context */
716 static void interface_notify_update(QXLInstance *sin, uint32_t update_id)
717 {
718 fprintf(stderr, "%s: abort()\n", __FUNCTION__);
719 abort();
720 }
721
722 /* called from spice server thread context only */
723 static int interface_flush_resources(QXLInstance *sin)
724 {
725 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
726 int ret;
727
728 dprint(qxl, 1, "free: guest flush (have %d)\n", qxl->num_free_res);
729 ret = qxl->num_free_res;
730 if (ret) {
731 qxl_push_free_res(qxl, 1);
732 }
733 return ret;
734 }
735
736 static void qxl_create_guest_primary_complete(PCIQXLDevice *d);
737
738 #if SPICE_INTERFACE_QXL_MINOR >= 1
739
740 /* called from spice server thread context only */
741 static void interface_async_complete(QXLInstance *sin, uint64_t cookie)
742 {
743 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
744 uint32_t current_async;
745
746 qemu_mutex_lock(&qxl->async_lock);
747 current_async = qxl->current_async;
748 qxl->current_async = QXL_UNDEFINED_IO;
749 qemu_mutex_unlock(&qxl->async_lock);
750
751 dprint(qxl, 2, "async_complete: %d (%ld) done\n", current_async, cookie);
752 switch (current_async) {
753 case QXL_IO_CREATE_PRIMARY_ASYNC:
754 qxl_create_guest_primary_complete(qxl);
755 break;
756 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
757 qxl_spice_destroy_surfaces_complete(qxl);
758 break;
759 case QXL_IO_DESTROY_SURFACE_ASYNC:
760 qxl_spice_destroy_surface_wait_complete(qxl, (uint32_t)cookie);
761 break;
762 }
763 qxl_send_events(qxl, QXL_INTERRUPT_IO_CMD);
764 }
765
766 #endif
767
768 static const QXLInterface qxl_interface = {
769 .base.type = SPICE_INTERFACE_QXL,
770 .base.description = "qxl gpu",
771 .base.major_version = SPICE_INTERFACE_QXL_MAJOR,
772 .base.minor_version = SPICE_INTERFACE_QXL_MINOR,
773
774 .attache_worker = interface_attach_worker,
775 .set_compression_level = interface_set_compression_level,
776 .set_mm_time = interface_set_mm_time,
777 .get_init_info = interface_get_init_info,
778
779 /* the callbacks below are called from spice server thread context */
780 .get_command = interface_get_command,
781 .req_cmd_notification = interface_req_cmd_notification,
782 .release_resource = interface_release_resource,
783 .get_cursor_command = interface_get_cursor_command,
784 .req_cursor_notification = interface_req_cursor_notification,
785 .notify_update = interface_notify_update,
786 .flush_resources = interface_flush_resources,
787 #if SPICE_INTERFACE_QXL_MINOR >= 1
788 .async_complete = interface_async_complete,
789 #endif
790 };
791
792 static void qxl_enter_vga_mode(PCIQXLDevice *d)
793 {
794 if (d->mode == QXL_MODE_VGA) {
795 return;
796 }
797 dprint(d, 1, "%s\n", __FUNCTION__);
798 qemu_spice_create_host_primary(&d->ssd);
799 d->mode = QXL_MODE_VGA;
800 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
801 }
802
803 static void qxl_exit_vga_mode(PCIQXLDevice *d)
804 {
805 if (d->mode != QXL_MODE_VGA) {
806 return;
807 }
808 dprint(d, 1, "%s\n", __FUNCTION__);
809 qxl_destroy_primary(d, QXL_SYNC);
810 }
811
812 static void qxl_update_irq(PCIQXLDevice *d)
813 {
814 uint32_t pending = le32_to_cpu(d->ram->int_pending);
815 uint32_t mask = le32_to_cpu(d->ram->int_mask);
816 int level = !!(pending & mask);
817 qemu_set_irq(d->pci.irq[0], level);
818 qxl_ring_set_dirty(d);
819 }
820
821 static void qxl_check_state(PCIQXLDevice *d)
822 {
823 QXLRam *ram = d->ram;
824
825 assert(!d->ssd.running || SPICE_RING_IS_EMPTY(&ram->cmd_ring));
826 assert(!d->ssd.running || SPICE_RING_IS_EMPTY(&ram->cursor_ring));
827 }
828
829 static void qxl_reset_state(PCIQXLDevice *d)
830 {
831 QXLRom *rom = d->rom;
832
833 qxl_check_state(d);
834 d->shadow_rom.update_id = cpu_to_le32(0);
835 *rom = d->shadow_rom;
836 qxl_rom_set_dirty(d);
837 init_qxl_ram(d);
838 d->num_free_res = 0;
839 d->last_release = NULL;
840 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
841 }
842
843 static void qxl_soft_reset(PCIQXLDevice *d)
844 {
845 dprint(d, 1, "%s:\n", __FUNCTION__);
846 qxl_check_state(d);
847
848 if (d->id == 0) {
849 qxl_enter_vga_mode(d);
850 } else {
851 d->mode = QXL_MODE_UNDEFINED;
852 }
853 }
854
855 static void qxl_hard_reset(PCIQXLDevice *d, int loadvm)
856 {
857 dprint(d, 1, "%s: start%s\n", __FUNCTION__,
858 loadvm ? " (loadvm)" : "");
859
860 qxl_spice_reset_cursor(d);
861 qxl_spice_reset_image_cache(d);
862 qxl_reset_surfaces(d);
863 qxl_reset_memslots(d);
864
865 /* pre loadvm reset must not touch QXLRam. This lives in
866 * device memory, is migrated together with RAM and thus
867 * already loaded at this point */
868 if (!loadvm) {
869 qxl_reset_state(d);
870 }
871 qemu_spice_create_host_memslot(&d->ssd);
872 qxl_soft_reset(d);
873
874 dprint(d, 1, "%s: done\n", __FUNCTION__);
875 }
876
877 static void qxl_reset_handler(DeviceState *dev)
878 {
879 PCIQXLDevice *d = DO_UPCAST(PCIQXLDevice, pci.qdev, dev);
880 qxl_hard_reset(d, 0);
881 }
882
883 static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
884 {
885 VGACommonState *vga = opaque;
886 PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga);
887
888 if (qxl->mode != QXL_MODE_VGA) {
889 dprint(qxl, 1, "%s\n", __FUNCTION__);
890 qxl_destroy_primary(qxl, QXL_SYNC);
891 qxl_soft_reset(qxl);
892 }
893 vga_ioport_write(opaque, addr, val);
894 }
895
896 static const MemoryRegionPortio qxl_vga_portio_list[] = {
897 { 0x04, 2, 1, .read = vga_ioport_read,
898 .write = qxl_vga_ioport_write }, /* 3b4 */
899 { 0x0a, 1, 1, .read = vga_ioport_read,
900 .write = qxl_vga_ioport_write }, /* 3ba */
901 { 0x10, 16, 1, .read = vga_ioport_read,
902 .write = qxl_vga_ioport_write }, /* 3c0 */
903 { 0x24, 2, 1, .read = vga_ioport_read,
904 .write = qxl_vga_ioport_write }, /* 3d4 */
905 { 0x2a, 1, 1, .read = vga_ioport_read,
906 .write = qxl_vga_ioport_write }, /* 3da */
907 PORTIO_END_OF_LIST(),
908 };
909
910 static void qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta,
911 qxl_async_io async)
912 {
913 static const int regions[] = {
914 QXL_RAM_RANGE_INDEX,
915 QXL_VRAM_RANGE_INDEX,
916 };
917 uint64_t guest_start;
918 uint64_t guest_end;
919 int pci_region;
920 pcibus_t pci_start;
921 pcibus_t pci_end;
922 intptr_t virt_start;
923 QXLDevMemSlot memslot;
924 int i;
925
926 guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start);
927 guest_end = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end);
928
929 dprint(d, 1, "%s: slot %d: guest phys 0x%" PRIx64 " - 0x%" PRIx64 "\n",
930 __FUNCTION__, slot_id,
931 guest_start, guest_end);
932
933 PANIC_ON(slot_id >= NUM_MEMSLOTS);
934 PANIC_ON(guest_start > guest_end);
935
936 for (i = 0; i < ARRAY_SIZE(regions); i++) {
937 pci_region = regions[i];
938 pci_start = d->pci.io_regions[pci_region].addr;
939 pci_end = pci_start + d->pci.io_regions[pci_region].size;
940 /* mapped? */
941 if (pci_start == -1) {
942 continue;
943 }
944 /* start address in range ? */
945 if (guest_start < pci_start || guest_start > pci_end) {
946 continue;
947 }
948 /* end address in range ? */
949 if (guest_end > pci_end) {
950 continue;
951 }
952 /* passed */
953 break;
954 }
955 PANIC_ON(i == ARRAY_SIZE(regions)); /* finished loop without match */
956
957 switch (pci_region) {
958 case QXL_RAM_RANGE_INDEX:
959 virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vga.vram);
960 break;
961 case QXL_VRAM_RANGE_INDEX:
962 virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vram_bar);
963 break;
964 default:
965 /* should not happen */
966 abort();
967 }
968
969 memslot.slot_id = slot_id;
970 memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */
971 memslot.virt_start = virt_start + (guest_start - pci_start);
972 memslot.virt_end = virt_start + (guest_end - pci_start);
973 memslot.addr_delta = memslot.virt_start - delta;
974 memslot.generation = d->rom->slot_generation = 0;
975 qxl_rom_set_dirty(d);
976
977 dprint(d, 1, "%s: slot %d: host virt 0x%lx - 0x%lx\n",
978 __FUNCTION__, memslot.slot_id,
979 memslot.virt_start, memslot.virt_end);
980
981 qemu_spice_add_memslot(&d->ssd, &memslot, async);
982 d->guest_slots[slot_id].ptr = (void*)memslot.virt_start;
983 d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start;
984 d->guest_slots[slot_id].delta = delta;
985 d->guest_slots[slot_id].active = 1;
986 }
987
988 static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id)
989 {
990 dprint(d, 1, "%s: slot %d\n", __FUNCTION__, slot_id);
991 qemu_spice_del_memslot(&d->ssd, MEMSLOT_GROUP_HOST, slot_id);
992 d->guest_slots[slot_id].active = 0;
993 }
994
995 static void qxl_reset_memslots(PCIQXLDevice *d)
996 {
997 dprint(d, 1, "%s:\n", __FUNCTION__);
998 qxl_spice_reset_memslots(d);
999 memset(&d->guest_slots, 0, sizeof(d->guest_slots));
1000 }
1001
1002 static void qxl_reset_surfaces(PCIQXLDevice *d)
1003 {
1004 dprint(d, 1, "%s:\n", __FUNCTION__);
1005 d->mode = QXL_MODE_UNDEFINED;
1006 qxl_spice_destroy_surfaces(d, QXL_SYNC);
1007 }
1008
1009 /* called from spice server thread context only */
1010 void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id)
1011 {
1012 uint64_t phys = le64_to_cpu(pqxl);
1013 uint32_t slot = (phys >> (64 - 8)) & 0xff;
1014 uint64_t offset = phys & 0xffffffffffff;
1015
1016 switch (group_id) {
1017 case MEMSLOT_GROUP_HOST:
1018 return (void*)offset;
1019 case MEMSLOT_GROUP_GUEST:
1020 PANIC_ON(slot >= NUM_MEMSLOTS);
1021 PANIC_ON(!qxl->guest_slots[slot].active);
1022 PANIC_ON(offset < qxl->guest_slots[slot].delta);
1023 offset -= qxl->guest_slots[slot].delta;
1024 PANIC_ON(offset > qxl->guest_slots[slot].size)
1025 return qxl->guest_slots[slot].ptr + offset;
1026 default:
1027 PANIC_ON(1);
1028 }
1029 }
1030
1031 static void qxl_create_guest_primary_complete(PCIQXLDevice *qxl)
1032 {
1033 /* for local rendering */
1034 qxl_render_resize(qxl);
1035 }
1036
1037 static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm,
1038 qxl_async_io async)
1039 {
1040 QXLDevSurfaceCreate surface;
1041 QXLSurfaceCreate *sc = &qxl->guest_primary.surface;
1042
1043 assert(qxl->mode != QXL_MODE_NATIVE);
1044 qxl_exit_vga_mode(qxl);
1045
1046 dprint(qxl, 1, "%s: %dx%d\n", __FUNCTION__,
1047 le32_to_cpu(sc->width), le32_to_cpu(sc->height));
1048
1049 surface.format = le32_to_cpu(sc->format);
1050 surface.height = le32_to_cpu(sc->height);
1051 surface.mem = le64_to_cpu(sc->mem);
1052 surface.position = le32_to_cpu(sc->position);
1053 surface.stride = le32_to_cpu(sc->stride);
1054 surface.width = le32_to_cpu(sc->width);
1055 surface.type = le32_to_cpu(sc->type);
1056 surface.flags = le32_to_cpu(sc->flags);
1057
1058 surface.mouse_mode = true;
1059 surface.group_id = MEMSLOT_GROUP_GUEST;
1060 if (loadvm) {
1061 surface.flags |= QXL_SURF_FLAG_KEEP_DATA;
1062 }
1063
1064 qxl->mode = QXL_MODE_NATIVE;
1065 qxl->cmdflags = 0;
1066 qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface, async);
1067
1068 if (async == QXL_SYNC) {
1069 qxl_create_guest_primary_complete(qxl);
1070 }
1071 }
1072
1073 /* return 1 if surface destoy was initiated (in QXL_ASYNC case) or
1074 * done (in QXL_SYNC case), 0 otherwise. */
1075 static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async)
1076 {
1077 if (d->mode == QXL_MODE_UNDEFINED) {
1078 return 0;
1079 }
1080
1081 dprint(d, 1, "%s\n", __FUNCTION__);
1082
1083 d->mode = QXL_MODE_UNDEFINED;
1084 qemu_spice_destroy_primary_surface(&d->ssd, 0, async);
1085 qxl_spice_reset_cursor(d);
1086 return 1;
1087 }
1088
1089 static void qxl_set_mode(PCIQXLDevice *d, int modenr, int loadvm)
1090 {
1091 pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1092 pcibus_t end = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start;
1093 QXLMode *mode = d->modes->modes + modenr;
1094 uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1095 QXLMemSlot slot = {
1096 .mem_start = start,
1097 .mem_end = end
1098 };
1099 QXLSurfaceCreate surface = {
1100 .width = mode->x_res,
1101 .height = mode->y_res,
1102 .stride = -mode->x_res * 4,
1103 .format = SPICE_SURFACE_FMT_32_xRGB,
1104 .flags = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0,
1105 .mouse_mode = true,
1106 .mem = devmem + d->shadow_rom.draw_area_offset,
1107 };
1108
1109 dprint(d, 1, "%s: mode %d [ %d x %d @ %d bpp devmem 0x%" PRIx64 " ]\n",
1110 __func__, modenr, mode->x_res, mode->y_res, mode->bits, devmem);
1111 if (!loadvm) {
1112 qxl_hard_reset(d, 0);
1113 }
1114
1115 d->guest_slots[0].slot = slot;
1116 qxl_add_memslot(d, 0, devmem, QXL_SYNC);
1117
1118 d->guest_primary.surface = surface;
1119 qxl_create_guest_primary(d, 0, QXL_SYNC);
1120
1121 d->mode = QXL_MODE_COMPAT;
1122 d->cmdflags = QXL_COMMAND_FLAG_COMPAT;
1123 #ifdef QXL_COMMAND_FLAG_COMPAT_16BPP /* new in spice 0.6.1 */
1124 if (mode->bits == 16) {
1125 d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP;
1126 }
1127 #endif
1128 d->shadow_rom.mode = cpu_to_le32(modenr);
1129 d->rom->mode = cpu_to_le32(modenr);
1130 qxl_rom_set_dirty(d);
1131 }
1132
1133 static void ioport_write(void *opaque, target_phys_addr_t addr,
1134 uint64_t val, unsigned size)
1135 {
1136 PCIQXLDevice *d = opaque;
1137 uint32_t io_port = addr;
1138 qxl_async_io async = QXL_SYNC;
1139 #if SPICE_INTERFACE_QXL_MINOR >= 1
1140 uint32_t orig_io_port = io_port;
1141 #endif
1142
1143 switch (io_port) {
1144 case QXL_IO_RESET:
1145 case QXL_IO_SET_MODE:
1146 case QXL_IO_MEMSLOT_ADD:
1147 case QXL_IO_MEMSLOT_DEL:
1148 case QXL_IO_CREATE_PRIMARY:
1149 case QXL_IO_UPDATE_IRQ:
1150 case QXL_IO_LOG:
1151 #if SPICE_INTERFACE_QXL_MINOR >= 1
1152 case QXL_IO_MEMSLOT_ADD_ASYNC:
1153 case QXL_IO_CREATE_PRIMARY_ASYNC:
1154 #endif
1155 break;
1156 default:
1157 if (d->mode != QXL_MODE_VGA) {
1158 break;
1159 }
1160 dprint(d, 1, "%s: unexpected port 0x%x (%s) in vga mode\n",
1161 __func__, io_port, io_port_to_string(io_port));
1162 #if SPICE_INTERFACE_QXL_MINOR >= 1
1163 /* be nice to buggy guest drivers */
1164 if (io_port >= QXL_IO_UPDATE_AREA_ASYNC &&
1165 io_port <= QXL_IO_DESTROY_ALL_SURFACES_ASYNC) {
1166 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1167 }
1168 #endif
1169 return;
1170 }
1171
1172 #if SPICE_INTERFACE_QXL_MINOR >= 1
1173 /* we change the io_port to avoid ifdeffery in the main switch */
1174 orig_io_port = io_port;
1175 switch (io_port) {
1176 case QXL_IO_UPDATE_AREA_ASYNC:
1177 io_port = QXL_IO_UPDATE_AREA;
1178 goto async_common;
1179 case QXL_IO_MEMSLOT_ADD_ASYNC:
1180 io_port = QXL_IO_MEMSLOT_ADD;
1181 goto async_common;
1182 case QXL_IO_CREATE_PRIMARY_ASYNC:
1183 io_port = QXL_IO_CREATE_PRIMARY;
1184 goto async_common;
1185 case QXL_IO_DESTROY_PRIMARY_ASYNC:
1186 io_port = QXL_IO_DESTROY_PRIMARY;
1187 goto async_common;
1188 case QXL_IO_DESTROY_SURFACE_ASYNC:
1189 io_port = QXL_IO_DESTROY_SURFACE_WAIT;
1190 goto async_common;
1191 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
1192 io_port = QXL_IO_DESTROY_ALL_SURFACES;
1193 goto async_common;
1194 case QXL_IO_FLUSH_SURFACES_ASYNC:
1195 async_common:
1196 async = QXL_ASYNC;
1197 qemu_mutex_lock(&d->async_lock);
1198 if (d->current_async != QXL_UNDEFINED_IO) {
1199 qxl_guest_bug(d, "%d async started before last (%d) complete",
1200 io_port, d->current_async);
1201 qemu_mutex_unlock(&d->async_lock);
1202 return;
1203 }
1204 d->current_async = orig_io_port;
1205 qemu_mutex_unlock(&d->async_lock);
1206 dprint(d, 2, "start async %d (%"PRId64")\n", io_port, val);
1207 break;
1208 default:
1209 break;
1210 }
1211 #endif
1212
1213 switch (io_port) {
1214 case QXL_IO_UPDATE_AREA:
1215 {
1216 QXLRect update = d->ram->update_area;
1217 qxl_spice_update_area(d, d->ram->update_surface,
1218 &update, NULL, 0, 0, async);
1219 break;
1220 }
1221 case QXL_IO_NOTIFY_CMD:
1222 qemu_spice_wakeup(&d->ssd);
1223 break;
1224 case QXL_IO_NOTIFY_CURSOR:
1225 qemu_spice_wakeup(&d->ssd);
1226 break;
1227 case QXL_IO_UPDATE_IRQ:
1228 qxl_update_irq(d);
1229 break;
1230 case QXL_IO_NOTIFY_OOM:
1231 if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) {
1232 break;
1233 }
1234 d->oom_running = 1;
1235 qxl_spice_oom(d);
1236 d->oom_running = 0;
1237 break;
1238 case QXL_IO_SET_MODE:
1239 dprint(d, 1, "QXL_SET_MODE %d\n", (int)val);
1240 qxl_set_mode(d, val, 0);
1241 break;
1242 case QXL_IO_LOG:
1243 if (d->guestdebug) {
1244 fprintf(stderr, "qxl/guest-%d: %" PRId64 ": %s", d->id,
1245 qemu_get_clock_ns(vm_clock), d->ram->log_buf);
1246 }
1247 break;
1248 case QXL_IO_RESET:
1249 dprint(d, 1, "QXL_IO_RESET\n");
1250 qxl_hard_reset(d, 0);
1251 break;
1252 case QXL_IO_MEMSLOT_ADD:
1253 if (val >= NUM_MEMSLOTS) {
1254 qxl_guest_bug(d, "QXL_IO_MEMSLOT_ADD: val out of range");
1255 break;
1256 }
1257 if (d->guest_slots[val].active) {
1258 qxl_guest_bug(d, "QXL_IO_MEMSLOT_ADD: memory slot already active");
1259 break;
1260 }
1261 d->guest_slots[val].slot = d->ram->mem_slot;
1262 qxl_add_memslot(d, val, 0, async);
1263 break;
1264 case QXL_IO_MEMSLOT_DEL:
1265 if (val >= NUM_MEMSLOTS) {
1266 qxl_guest_bug(d, "QXL_IO_MEMSLOT_DEL: val out of range");
1267 break;
1268 }
1269 qxl_del_memslot(d, val);
1270 break;
1271 case QXL_IO_CREATE_PRIMARY:
1272 if (val != 0) {
1273 qxl_guest_bug(d, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0",
1274 async);
1275 goto cancel_async;
1276 }
1277 dprint(d, 1, "QXL_IO_CREATE_PRIMARY async=%d\n", async);
1278 d->guest_primary.surface = d->ram->create_surface;
1279 qxl_create_guest_primary(d, 0, async);
1280 break;
1281 case QXL_IO_DESTROY_PRIMARY:
1282 if (val != 0) {
1283 qxl_guest_bug(d, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0",
1284 async);
1285 goto cancel_async;
1286 }
1287 dprint(d, 1, "QXL_IO_DESTROY_PRIMARY (async=%d) (%s)\n", async,
1288 qxl_mode_to_string(d->mode));
1289 if (!qxl_destroy_primary(d, async)) {
1290 dprint(d, 1, "QXL_IO_DESTROY_PRIMARY_ASYNC in %s, ignored\n",
1291 qxl_mode_to_string(d->mode));
1292 goto cancel_async;
1293 }
1294 break;
1295 case QXL_IO_DESTROY_SURFACE_WAIT:
1296 if (val >= NUM_SURFACES) {
1297 qxl_guest_bug(d, "QXL_IO_DESTROY_SURFACE (async=%d):"
1298 "%d >= NUM_SURFACES", async, val);
1299 goto cancel_async;
1300 }
1301 qxl_spice_destroy_surface_wait(d, val, async);
1302 break;
1303 #if SPICE_INTERFACE_QXL_MINOR >= 1
1304 case QXL_IO_FLUSH_RELEASE: {
1305 QXLReleaseRing *ring = &d->ram->release_ring;
1306 if (ring->prod - ring->cons + 1 == ring->num_items) {
1307 fprintf(stderr,
1308 "ERROR: no flush, full release ring [p%d,%dc]\n",
1309 ring->prod, ring->cons);
1310 }
1311 qxl_push_free_res(d, 1 /* flush */);
1312 dprint(d, 1, "QXL_IO_FLUSH_RELEASE exit (%s, s#=%d, res#=%d,%p)\n",
1313 qxl_mode_to_string(d->mode), d->guest_surfaces.count,
1314 d->num_free_res, d->last_release);
1315 break;
1316 }
1317 case QXL_IO_FLUSH_SURFACES_ASYNC:
1318 dprint(d, 1, "QXL_IO_FLUSH_SURFACES_ASYNC"
1319 " (%"PRId64") (%s, s#=%d, res#=%d)\n",
1320 val, qxl_mode_to_string(d->mode), d->guest_surfaces.count,
1321 d->num_free_res);
1322 qxl_spice_flush_surfaces_async(d);
1323 break;
1324 #endif
1325 case QXL_IO_DESTROY_ALL_SURFACES:
1326 d->mode = QXL_MODE_UNDEFINED;
1327 qxl_spice_destroy_surfaces(d, async);
1328 break;
1329 default:
1330 fprintf(stderr, "%s: ioport=0x%x, abort()\n", __FUNCTION__, io_port);
1331 abort();
1332 }
1333 return;
1334 cancel_async:
1335 #if SPICE_INTERFACE_QXL_MINOR >= 1
1336 if (async) {
1337 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1338 qemu_mutex_lock(&d->async_lock);
1339 d->current_async = QXL_UNDEFINED_IO;
1340 qemu_mutex_unlock(&d->async_lock);
1341 }
1342 #else
1343 return;
1344 #endif
1345 }
1346
1347 static uint64_t ioport_read(void *opaque, target_phys_addr_t addr,
1348 unsigned size)
1349 {
1350 PCIQXLDevice *d = opaque;
1351
1352 dprint(d, 1, "%s: unexpected\n", __FUNCTION__);
1353 return 0xff;
1354 }
1355
1356 static const MemoryRegionOps qxl_io_ops = {
1357 .read = ioport_read,
1358 .write = ioport_write,
1359 .valid = {
1360 .min_access_size = 1,
1361 .max_access_size = 1,
1362 },
1363 };
1364
1365 static void pipe_read(void *opaque)
1366 {
1367 PCIQXLDevice *d = opaque;
1368 char dummy;
1369 int len;
1370
1371 do {
1372 len = read(d->pipe[0], &dummy, sizeof(dummy));
1373 } while (len == sizeof(dummy));
1374 qxl_update_irq(d);
1375 }
1376
1377 static void qxl_send_events(PCIQXLDevice *d, uint32_t events)
1378 {
1379 uint32_t old_pending;
1380 uint32_t le_events = cpu_to_le32(events);
1381
1382 assert(d->ssd.running);
1383 old_pending = __sync_fetch_and_or(&d->ram->int_pending, le_events);
1384 if ((old_pending & le_events) == le_events) {
1385 return;
1386 }
1387 if (qemu_thread_is_self(&d->main)) {
1388 qxl_update_irq(d);
1389 } else {
1390 if (write(d->pipe[1], d, 1) != 1) {
1391 dprint(d, 1, "%s: write to pipe failed\n", __FUNCTION__);
1392 }
1393 }
1394 }
1395
1396 static void init_pipe_signaling(PCIQXLDevice *d)
1397 {
1398 if (pipe(d->pipe) < 0) {
1399 dprint(d, 1, "%s: pipe creation failed\n", __FUNCTION__);
1400 return;
1401 }
1402 fcntl(d->pipe[0], F_SETFL, O_NONBLOCK);
1403 fcntl(d->pipe[1], F_SETFL, O_NONBLOCK);
1404 fcntl(d->pipe[0], F_SETOWN, getpid());
1405
1406 qemu_thread_get_self(&d->main);
1407 qemu_set_fd_handler(d->pipe[0], pipe_read, NULL, d);
1408 }
1409
1410 /* graphics console */
1411
1412 static void qxl_hw_update(void *opaque)
1413 {
1414 PCIQXLDevice *qxl = opaque;
1415 VGACommonState *vga = &qxl->vga;
1416
1417 switch (qxl->mode) {
1418 case QXL_MODE_VGA:
1419 vga->update(vga);
1420 break;
1421 case QXL_MODE_COMPAT:
1422 case QXL_MODE_NATIVE:
1423 qxl_render_update(qxl);
1424 break;
1425 default:
1426 break;
1427 }
1428 }
1429
1430 static void qxl_hw_invalidate(void *opaque)
1431 {
1432 PCIQXLDevice *qxl = opaque;
1433 VGACommonState *vga = &qxl->vga;
1434
1435 vga->invalidate(vga);
1436 }
1437
1438 static void qxl_hw_screen_dump(void *opaque, const char *filename)
1439 {
1440 PCIQXLDevice *qxl = opaque;
1441 VGACommonState *vga = &qxl->vga;
1442
1443 switch (qxl->mode) {
1444 case QXL_MODE_COMPAT:
1445 case QXL_MODE_NATIVE:
1446 qxl_render_update(qxl);
1447 ppm_save(filename, qxl->ssd.ds->surface);
1448 break;
1449 case QXL_MODE_VGA:
1450 vga->screen_dump(vga, filename);
1451 break;
1452 default:
1453 break;
1454 }
1455 }
1456
1457 static void qxl_hw_text_update(void *opaque, console_ch_t *chardata)
1458 {
1459 PCIQXLDevice *qxl = opaque;
1460 VGACommonState *vga = &qxl->vga;
1461
1462 if (qxl->mode == QXL_MODE_VGA) {
1463 vga->text_update(vga, chardata);
1464 return;
1465 }
1466 }
1467
1468 static void qxl_vm_change_state_handler(void *opaque, int running,
1469 RunState state)
1470 {
1471 PCIQXLDevice *qxl = opaque;
1472 qemu_spice_vm_change_state_handler(&qxl->ssd, running, state);
1473
1474 if (running) {
1475 /*
1476 * if qxl_send_events was called from spice server context before
1477 * migration ended, qxl_update_irq for these events might not have been
1478 * called
1479 */
1480 qxl_update_irq(qxl);
1481 } else if (qxl->mode == QXL_MODE_NATIVE) {
1482 /* dirty all vram (which holds surfaces) and devram (primary surface)
1483 * to make sure they are saved */
1484 /* FIXME #1: should go out during "live" stage */
1485 /* FIXME #2: we only need to save the areas which are actually used */
1486 qxl_set_dirty(&qxl->vram_bar, 0, qxl->vram_size);
1487 qxl_set_dirty(&qxl->vga.vram, qxl->shadow_rom.draw_area_offset,
1488 qxl->shadow_rom.surface0_area_size);
1489 }
1490 }
1491
1492 /* display change listener */
1493
1494 static void display_update(struct DisplayState *ds, int x, int y, int w, int h)
1495 {
1496 if (qxl0->mode == QXL_MODE_VGA) {
1497 qemu_spice_display_update(&qxl0->ssd, x, y, w, h);
1498 }
1499 }
1500
1501 static void display_resize(struct DisplayState *ds)
1502 {
1503 if (qxl0->mode == QXL_MODE_VGA) {
1504 qemu_spice_display_resize(&qxl0->ssd);
1505 }
1506 }
1507
1508 static void display_refresh(struct DisplayState *ds)
1509 {
1510 if (qxl0->mode == QXL_MODE_VGA) {
1511 qemu_spice_display_refresh(&qxl0->ssd);
1512 }
1513 }
1514
1515 static DisplayChangeListener display_listener = {
1516 .dpy_update = display_update,
1517 .dpy_resize = display_resize,
1518 .dpy_refresh = display_refresh,
1519 };
1520
1521 static int qxl_init_common(PCIQXLDevice *qxl)
1522 {
1523 uint8_t* config = qxl->pci.config;
1524 uint32_t pci_device_rev;
1525 uint32_t io_size;
1526
1527 qxl->mode = QXL_MODE_UNDEFINED;
1528 qxl->generation = 1;
1529 qxl->num_memslots = NUM_MEMSLOTS;
1530 qxl->num_surfaces = NUM_SURFACES;
1531 qemu_mutex_init(&qxl->track_lock);
1532 qemu_mutex_init(&qxl->async_lock);
1533 qxl->current_async = QXL_UNDEFINED_IO;
1534
1535 switch (qxl->revision) {
1536 case 1: /* spice 0.4 -- qxl-1 */
1537 pci_device_rev = QXL_REVISION_STABLE_V04;
1538 break;
1539 case 2: /* spice 0.6 -- qxl-2 */
1540 pci_device_rev = QXL_REVISION_STABLE_V06;
1541 break;
1542 #if SPICE_INTERFACE_QXL_MINOR >= 1
1543 case 3: /* qxl-3 */
1544 #endif
1545 default:
1546 pci_device_rev = QXL_DEFAULT_REVISION;
1547 break;
1548 }
1549
1550 pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev);
1551 pci_set_byte(&config[PCI_INTERRUPT_PIN], 1);
1552
1553 qxl->rom_size = qxl_rom_size();
1554 memory_region_init_ram(&qxl->rom_bar, "qxl.vrom", qxl->rom_size);
1555 vmstate_register_ram(&qxl->rom_bar, &qxl->pci.qdev);
1556 init_qxl_rom(qxl);
1557 init_qxl_ram(qxl);
1558
1559 if (qxl->vram_size < 16 * 1024 * 1024) {
1560 qxl->vram_size = 16 * 1024 * 1024;
1561 }
1562 if (qxl->revision == 1) {
1563 qxl->vram_size = 4096;
1564 }
1565 qxl->vram_size = msb_mask(qxl->vram_size * 2 - 1);
1566 memory_region_init_ram(&qxl->vram_bar, "qxl.vram", qxl->vram_size);
1567 vmstate_register_ram(&qxl->vram_bar, &qxl->pci.qdev);
1568
1569 io_size = msb_mask(QXL_IO_RANGE_SIZE * 2 - 1);
1570 if (qxl->revision == 1) {
1571 io_size = 8;
1572 }
1573
1574 memory_region_init_io(&qxl->io_bar, &qxl_io_ops, qxl,
1575 "qxl-ioports", io_size);
1576 if (qxl->id == 0) {
1577 vga_dirty_log_start(&qxl->vga);
1578 }
1579
1580
1581 pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX,
1582 PCI_BASE_ADDRESS_SPACE_IO, &qxl->io_bar);
1583
1584 pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX,
1585 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->rom_bar);
1586
1587 pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX,
1588 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vga.vram);
1589
1590 pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX,
1591 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vram_bar);
1592
1593 qxl->ssd.qxl.base.sif = &qxl_interface.base;
1594 qxl->ssd.qxl.id = qxl->id;
1595 qemu_spice_add_interface(&qxl->ssd.qxl.base);
1596 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl);
1597
1598 init_pipe_signaling(qxl);
1599 qxl_reset_state(qxl);
1600
1601 return 0;
1602 }
1603
1604 static int qxl_init_primary(PCIDevice *dev)
1605 {
1606 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev);
1607 VGACommonState *vga = &qxl->vga;
1608 ram_addr_t ram_size = msb_mask(qxl->vga.vram_size * 2 - 1);
1609 PortioList *qxl_vga_port_list = g_new(PortioList, 1);
1610
1611 qxl->id = 0;
1612
1613 if (ram_size < 32 * 1024 * 1024) {
1614 ram_size = 32 * 1024 * 1024;
1615 }
1616 vga_common_init(vga, ram_size);
1617 vga_init(vga, pci_address_space(dev), pci_address_space_io(dev), false);
1618 portio_list_init(qxl_vga_port_list, qxl_vga_portio_list, vga, "vga");
1619 portio_list_add(qxl_vga_port_list, pci_address_space_io(dev), 0x3b0);
1620
1621 vga->ds = graphic_console_init(qxl_hw_update, qxl_hw_invalidate,
1622 qxl_hw_screen_dump, qxl_hw_text_update, qxl);
1623 qemu_spice_display_init_common(&qxl->ssd, vga->ds);
1624
1625 qxl0 = qxl;
1626 register_displaychangelistener(vga->ds, &display_listener);
1627
1628 return qxl_init_common(qxl);
1629 }
1630
1631 static int qxl_init_secondary(PCIDevice *dev)
1632 {
1633 static int device_id = 1;
1634 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev);
1635 ram_addr_t ram_size = msb_mask(qxl->vga.vram_size * 2 - 1);
1636
1637 qxl->id = device_id++;
1638
1639 if (ram_size < 16 * 1024 * 1024) {
1640 ram_size = 16 * 1024 * 1024;
1641 }
1642 qxl->vga.vram_size = ram_size;
1643 memory_region_init_ram(&qxl->vga.vram, "qxl.vgavram", qxl->vga.vram_size);
1644 vmstate_register_ram(&qxl->vga.vram, &qxl->pci.qdev);
1645 qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram);
1646
1647 return qxl_init_common(qxl);
1648 }
1649
1650 static void qxl_pre_save(void *opaque)
1651 {
1652 PCIQXLDevice* d = opaque;
1653 uint8_t *ram_start = d->vga.vram_ptr;
1654
1655 dprint(d, 1, "%s:\n", __FUNCTION__);
1656 if (d->last_release == NULL) {
1657 d->last_release_offset = 0;
1658 } else {
1659 d->last_release_offset = (uint8_t *)d->last_release - ram_start;
1660 }
1661 assert(d->last_release_offset < d->vga.vram_size);
1662 }
1663
1664 static int qxl_pre_load(void *opaque)
1665 {
1666 PCIQXLDevice* d = opaque;
1667
1668 dprint(d, 1, "%s: start\n", __FUNCTION__);
1669 qxl_hard_reset(d, 1);
1670 qxl_exit_vga_mode(d);
1671 dprint(d, 1, "%s: done\n", __FUNCTION__);
1672 return 0;
1673 }
1674
1675 static void qxl_create_memslots(PCIQXLDevice *d)
1676 {
1677 int i;
1678
1679 for (i = 0; i < NUM_MEMSLOTS; i++) {
1680 if (!d->guest_slots[i].active) {
1681 continue;
1682 }
1683 dprint(d, 1, "%s: restoring guest slot %d\n", __func__, i);
1684 qxl_add_memslot(d, i, 0, QXL_SYNC);
1685 }
1686 }
1687
1688 static int qxl_post_load(void *opaque, int version)
1689 {
1690 PCIQXLDevice* d = opaque;
1691 uint8_t *ram_start = d->vga.vram_ptr;
1692 QXLCommandExt *cmds;
1693 int in, out, newmode;
1694
1695 dprint(d, 1, "%s: start\n", __FUNCTION__);
1696
1697 assert(d->last_release_offset < d->vga.vram_size);
1698 if (d->last_release_offset == 0) {
1699 d->last_release = NULL;
1700 } else {
1701 d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset);
1702 }
1703
1704 d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset);
1705
1706 dprint(d, 1, "%s: restore mode (%s)\n", __FUNCTION__,
1707 qxl_mode_to_string(d->mode));
1708 newmode = d->mode;
1709 d->mode = QXL_MODE_UNDEFINED;
1710
1711 switch (newmode) {
1712 case QXL_MODE_UNDEFINED:
1713 break;
1714 case QXL_MODE_VGA:
1715 qxl_create_memslots(d);
1716 qxl_enter_vga_mode(d);
1717 break;
1718 case QXL_MODE_NATIVE:
1719 qxl_create_memslots(d);
1720 qxl_create_guest_primary(d, 1, QXL_SYNC);
1721
1722 /* replay surface-create and cursor-set commands */
1723 cmds = g_malloc0(sizeof(QXLCommandExt) * (NUM_SURFACES + 1));
1724 for (in = 0, out = 0; in < NUM_SURFACES; in++) {
1725 if (d->guest_surfaces.cmds[in] == 0) {
1726 continue;
1727 }
1728 cmds[out].cmd.data = d->guest_surfaces.cmds[in];
1729 cmds[out].cmd.type = QXL_CMD_SURFACE;
1730 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
1731 out++;
1732 }
1733 if (d->guest_cursor) {
1734 cmds[out].cmd.data = d->guest_cursor;
1735 cmds[out].cmd.type = QXL_CMD_CURSOR;
1736 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
1737 out++;
1738 }
1739 qxl_spice_loadvm_commands(d, cmds, out);
1740 g_free(cmds);
1741
1742 break;
1743 case QXL_MODE_COMPAT:
1744 /* note: no need to call qxl_create_memslots, qxl_set_mode
1745 * creates the mem slot. */
1746 qxl_set_mode(d, d->shadow_rom.mode, 1);
1747 break;
1748 }
1749 dprint(d, 1, "%s: done\n", __FUNCTION__);
1750
1751 return 0;
1752 }
1753
1754 #define QXL_SAVE_VERSION 21
1755
1756 static VMStateDescription qxl_memslot = {
1757 .name = "qxl-memslot",
1758 .version_id = QXL_SAVE_VERSION,
1759 .minimum_version_id = QXL_SAVE_VERSION,
1760 .fields = (VMStateField[]) {
1761 VMSTATE_UINT64(slot.mem_start, struct guest_slots),
1762 VMSTATE_UINT64(slot.mem_end, struct guest_slots),
1763 VMSTATE_UINT32(active, struct guest_slots),
1764 VMSTATE_END_OF_LIST()
1765 }
1766 };
1767
1768 static VMStateDescription qxl_surface = {
1769 .name = "qxl-surface",
1770 .version_id = QXL_SAVE_VERSION,
1771 .minimum_version_id = QXL_SAVE_VERSION,
1772 .fields = (VMStateField[]) {
1773 VMSTATE_UINT32(width, QXLSurfaceCreate),
1774 VMSTATE_UINT32(height, QXLSurfaceCreate),
1775 VMSTATE_INT32(stride, QXLSurfaceCreate),
1776 VMSTATE_UINT32(format, QXLSurfaceCreate),
1777 VMSTATE_UINT32(position, QXLSurfaceCreate),
1778 VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate),
1779 VMSTATE_UINT32(flags, QXLSurfaceCreate),
1780 VMSTATE_UINT32(type, QXLSurfaceCreate),
1781 VMSTATE_UINT64(mem, QXLSurfaceCreate),
1782 VMSTATE_END_OF_LIST()
1783 }
1784 };
1785
1786 static VMStateDescription qxl_vmstate = {
1787 .name = "qxl",
1788 .version_id = QXL_SAVE_VERSION,
1789 .minimum_version_id = QXL_SAVE_VERSION,
1790 .pre_save = qxl_pre_save,
1791 .pre_load = qxl_pre_load,
1792 .post_load = qxl_post_load,
1793 .fields = (VMStateField []) {
1794 VMSTATE_PCI_DEVICE(pci, PCIQXLDevice),
1795 VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState),
1796 VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice),
1797 VMSTATE_UINT32(num_free_res, PCIQXLDevice),
1798 VMSTATE_UINT32(last_release_offset, PCIQXLDevice),
1799 VMSTATE_UINT32(mode, PCIQXLDevice),
1800 VMSTATE_UINT32(ssd.unique, PCIQXLDevice),
1801 VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice),
1802 VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0,
1803 qxl_memslot, struct guest_slots),
1804 VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0,
1805 qxl_surface, QXLSurfaceCreate),
1806 VMSTATE_INT32_EQUAL(num_surfaces, PCIQXLDevice),
1807 VMSTATE_ARRAY(guest_surfaces.cmds, PCIQXLDevice, NUM_SURFACES, 0,
1808 vmstate_info_uint64, uint64_t),
1809 VMSTATE_UINT64(guest_cursor, PCIQXLDevice),
1810 VMSTATE_END_OF_LIST()
1811 },
1812 };
1813
1814 static Property qxl_properties[] = {
1815 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size,
1816 64 * 1024 * 1024),
1817 DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram_size,
1818 64 * 1024 * 1024),
1819 DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision,
1820 QXL_DEFAULT_REVISION),
1821 DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0),
1822 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0),
1823 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0),
1824 DEFINE_PROP_END_OF_LIST(),
1825 };
1826
1827 static void qxl_primary_class_init(ObjectClass *klass, void *data)
1828 {
1829 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1830
1831 k->no_hotplug = 1;
1832 k->init = qxl_init_primary;
1833 k->romfile = "vgabios-qxl.bin";
1834 k->vendor_id = REDHAT_PCI_VENDOR_ID;
1835 k->device_id = QXL_DEVICE_ID_STABLE;
1836 k->class_id = PCI_CLASS_DISPLAY_VGA;
1837 }
1838
1839 static DeviceInfo qxl_primary_info = {
1840 .name = "qxl-vga",
1841 .desc = "Spice QXL GPU (primary, vga compatible)",
1842 .size = sizeof(PCIQXLDevice),
1843 .reset = qxl_reset_handler,
1844 .vmsd = &qxl_vmstate,
1845 .props = qxl_properties,
1846 .class_init = qxl_primary_class_init,
1847 };
1848
1849 static void qxl_secondary_class_init(ObjectClass *klass, void *data)
1850 {
1851 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1852
1853 k->init = qxl_init_secondary;
1854 k->vendor_id = REDHAT_PCI_VENDOR_ID;
1855 k->device_id = QXL_DEVICE_ID_STABLE;
1856 k->class_id = PCI_CLASS_DISPLAY_OTHER;
1857 }
1858
1859 static DeviceInfo qxl_secondary_info = {
1860 .name = "qxl",
1861 .desc = "Spice QXL GPU (secondary)",
1862 .size = sizeof(PCIQXLDevice),
1863 .reset = qxl_reset_handler,
1864 .vmsd = &qxl_vmstate,
1865 .props = qxl_properties,
1866 .class_init = qxl_secondary_class_init,
1867 };
1868
1869 static void qxl_register(void)
1870 {
1871 pci_qdev_register(&qxl_primary_info);
1872 pci_qdev_register(&qxl_secondary_info);
1873 }
1874
1875 device_init(qxl_register);