rdma: check num_sge does not exceed MAX_SGE
[qemu.git] / hw / rdma / rdma_backend.c
1 /*
2 * QEMU paravirtual RDMA - Generic RDMA backend
3 *
4 * Copyright (C) 2018 Oracle
5 * Copyright (C) 2018 Red Hat Inc
6 *
7 * Authors:
8 * Yuval Shaia <yuval.shaia@oracle.com>
9 * Marcel Apfelbaum <marcel@redhat.com>
10 *
11 * This work is licensed under the terms of the GNU GPL, version 2 or later.
12 * See the COPYING file in the top-level directory.
13 *
14 */
15
16 #include "qemu/osdep.h"
17 #include "qemu/error-report.h"
18 #include "sysemu/sysemu.h"
19 #include "qapi/error.h"
20 #include "qapi/qmp/qlist.h"
21 #include "qapi/qmp/qnum.h"
22 #include "qapi/qapi-events-rdma.h"
23
24 #include <infiniband/verbs.h>
25 #include <infiniband/umad_types.h>
26 #include <infiniband/umad.h>
27 #include <rdma/rdma_user_cm.h>
28
29 #include "contrib/rdmacm-mux/rdmacm-mux.h"
30 #include "trace.h"
31 #include "rdma_utils.h"
32 #include "rdma_rm.h"
33 #include "rdma_backend.h"
34
35 /* Vendor Errors */
36 #define VENDOR_ERR_FAIL_BACKEND 0x201
37 #define VENDOR_ERR_TOO_MANY_SGES 0x202
38 #define VENDOR_ERR_NOMEM 0x203
39 #define VENDOR_ERR_QP0 0x204
40 #define VENDOR_ERR_NO_SGE 0x205
41 #define VENDOR_ERR_MAD_SEND 0x206
42 #define VENDOR_ERR_INVLKEY 0x207
43 #define VENDOR_ERR_MR_SMALL 0x208
44 #define VENDOR_ERR_INV_MAD_BUFF 0x209
45 #define VENDOR_ERR_INV_NUM_SGE 0x210
46
47 #define THR_NAME_LEN 16
48 #define THR_POLL_TO 5000
49
50 #define MAD_HDR_SIZE sizeof(struct ibv_grh)
51
52 typedef struct BackendCtx {
53 void *up_ctx;
54 bool is_tx_req;
55 struct ibv_sge sge; /* Used to save MAD recv buffer */
56 } BackendCtx;
57
58 struct backend_umad {
59 struct ib_user_mad hdr;
60 char mad[RDMA_MAX_PRIVATE_DATA];
61 };
62
63 static void (*comp_handler)(void *ctx, struct ibv_wc *wc);
64
65 static void dummy_comp_handler(void *ctx, struct ibv_wc *wc)
66 {
67 pr_err("No completion handler is registered\n");
68 }
69
70 static inline void complete_work(enum ibv_wc_status status, uint32_t vendor_err,
71 void *ctx)
72 {
73 struct ibv_wc wc = {0};
74
75 wc.status = status;
76 wc.vendor_err = vendor_err;
77
78 comp_handler(ctx, &wc);
79 }
80
81 static void poll_cq(RdmaDeviceResources *rdma_dev_res, struct ibv_cq *ibcq)
82 {
83 int i, ne;
84 BackendCtx *bctx;
85 struct ibv_wc wc[2];
86
87 pr_dbg("Entering poll_cq loop on cq %p\n", ibcq);
88 do {
89 ne = ibv_poll_cq(ibcq, ARRAY_SIZE(wc), wc);
90
91 pr_dbg("Got %d completion(s) from cq %p\n", ne, ibcq);
92
93 for (i = 0; i < ne; i++) {
94 pr_dbg("wr_id=0x%" PRIx64 "\n", wc[i].wr_id);
95 pr_dbg("status=%d\n", wc[i].status);
96
97 bctx = rdma_rm_get_cqe_ctx(rdma_dev_res, wc[i].wr_id);
98 if (unlikely(!bctx)) {
99 pr_dbg("Error: Failed to find ctx for req %" PRId64 "\n",
100 wc[i].wr_id);
101 continue;
102 }
103 pr_dbg("Processing %s CQE\n", bctx->is_tx_req ? "send" : "recv");
104
105 comp_handler(bctx->up_ctx, &wc[i]);
106
107 rdma_rm_dealloc_cqe_ctx(rdma_dev_res, wc[i].wr_id);
108 g_free(bctx);
109 }
110 } while (ne > 0);
111
112 if (ne < 0) {
113 pr_dbg("Got error %d from ibv_poll_cq\n", ne);
114 }
115 }
116
117 static void *comp_handler_thread(void *arg)
118 {
119 RdmaBackendDev *backend_dev = (RdmaBackendDev *)arg;
120 int rc;
121 struct ibv_cq *ev_cq;
122 void *ev_ctx;
123 int flags;
124 GPollFD pfds[1];
125
126 /* Change to non-blocking mode */
127 flags = fcntl(backend_dev->channel->fd, F_GETFL);
128 rc = fcntl(backend_dev->channel->fd, F_SETFL, flags | O_NONBLOCK);
129 if (rc < 0) {
130 pr_dbg("Fail to change to non-blocking mode\n");
131 return NULL;
132 }
133
134 pr_dbg("Starting\n");
135
136 pfds[0].fd = backend_dev->channel->fd;
137 pfds[0].events = G_IO_IN | G_IO_HUP | G_IO_ERR;
138
139 backend_dev->comp_thread.is_running = true;
140
141 while (backend_dev->comp_thread.run) {
142 do {
143 rc = qemu_poll_ns(pfds, 1, THR_POLL_TO * (int64_t)SCALE_MS);
144 } while (!rc && backend_dev->comp_thread.run);
145
146 if (backend_dev->comp_thread.run) {
147 pr_dbg("Waiting for completion on channel %p\n", backend_dev->channel);
148 rc = ibv_get_cq_event(backend_dev->channel, &ev_cq, &ev_ctx);
149 pr_dbg("ibv_get_cq_event=%d\n", rc);
150 if (unlikely(rc)) {
151 pr_dbg("---> ibv_get_cq_event (%d)\n", rc);
152 continue;
153 }
154
155 rc = ibv_req_notify_cq(ev_cq, 0);
156 if (unlikely(rc)) {
157 pr_dbg("Error %d from ibv_req_notify_cq\n", rc);
158 }
159
160 poll_cq(backend_dev->rdma_dev_res, ev_cq);
161
162 ibv_ack_cq_events(ev_cq, 1);
163 }
164 }
165
166 pr_dbg("Going down\n");
167
168 /* TODO: Post cqe for all remaining buffs that were posted */
169
170 backend_dev->comp_thread.is_running = false;
171
172 qemu_thread_exit(0);
173
174 return NULL;
175 }
176
177 static inline void disable_rdmacm_mux_async(RdmaBackendDev *backend_dev)
178 {
179 atomic_set(&backend_dev->rdmacm_mux.can_receive, 0);
180 }
181
182 static inline void enable_rdmacm_mux_async(RdmaBackendDev *backend_dev)
183 {
184 atomic_set(&backend_dev->rdmacm_mux.can_receive, sizeof(RdmaCmMuxMsg));
185 }
186
187 static inline int rdmacm_mux_can_process_async(RdmaBackendDev *backend_dev)
188 {
189 return atomic_read(&backend_dev->rdmacm_mux.can_receive);
190 }
191
192 static int check_mux_op_status(CharBackend *mad_chr_be)
193 {
194 RdmaCmMuxMsg msg = {0};
195 int ret;
196
197 pr_dbg("Reading response\n");
198 ret = qemu_chr_fe_read_all(mad_chr_be, (uint8_t *)&msg, sizeof(msg));
199 if (ret != sizeof(msg)) {
200 pr_dbg("Invalid message size %d, expecting %ld\n", ret, sizeof(msg));
201 return -EIO;
202 }
203
204 pr_dbg("msg_type=%d\n", msg.hdr.msg_type);
205 pr_dbg("op_code=%d\n", msg.hdr.op_code);
206 pr_dbg("err_code=%d\n", msg.hdr.err_code);
207
208 if (msg.hdr.msg_type != RDMACM_MUX_MSG_TYPE_RESP) {
209 pr_dbg("Invalid message type %d\n", msg.hdr.msg_type);
210 return -EIO;
211 }
212
213 if (msg.hdr.err_code != RDMACM_MUX_ERR_CODE_OK) {
214 pr_dbg("Operation failed in mux, error code %d\n", msg.hdr.err_code);
215 return -EIO;
216 }
217
218 return 0;
219 }
220
221 static int exec_rdmacm_mux_req(RdmaBackendDev *backend_dev, RdmaCmMuxMsg *msg)
222 {
223 int rc = 0;
224
225 pr_dbg("Executing request %d\n", msg->hdr.op_code);
226
227 msg->hdr.msg_type = RDMACM_MUX_MSG_TYPE_REQ;
228 disable_rdmacm_mux_async(backend_dev);
229 rc = qemu_chr_fe_write(backend_dev->rdmacm_mux.chr_be,
230 (const uint8_t *)msg, sizeof(*msg));
231 if (rc != sizeof(*msg)) {
232 enable_rdmacm_mux_async(backend_dev);
233 pr_dbg("Fail to send request to rdmacm_mux (rc=%d)\n", rc);
234 return -EIO;
235 }
236
237 rc = check_mux_op_status(backend_dev->rdmacm_mux.chr_be);
238 if (rc) {
239 pr_dbg("Fail to execute rdmacm_mux request %d (rc=%d)\n",
240 msg->hdr.op_code, rc);
241 }
242
243 enable_rdmacm_mux_async(backend_dev);
244
245 return 0;
246 }
247
248 static void stop_backend_thread(RdmaBackendThread *thread)
249 {
250 thread->run = false;
251 while (thread->is_running) {
252 pr_dbg("Waiting for thread to complete\n");
253 sleep(THR_POLL_TO / SCALE_US / 2);
254 }
255 }
256
257 static void start_comp_thread(RdmaBackendDev *backend_dev)
258 {
259 char thread_name[THR_NAME_LEN] = {0};
260
261 stop_backend_thread(&backend_dev->comp_thread);
262
263 snprintf(thread_name, sizeof(thread_name), "rdma_comp_%s",
264 ibv_get_device_name(backend_dev->ib_dev));
265 backend_dev->comp_thread.run = true;
266 qemu_thread_create(&backend_dev->comp_thread.thread, thread_name,
267 comp_handler_thread, backend_dev, QEMU_THREAD_DETACHED);
268 }
269
270 void rdma_backend_register_comp_handler(void (*handler)(void *ctx,
271 struct ibv_wc *wc))
272 {
273 comp_handler = handler;
274 }
275
276 void rdma_backend_unregister_comp_handler(void)
277 {
278 rdma_backend_register_comp_handler(dummy_comp_handler);
279 }
280
281 int rdma_backend_query_port(RdmaBackendDev *backend_dev,
282 struct ibv_port_attr *port_attr)
283 {
284 int rc;
285
286 rc = ibv_query_port(backend_dev->context, backend_dev->port_num, port_attr);
287 if (rc) {
288 pr_dbg("Error %d from ibv_query_port\n", rc);
289 return -EIO;
290 }
291
292 return 0;
293 }
294
295 void rdma_backend_poll_cq(RdmaDeviceResources *rdma_dev_res, RdmaBackendCQ *cq)
296 {
297 poll_cq(rdma_dev_res, cq->ibcq);
298 }
299
300 static GHashTable *ah_hash;
301
302 static struct ibv_ah *create_ah(RdmaBackendDev *backend_dev, struct ibv_pd *pd,
303 uint8_t sgid_idx, union ibv_gid *dgid)
304 {
305 GBytes *ah_key = g_bytes_new(dgid, sizeof(*dgid));
306 struct ibv_ah *ah = g_hash_table_lookup(ah_hash, ah_key);
307
308 if (ah) {
309 trace_create_ah_cache_hit(be64_to_cpu(dgid->global.subnet_prefix),
310 be64_to_cpu(dgid->global.interface_id));
311 g_bytes_unref(ah_key);
312 } else {
313 struct ibv_ah_attr ah_attr = {
314 .is_global = 1,
315 .port_num = backend_dev->port_num,
316 .grh.hop_limit = 1,
317 };
318
319 ah_attr.grh.dgid = *dgid;
320 ah_attr.grh.sgid_index = sgid_idx;
321
322 ah = ibv_create_ah(pd, &ah_attr);
323 if (ah) {
324 g_hash_table_insert(ah_hash, ah_key, ah);
325 } else {
326 g_bytes_unref(ah_key);
327 pr_dbg("Fail to create AH for gid <0x%" PRIx64 ", 0x%" PRIx64 ">\n",
328 be64_to_cpu(dgid->global.subnet_prefix),
329 be64_to_cpu(dgid->global.interface_id));
330 }
331
332 trace_create_ah_cache_miss(be64_to_cpu(dgid->global.subnet_prefix),
333 be64_to_cpu(dgid->global.interface_id));
334 }
335
336 return ah;
337 }
338
339 static void destroy_ah_hash_key(gpointer data)
340 {
341 g_bytes_unref(data);
342 }
343
344 static void destroy_ah_hast_data(gpointer data)
345 {
346 struct ibv_ah *ah = data;
347
348 ibv_destroy_ah(ah);
349 }
350
351 static void ah_cache_init(void)
352 {
353 ah_hash = g_hash_table_new_full(g_bytes_hash, g_bytes_equal,
354 destroy_ah_hash_key, destroy_ah_hast_data);
355 }
356
357 static int build_host_sge_array(RdmaDeviceResources *rdma_dev_res,
358 struct ibv_sge *dsge, struct ibv_sge *ssge,
359 uint8_t num_sge)
360 {
361 RdmaRmMR *mr;
362 int ssge_idx;
363
364 pr_dbg("num_sge=%d\n", num_sge);
365
366 for (ssge_idx = 0; ssge_idx < num_sge; ssge_idx++) {
367 mr = rdma_rm_get_mr(rdma_dev_res, ssge[ssge_idx].lkey);
368 if (unlikely(!mr)) {
369 pr_dbg("Invalid lkey 0x%x\n", ssge[ssge_idx].lkey);
370 return VENDOR_ERR_INVLKEY | ssge[ssge_idx].lkey;
371 }
372
373 dsge->addr = (uintptr_t)mr->virt + ssge[ssge_idx].addr - mr->start;
374 dsge->length = ssge[ssge_idx].length;
375 dsge->lkey = rdma_backend_mr_lkey(&mr->backend_mr);
376
377 pr_dbg("ssge->addr=0x%" PRIx64 "\n", ssge[ssge_idx].addr);
378 pr_dbg("dsge->addr=0x%" PRIx64 "\n", dsge->addr);
379 pr_dbg("dsge->length=%d\n", dsge->length);
380 pr_dbg("dsge->lkey=0x%x\n", dsge->lkey);
381
382 dsge++;
383 }
384
385 return 0;
386 }
387
388 static int mad_send(RdmaBackendDev *backend_dev, uint8_t sgid_idx,
389 union ibv_gid *sgid, struct ibv_sge *sge, uint32_t num_sge)
390 {
391 RdmaCmMuxMsg msg = {0};
392 char *hdr, *data;
393 int ret;
394
395 pr_dbg("num_sge=%d\n", num_sge);
396
397 if (num_sge != 2) {
398 return -EINVAL;
399 }
400
401 msg.hdr.op_code = RDMACM_MUX_OP_CODE_MAD;
402 memcpy(msg.hdr.sgid.raw, sgid->raw, sizeof(msg.hdr.sgid));
403
404 msg.umad_len = sge[0].length + sge[1].length;
405 pr_dbg("umad_len=%d\n", msg.umad_len);
406
407 if (msg.umad_len > sizeof(msg.umad.mad)) {
408 return -ENOMEM;
409 }
410
411 msg.umad.hdr.addr.qpn = htobe32(1);
412 msg.umad.hdr.addr.grh_present = 1;
413 pr_dbg("sgid_idx=%d\n", sgid_idx);
414 pr_dbg("sgid=0x%llx\n", sgid->global.interface_id);
415 msg.umad.hdr.addr.gid_index = sgid_idx;
416 memcpy(msg.umad.hdr.addr.gid, sgid->raw, sizeof(msg.umad.hdr.addr.gid));
417 msg.umad.hdr.addr.hop_limit = 0xFF;
418
419 hdr = rdma_pci_dma_map(backend_dev->dev, sge[0].addr, sge[0].length);
420 if (!hdr) {
421 pr_dbg("Fail to map to sge[0]\n");
422 return -ENOMEM;
423 }
424 data = rdma_pci_dma_map(backend_dev->dev, sge[1].addr, sge[1].length);
425 if (!data) {
426 pr_dbg("Fail to map to sge[1]\n");
427 rdma_pci_dma_unmap(backend_dev->dev, hdr, sge[0].length);
428 return -ENOMEM;
429 }
430
431 pr_dbg_buf("mad_hdr", hdr, sge[0].length);
432 pr_dbg_buf("mad_data", data, sge[1].length);
433
434 memcpy(&msg.umad.mad[0], hdr, sge[0].length);
435 memcpy(&msg.umad.mad[sge[0].length], data, sge[1].length);
436
437 rdma_pci_dma_unmap(backend_dev->dev, data, sge[1].length);
438 rdma_pci_dma_unmap(backend_dev->dev, hdr, sge[0].length);
439
440 ret = exec_rdmacm_mux_req(backend_dev, &msg);
441 if (ret) {
442 pr_dbg("Fail to send MAD to rdma_umadmux (%d)\n", ret);
443 return -EIO;
444 }
445
446 return 0;
447 }
448
449 void rdma_backend_post_send(RdmaBackendDev *backend_dev,
450 RdmaBackendQP *qp, uint8_t qp_type,
451 struct ibv_sge *sge, uint32_t num_sge,
452 uint8_t sgid_idx, union ibv_gid *sgid,
453 union ibv_gid *dgid, uint32_t dqpn, uint32_t dqkey,
454 void *ctx)
455 {
456 BackendCtx *bctx;
457 struct ibv_sge new_sge[MAX_SGE];
458 uint32_t bctx_id;
459 int rc;
460 struct ibv_send_wr wr = {0}, *bad_wr;
461
462 if (!qp->ibqp) { /* This field does not get initialized for QP0 and QP1 */
463 if (qp_type == IBV_QPT_SMI) {
464 pr_dbg("QP0 unsupported\n");
465 complete_work(IBV_WC_GENERAL_ERR, VENDOR_ERR_QP0, ctx);
466 } else if (qp_type == IBV_QPT_GSI) {
467 pr_dbg("QP1\n");
468 rc = mad_send(backend_dev, sgid_idx, sgid, sge, num_sge);
469 if (rc) {
470 complete_work(IBV_WC_GENERAL_ERR, VENDOR_ERR_MAD_SEND, ctx);
471 } else {
472 complete_work(IBV_WC_SUCCESS, 0, ctx);
473 }
474 }
475 return;
476 }
477
478 pr_dbg("num_sge=%d\n", num_sge);
479 if (!num_sge || num_sge > MAX_SGE) {
480 pr_dbg("invalid num_sge=%d\n", num_sge);
481 complete_work(IBV_WC_GENERAL_ERR, VENDOR_ERR_INV_NUM_SGE, ctx);
482 return;
483 }
484
485 bctx = g_malloc0(sizeof(*bctx));
486 bctx->up_ctx = ctx;
487 bctx->is_tx_req = 1;
488
489 rc = rdma_rm_alloc_cqe_ctx(backend_dev->rdma_dev_res, &bctx_id, bctx);
490 if (unlikely(rc)) {
491 pr_dbg("Failed to allocate cqe_ctx\n");
492 complete_work(IBV_WC_GENERAL_ERR, VENDOR_ERR_NOMEM, ctx);
493 goto out_free_bctx;
494 }
495
496 rc = build_host_sge_array(backend_dev->rdma_dev_res, new_sge, sge, num_sge);
497 if (rc) {
498 pr_dbg("Error: Failed to build host SGE array\n");
499 complete_work(IBV_WC_GENERAL_ERR, rc, ctx);
500 goto out_dealloc_cqe_ctx;
501 }
502
503 if (qp_type == IBV_QPT_UD) {
504 wr.wr.ud.ah = create_ah(backend_dev, qp->ibpd, sgid_idx, dgid);
505 if (!wr.wr.ud.ah) {
506 complete_work(IBV_WC_GENERAL_ERR, VENDOR_ERR_FAIL_BACKEND, ctx);
507 goto out_dealloc_cqe_ctx;
508 }
509 wr.wr.ud.remote_qpn = dqpn;
510 wr.wr.ud.remote_qkey = dqkey;
511 }
512
513 wr.num_sge = num_sge;
514 wr.opcode = IBV_WR_SEND;
515 wr.send_flags = IBV_SEND_SIGNALED;
516 wr.sg_list = new_sge;
517 wr.wr_id = bctx_id;
518
519 rc = ibv_post_send(qp->ibqp, &wr, &bad_wr);
520 pr_dbg("ibv_post_send=%d\n", rc);
521 if (rc) {
522 pr_dbg("Fail (%d, %d) to post send WQE to qpn %d\n", rc, errno,
523 qp->ibqp->qp_num);
524 complete_work(IBV_WC_GENERAL_ERR, VENDOR_ERR_FAIL_BACKEND, ctx);
525 goto out_dealloc_cqe_ctx;
526 }
527
528 return;
529
530 out_dealloc_cqe_ctx:
531 rdma_rm_dealloc_cqe_ctx(backend_dev->rdma_dev_res, bctx_id);
532
533 out_free_bctx:
534 g_free(bctx);
535 }
536
537 static unsigned int save_mad_recv_buffer(RdmaBackendDev *backend_dev,
538 struct ibv_sge *sge, uint32_t num_sge,
539 void *ctx)
540 {
541 BackendCtx *bctx;
542 int rc;
543 uint32_t bctx_id;
544
545 if (num_sge != 1) {
546 pr_dbg("Invalid num_sge (%d), expecting 1\n", num_sge);
547 return VENDOR_ERR_INV_NUM_SGE;
548 }
549
550 if (sge[0].length < RDMA_MAX_PRIVATE_DATA + sizeof(struct ibv_grh)) {
551 pr_dbg("Too small buffer for MAD\n");
552 return VENDOR_ERR_INV_MAD_BUFF;
553 }
554
555 pr_dbg("addr=0x%" PRIx64"\n", sge[0].addr);
556 pr_dbg("length=%d\n", sge[0].length);
557 pr_dbg("lkey=%d\n", sge[0].lkey);
558
559 bctx = g_malloc0(sizeof(*bctx));
560
561 rc = rdma_rm_alloc_cqe_ctx(backend_dev->rdma_dev_res, &bctx_id, bctx);
562 if (unlikely(rc)) {
563 g_free(bctx);
564 pr_dbg("Fail to allocate cqe_ctx\n");
565 return VENDOR_ERR_NOMEM;
566 }
567
568 pr_dbg("bctx_id %d, bctx %p, ctx %p\n", bctx_id, bctx, ctx);
569 bctx->up_ctx = ctx;
570 bctx->sge = *sge;
571
572 qemu_mutex_lock(&backend_dev->recv_mads_list.lock);
573 qlist_append_int(backend_dev->recv_mads_list.list, bctx_id);
574 qemu_mutex_unlock(&backend_dev->recv_mads_list.lock);
575
576 return 0;
577 }
578
579 void rdma_backend_post_recv(RdmaBackendDev *backend_dev,
580 RdmaDeviceResources *rdma_dev_res,
581 RdmaBackendQP *qp, uint8_t qp_type,
582 struct ibv_sge *sge, uint32_t num_sge, void *ctx)
583 {
584 BackendCtx *bctx;
585 struct ibv_sge new_sge[MAX_SGE];
586 uint32_t bctx_id;
587 int rc;
588 struct ibv_recv_wr wr = {0}, *bad_wr;
589
590 if (!qp->ibqp) { /* This field does not get initialized for QP0 and QP1 */
591 if (qp_type == IBV_QPT_SMI) {
592 pr_dbg("QP0 unsupported\n");
593 complete_work(IBV_WC_GENERAL_ERR, VENDOR_ERR_QP0, ctx);
594 }
595 if (qp_type == IBV_QPT_GSI) {
596 pr_dbg("QP1\n");
597 rc = save_mad_recv_buffer(backend_dev, sge, num_sge, ctx);
598 if (rc) {
599 complete_work(IBV_WC_GENERAL_ERR, rc, ctx);
600 }
601 }
602 return;
603 }
604
605 pr_dbg("num_sge=%d\n", num_sge);
606 if (!num_sge || num_sge > MAX_SGE) {
607 pr_dbg("invalid num_sge=%d\n", num_sge);
608 complete_work(IBV_WC_GENERAL_ERR, VENDOR_ERR_INV_NUM_SGE, ctx);
609 return;
610 }
611
612 bctx = g_malloc0(sizeof(*bctx));
613 bctx->up_ctx = ctx;
614 bctx->is_tx_req = 0;
615
616 rc = rdma_rm_alloc_cqe_ctx(rdma_dev_res, &bctx_id, bctx);
617 if (unlikely(rc)) {
618 pr_dbg("Failed to allocate cqe_ctx\n");
619 complete_work(IBV_WC_GENERAL_ERR, VENDOR_ERR_NOMEM, ctx);
620 goto out_free_bctx;
621 }
622
623 rc = build_host_sge_array(rdma_dev_res, new_sge, sge, num_sge);
624 if (rc) {
625 pr_dbg("Error: Failed to build host SGE array\n");
626 complete_work(IBV_WC_GENERAL_ERR, rc, ctx);
627 goto out_dealloc_cqe_ctx;
628 }
629
630 wr.num_sge = num_sge;
631 wr.sg_list = new_sge;
632 wr.wr_id = bctx_id;
633 rc = ibv_post_recv(qp->ibqp, &wr, &bad_wr);
634 pr_dbg("ibv_post_recv=%d\n", rc);
635 if (rc) {
636 pr_dbg("Fail (%d, %d) to post recv WQE to qpn %d\n", rc, errno,
637 qp->ibqp->qp_num);
638 complete_work(IBV_WC_GENERAL_ERR, VENDOR_ERR_FAIL_BACKEND, ctx);
639 goto out_dealloc_cqe_ctx;
640 }
641
642 return;
643
644 out_dealloc_cqe_ctx:
645 rdma_rm_dealloc_cqe_ctx(rdma_dev_res, bctx_id);
646
647 out_free_bctx:
648 g_free(bctx);
649 }
650
651 int rdma_backend_create_pd(RdmaBackendDev *backend_dev, RdmaBackendPD *pd)
652 {
653 pd->ibpd = ibv_alloc_pd(backend_dev->context);
654
655 return pd->ibpd ? 0 : -EIO;
656 }
657
658 void rdma_backend_destroy_pd(RdmaBackendPD *pd)
659 {
660 if (pd->ibpd) {
661 ibv_dealloc_pd(pd->ibpd);
662 }
663 }
664
665 int rdma_backend_create_mr(RdmaBackendMR *mr, RdmaBackendPD *pd, void *addr,
666 size_t length, int access)
667 {
668 pr_dbg("addr=0x%p\n", addr);
669 pr_dbg("len=%zu\n", length);
670 mr->ibmr = ibv_reg_mr(pd->ibpd, addr, length, access);
671 if (mr->ibmr) {
672 pr_dbg("lkey=0x%x\n", mr->ibmr->lkey);
673 pr_dbg("rkey=0x%x\n", mr->ibmr->rkey);
674 mr->ibpd = pd->ibpd;
675 }
676
677 return mr->ibmr ? 0 : -EIO;
678 }
679
680 void rdma_backend_destroy_mr(RdmaBackendMR *mr)
681 {
682 if (mr->ibmr) {
683 ibv_dereg_mr(mr->ibmr);
684 }
685 }
686
687 int rdma_backend_create_cq(RdmaBackendDev *backend_dev, RdmaBackendCQ *cq,
688 int cqe)
689 {
690 int rc;
691
692 pr_dbg("cqe=%d\n", cqe);
693
694 pr_dbg("dev->channel=%p\n", backend_dev->channel);
695 cq->ibcq = ibv_create_cq(backend_dev->context, cqe + 1, NULL,
696 backend_dev->channel, 0);
697
698 if (cq->ibcq) {
699 rc = ibv_req_notify_cq(cq->ibcq, 0);
700 if (rc) {
701 pr_dbg("Error %d from ibv_req_notify_cq\n", rc);
702 }
703 cq->backend_dev = backend_dev;
704 }
705
706 return cq->ibcq ? 0 : -EIO;
707 }
708
709 void rdma_backend_destroy_cq(RdmaBackendCQ *cq)
710 {
711 if (cq->ibcq) {
712 ibv_destroy_cq(cq->ibcq);
713 }
714 }
715
716 int rdma_backend_create_qp(RdmaBackendQP *qp, uint8_t qp_type,
717 RdmaBackendPD *pd, RdmaBackendCQ *scq,
718 RdmaBackendCQ *rcq, uint32_t max_send_wr,
719 uint32_t max_recv_wr, uint32_t max_send_sge,
720 uint32_t max_recv_sge)
721 {
722 struct ibv_qp_init_attr attr = {0};
723
724 qp->ibqp = 0;
725 pr_dbg("qp_type=%d\n", qp_type);
726
727 switch (qp_type) {
728 case IBV_QPT_GSI:
729 return 0;
730
731 case IBV_QPT_RC:
732 /* fall through */
733 case IBV_QPT_UD:
734 /* do nothing */
735 break;
736
737 default:
738 pr_dbg("Unsupported QP type %d\n", qp_type);
739 return -EIO;
740 }
741
742 attr.qp_type = qp_type;
743 attr.send_cq = scq->ibcq;
744 attr.recv_cq = rcq->ibcq;
745 attr.cap.max_send_wr = max_send_wr;
746 attr.cap.max_recv_wr = max_recv_wr;
747 attr.cap.max_send_sge = max_send_sge;
748 attr.cap.max_recv_sge = max_recv_sge;
749
750 pr_dbg("max_send_wr=%d\n", max_send_wr);
751 pr_dbg("max_recv_wr=%d\n", max_recv_wr);
752 pr_dbg("max_send_sge=%d\n", max_send_sge);
753 pr_dbg("max_recv_sge=%d\n", max_recv_sge);
754
755 qp->ibqp = ibv_create_qp(pd->ibpd, &attr);
756 if (likely(!qp->ibqp)) {
757 pr_dbg("Error from ibv_create_qp\n");
758 return -EIO;
759 }
760
761 qp->ibpd = pd->ibpd;
762
763 /* TODO: Query QP to get max_inline_data and save it to be used in send */
764
765 pr_dbg("qpn=0x%x\n", qp->ibqp->qp_num);
766
767 return 0;
768 }
769
770 int rdma_backend_qp_state_init(RdmaBackendDev *backend_dev, RdmaBackendQP *qp,
771 uint8_t qp_type, uint32_t qkey)
772 {
773 struct ibv_qp_attr attr = {0};
774 int rc, attr_mask;
775
776 pr_dbg("qpn=0x%x\n", qp->ibqp->qp_num);
777 pr_dbg("sport_num=%d\n", backend_dev->port_num);
778
779 attr_mask = IBV_QP_STATE | IBV_QP_PKEY_INDEX | IBV_QP_PORT;
780 attr.qp_state = IBV_QPS_INIT;
781 attr.pkey_index = 0;
782 attr.port_num = backend_dev->port_num;
783
784 switch (qp_type) {
785 case IBV_QPT_RC:
786 attr_mask |= IBV_QP_ACCESS_FLAGS;
787 break;
788
789 case IBV_QPT_UD:
790 attr.qkey = qkey;
791 attr_mask |= IBV_QP_QKEY;
792 break;
793
794 default:
795 pr_dbg("Unsupported QP type %d\n", qp_type);
796 return -EIO;
797 }
798
799 rc = ibv_modify_qp(qp->ibqp, &attr, attr_mask);
800 if (rc) {
801 pr_dbg("Error %d from ibv_modify_qp\n", rc);
802 return -EIO;
803 }
804
805 return 0;
806 }
807
808 int rdma_backend_qp_state_rtr(RdmaBackendDev *backend_dev, RdmaBackendQP *qp,
809 uint8_t qp_type, uint8_t sgid_idx,
810 union ibv_gid *dgid, uint32_t dqpn,
811 uint32_t rq_psn, uint32_t qkey, bool use_qkey)
812 {
813 struct ibv_qp_attr attr = {0};
814 union ibv_gid ibv_gid = {
815 .global.interface_id = dgid->global.interface_id,
816 .global.subnet_prefix = dgid->global.subnet_prefix
817 };
818 int rc, attr_mask;
819
820 attr.qp_state = IBV_QPS_RTR;
821 attr_mask = IBV_QP_STATE;
822
823 qp->sgid_idx = sgid_idx;
824
825 switch (qp_type) {
826 case IBV_QPT_RC:
827 pr_dbg("dgid=0x%" PRIx64 ",%" PRIx64 "\n",
828 be64_to_cpu(ibv_gid.global.subnet_prefix),
829 be64_to_cpu(ibv_gid.global.interface_id));
830 pr_dbg("dqpn=0x%x\n", dqpn);
831 pr_dbg("sgid_idx=%d\n", qp->sgid_idx);
832 pr_dbg("sport_num=%d\n", backend_dev->port_num);
833 pr_dbg("rq_psn=0x%x\n", rq_psn);
834
835 attr.path_mtu = IBV_MTU_1024;
836 attr.dest_qp_num = dqpn;
837 attr.max_dest_rd_atomic = 1;
838 attr.min_rnr_timer = 12;
839 attr.ah_attr.port_num = backend_dev->port_num;
840 attr.ah_attr.is_global = 1;
841 attr.ah_attr.grh.hop_limit = 1;
842 attr.ah_attr.grh.dgid = ibv_gid;
843 attr.ah_attr.grh.sgid_index = qp->sgid_idx;
844 attr.rq_psn = rq_psn;
845
846 attr_mask |= IBV_QP_AV | IBV_QP_PATH_MTU | IBV_QP_DEST_QPN |
847 IBV_QP_RQ_PSN | IBV_QP_MAX_DEST_RD_ATOMIC |
848 IBV_QP_MIN_RNR_TIMER;
849 break;
850
851 case IBV_QPT_UD:
852 pr_dbg("qkey=0x%x\n", qkey);
853 if (use_qkey) {
854 attr.qkey = qkey;
855 attr_mask |= IBV_QP_QKEY;
856 }
857 break;
858 }
859
860 rc = ibv_modify_qp(qp->ibqp, &attr, attr_mask);
861 if (rc) {
862 pr_dbg("Error %d from ibv_modify_qp\n", rc);
863 return -EIO;
864 }
865
866 return 0;
867 }
868
869 int rdma_backend_qp_state_rts(RdmaBackendQP *qp, uint8_t qp_type,
870 uint32_t sq_psn, uint32_t qkey, bool use_qkey)
871 {
872 struct ibv_qp_attr attr = {0};
873 int rc, attr_mask;
874
875 pr_dbg("qpn=0x%x\n", qp->ibqp->qp_num);
876 pr_dbg("sq_psn=0x%x\n", sq_psn);
877
878 attr.qp_state = IBV_QPS_RTS;
879 attr.sq_psn = sq_psn;
880 attr_mask = IBV_QP_STATE | IBV_QP_SQ_PSN;
881
882 switch (qp_type) {
883 case IBV_QPT_RC:
884 attr.timeout = 14;
885 attr.retry_cnt = 7;
886 attr.rnr_retry = 7;
887 attr.max_rd_atomic = 1;
888
889 attr_mask |= IBV_QP_TIMEOUT | IBV_QP_RETRY_CNT | IBV_QP_RNR_RETRY |
890 IBV_QP_MAX_QP_RD_ATOMIC;
891 break;
892
893 case IBV_QPT_UD:
894 if (use_qkey) {
895 pr_dbg("qkey=0x%x\n", qkey);
896 attr.qkey = qkey;
897 attr_mask |= IBV_QP_QKEY;
898 }
899 break;
900 }
901
902 rc = ibv_modify_qp(qp->ibqp, &attr, attr_mask);
903 if (rc) {
904 pr_dbg("Error %d from ibv_modify_qp\n", rc);
905 return -EIO;
906 }
907
908 return 0;
909 }
910
911 int rdma_backend_query_qp(RdmaBackendQP *qp, struct ibv_qp_attr *attr,
912 int attr_mask, struct ibv_qp_init_attr *init_attr)
913 {
914 if (!qp->ibqp) {
915 pr_dbg("QP1\n");
916 attr->qp_state = IBV_QPS_RTS;
917 return 0;
918 }
919
920 return ibv_query_qp(qp->ibqp, attr, attr_mask, init_attr);
921 }
922
923 void rdma_backend_destroy_qp(RdmaBackendQP *qp)
924 {
925 if (qp->ibqp) {
926 ibv_destroy_qp(qp->ibqp);
927 }
928 }
929
930 #define CHK_ATTR(req, dev, member, fmt) ({ \
931 pr_dbg("%s="fmt","fmt"\n", #member, dev.member, req->member); \
932 if (req->member > dev.member) { \
933 warn_report("%s = "fmt" is higher than host device capability "fmt, \
934 #member, req->member, dev.member); \
935 req->member = dev.member; \
936 } \
937 pr_dbg("%s="fmt"\n", #member, req->member); })
938
939 static int init_device_caps(RdmaBackendDev *backend_dev,
940 struct ibv_device_attr *dev_attr)
941 {
942 if (ibv_query_device(backend_dev->context, &backend_dev->dev_attr)) {
943 return -EIO;
944 }
945
946 CHK_ATTR(dev_attr, backend_dev->dev_attr, max_mr_size, "%" PRId64);
947 CHK_ATTR(dev_attr, backend_dev->dev_attr, max_qp, "%d");
948 CHK_ATTR(dev_attr, backend_dev->dev_attr, max_sge, "%d");
949 CHK_ATTR(dev_attr, backend_dev->dev_attr, max_qp_wr, "%d");
950 CHK_ATTR(dev_attr, backend_dev->dev_attr, max_cq, "%d");
951 CHK_ATTR(dev_attr, backend_dev->dev_attr, max_cqe, "%d");
952 CHK_ATTR(dev_attr, backend_dev->dev_attr, max_mr, "%d");
953 CHK_ATTR(dev_attr, backend_dev->dev_attr, max_pd, "%d");
954 CHK_ATTR(dev_attr, backend_dev->dev_attr, max_qp_rd_atom, "%d");
955 CHK_ATTR(dev_attr, backend_dev->dev_attr, max_qp_init_rd_atom, "%d");
956 CHK_ATTR(dev_attr, backend_dev->dev_attr, max_ah, "%d");
957
958 return 0;
959 }
960
961 static inline void build_mad_hdr(struct ibv_grh *grh, union ibv_gid *sgid,
962 union ibv_gid *my_gid, int paylen)
963 {
964 grh->paylen = htons(paylen);
965 grh->sgid = *sgid;
966 grh->dgid = *my_gid;
967
968 pr_dbg("paylen=%d (net=0x%x)\n", paylen, grh->paylen);
969 pr_dbg("dgid=0x%llx\n", my_gid->global.interface_id);
970 pr_dbg("sgid=0x%llx\n", sgid->global.interface_id);
971 }
972
973 static void process_incoming_mad_req(RdmaBackendDev *backend_dev,
974 RdmaCmMuxMsg *msg)
975 {
976 QObject *o_ctx_id;
977 unsigned long cqe_ctx_id;
978 BackendCtx *bctx;
979 char *mad;
980
981 pr_dbg("umad_len=%d\n", msg->umad_len);
982
983 #ifdef PVRDMA_DEBUG
984 struct umad_hdr *hdr = (struct umad_hdr *)&msg->umad.mad;
985 pr_dbg("bv %x cls %x cv %x mtd %x st %d tid %" PRIx64 " at %x atm %x\n",
986 hdr->base_version, hdr->mgmt_class, hdr->class_version,
987 hdr->method, hdr->status, be64toh(hdr->tid),
988 hdr->attr_id, hdr->attr_mod);
989 #endif
990
991 qemu_mutex_lock(&backend_dev->recv_mads_list.lock);
992 o_ctx_id = qlist_pop(backend_dev->recv_mads_list.list);
993 qemu_mutex_unlock(&backend_dev->recv_mads_list.lock);
994 if (!o_ctx_id) {
995 pr_dbg("No more free MADs buffers, waiting for a while\n");
996 sleep(THR_POLL_TO);
997 return;
998 }
999
1000 cqe_ctx_id = qnum_get_uint(qobject_to(QNum, o_ctx_id));
1001 bctx = rdma_rm_get_cqe_ctx(backend_dev->rdma_dev_res, cqe_ctx_id);
1002 if (unlikely(!bctx)) {
1003 pr_dbg("Error: Fail to find ctx for %ld\n", cqe_ctx_id);
1004 return;
1005 }
1006
1007 pr_dbg("id %ld, bctx %p, ctx %p\n", cqe_ctx_id, bctx, bctx->up_ctx);
1008
1009 mad = rdma_pci_dma_map(backend_dev->dev, bctx->sge.addr,
1010 bctx->sge.length);
1011 if (!mad || bctx->sge.length < msg->umad_len + MAD_HDR_SIZE) {
1012 complete_work(IBV_WC_GENERAL_ERR, VENDOR_ERR_INV_MAD_BUFF,
1013 bctx->up_ctx);
1014 } else {
1015 struct ibv_wc wc = {0};
1016 pr_dbg_buf("mad", msg->umad.mad, msg->umad_len);
1017 memset(mad, 0, bctx->sge.length);
1018 build_mad_hdr((struct ibv_grh *)mad,
1019 (union ibv_gid *)&msg->umad.hdr.addr.gid, &msg->hdr.sgid,
1020 msg->umad_len);
1021 memcpy(&mad[MAD_HDR_SIZE], msg->umad.mad, msg->umad_len);
1022 rdma_pci_dma_unmap(backend_dev->dev, mad, bctx->sge.length);
1023
1024 wc.byte_len = msg->umad_len;
1025 wc.status = IBV_WC_SUCCESS;
1026 wc.wc_flags = IBV_WC_GRH;
1027 comp_handler(bctx->up_ctx, &wc);
1028 }
1029
1030 g_free(bctx);
1031 rdma_rm_dealloc_cqe_ctx(backend_dev->rdma_dev_res, cqe_ctx_id);
1032 }
1033
1034 static inline int rdmacm_mux_can_receive(void *opaque)
1035 {
1036 RdmaBackendDev *backend_dev = (RdmaBackendDev *)opaque;
1037
1038 return rdmacm_mux_can_process_async(backend_dev);
1039 }
1040
1041 static void rdmacm_mux_read(void *opaque, const uint8_t *buf, int size)
1042 {
1043 RdmaBackendDev *backend_dev = (RdmaBackendDev *)opaque;
1044 RdmaCmMuxMsg *msg = (RdmaCmMuxMsg *)buf;
1045
1046 pr_dbg("Got %d bytes\n", size);
1047 pr_dbg("msg_type=%d\n", msg->hdr.msg_type);
1048 pr_dbg("op_code=%d\n", msg->hdr.op_code);
1049
1050 if (msg->hdr.msg_type != RDMACM_MUX_MSG_TYPE_REQ &&
1051 msg->hdr.op_code != RDMACM_MUX_OP_CODE_MAD) {
1052 pr_dbg("Error: Not a MAD request, skipping\n");
1053 return;
1054 }
1055 process_incoming_mad_req(backend_dev, msg);
1056 }
1057
1058 static int mad_init(RdmaBackendDev *backend_dev, CharBackend *mad_chr_be)
1059 {
1060 int ret;
1061
1062 backend_dev->rdmacm_mux.chr_be = mad_chr_be;
1063
1064 ret = qemu_chr_fe_backend_connected(backend_dev->rdmacm_mux.chr_be);
1065 if (!ret) {
1066 pr_dbg("Missing chardev for MAD multiplexer\n");
1067 return -EIO;
1068 }
1069
1070 qemu_mutex_init(&backend_dev->recv_mads_list.lock);
1071 backend_dev->recv_mads_list.list = qlist_new();
1072
1073 enable_rdmacm_mux_async(backend_dev);
1074
1075 qemu_chr_fe_set_handlers(backend_dev->rdmacm_mux.chr_be,
1076 rdmacm_mux_can_receive, rdmacm_mux_read, NULL,
1077 NULL, backend_dev, NULL, true);
1078
1079 return 0;
1080 }
1081
1082 static void mad_fini(RdmaBackendDev *backend_dev)
1083 {
1084 pr_dbg("Stopping MAD\n");
1085 disable_rdmacm_mux_async(backend_dev);
1086 qemu_chr_fe_disconnect(backend_dev->rdmacm_mux.chr_be);
1087 qlist_destroy_obj(QOBJECT(backend_dev->recv_mads_list.list));
1088 qemu_mutex_destroy(&backend_dev->recv_mads_list.lock);
1089 }
1090
1091 int rdma_backend_get_gid_index(RdmaBackendDev *backend_dev,
1092 union ibv_gid *gid)
1093 {
1094 union ibv_gid sgid;
1095 int ret;
1096 int i = 0;
1097
1098 pr_dbg("0x%llx, 0x%llx\n",
1099 (long long unsigned int)be64_to_cpu(gid->global.subnet_prefix),
1100 (long long unsigned int)be64_to_cpu(gid->global.interface_id));
1101
1102 do {
1103 ret = ibv_query_gid(backend_dev->context, backend_dev->port_num, i,
1104 &sgid);
1105 i++;
1106 } while (!ret && (memcmp(&sgid, gid, sizeof(*gid))));
1107
1108 pr_dbg("gid_index=%d\n", i - 1);
1109
1110 return ret ? ret : i - 1;
1111 }
1112
1113 int rdma_backend_add_gid(RdmaBackendDev *backend_dev, const char *ifname,
1114 union ibv_gid *gid)
1115 {
1116 RdmaCmMuxMsg msg = {0};
1117 int ret;
1118
1119 pr_dbg("0x%llx, 0x%llx\n",
1120 (long long unsigned int)be64_to_cpu(gid->global.subnet_prefix),
1121 (long long unsigned int)be64_to_cpu(gid->global.interface_id));
1122
1123 msg.hdr.op_code = RDMACM_MUX_OP_CODE_REG;
1124 memcpy(msg.hdr.sgid.raw, gid->raw, sizeof(msg.hdr.sgid));
1125
1126 ret = exec_rdmacm_mux_req(backend_dev, &msg);
1127 if (ret) {
1128 pr_dbg("Fail to register GID to rdma_umadmux (%d)\n", ret);
1129 return -EIO;
1130 }
1131
1132 qapi_event_send_rdma_gid_status_changed(ifname, true,
1133 gid->global.subnet_prefix,
1134 gid->global.interface_id);
1135
1136 return ret;
1137 }
1138
1139 int rdma_backend_del_gid(RdmaBackendDev *backend_dev, const char *ifname,
1140 union ibv_gid *gid)
1141 {
1142 RdmaCmMuxMsg msg = {0};
1143 int ret;
1144
1145 pr_dbg("0x%llx, 0x%llx\n",
1146 (long long unsigned int)be64_to_cpu(gid->global.subnet_prefix),
1147 (long long unsigned int)be64_to_cpu(gid->global.interface_id));
1148
1149 msg.hdr.op_code = RDMACM_MUX_OP_CODE_UNREG;
1150 memcpy(msg.hdr.sgid.raw, gid->raw, sizeof(msg.hdr.sgid));
1151
1152 ret = exec_rdmacm_mux_req(backend_dev, &msg);
1153 if (ret) {
1154 pr_dbg("Fail to unregister GID from rdma_umadmux (%d)\n", ret);
1155 return -EIO;
1156 }
1157
1158 qapi_event_send_rdma_gid_status_changed(ifname, false,
1159 gid->global.subnet_prefix,
1160 gid->global.interface_id);
1161
1162 return 0;
1163 }
1164
1165 int rdma_backend_init(RdmaBackendDev *backend_dev, PCIDevice *pdev,
1166 RdmaDeviceResources *rdma_dev_res,
1167 const char *backend_device_name, uint8_t port_num,
1168 struct ibv_device_attr *dev_attr, CharBackend *mad_chr_be,
1169 Error **errp)
1170 {
1171 int i;
1172 int ret = 0;
1173 int num_ibv_devices;
1174 struct ibv_device **dev_list;
1175
1176 memset(backend_dev, 0, sizeof(*backend_dev));
1177
1178 backend_dev->dev = pdev;
1179 backend_dev->port_num = port_num;
1180 backend_dev->rdma_dev_res = rdma_dev_res;
1181
1182 rdma_backend_register_comp_handler(dummy_comp_handler);
1183
1184 dev_list = ibv_get_device_list(&num_ibv_devices);
1185 if (!dev_list) {
1186 error_setg(errp, "Failed to get IB devices list");
1187 return -EIO;
1188 }
1189
1190 if (num_ibv_devices == 0) {
1191 error_setg(errp, "No IB devices were found");
1192 ret = -ENXIO;
1193 goto out_free_dev_list;
1194 }
1195
1196 if (backend_device_name) {
1197 for (i = 0; dev_list[i]; ++i) {
1198 if (!strcmp(ibv_get_device_name(dev_list[i]),
1199 backend_device_name)) {
1200 break;
1201 }
1202 }
1203
1204 backend_dev->ib_dev = dev_list[i];
1205 if (!backend_dev->ib_dev) {
1206 error_setg(errp, "Failed to find IB device %s",
1207 backend_device_name);
1208 ret = -EIO;
1209 goto out_free_dev_list;
1210 }
1211 } else {
1212 backend_dev->ib_dev = *dev_list;
1213 }
1214
1215 pr_dbg("Using backend device %s, port %d\n",
1216 ibv_get_device_name(backend_dev->ib_dev), backend_dev->port_num);
1217 pr_dbg("uverb device %s\n", backend_dev->ib_dev->dev_name);
1218
1219 backend_dev->context = ibv_open_device(backend_dev->ib_dev);
1220 if (!backend_dev->context) {
1221 error_setg(errp, "Failed to open IB device");
1222 ret = -EIO;
1223 goto out;
1224 }
1225
1226 backend_dev->channel = ibv_create_comp_channel(backend_dev->context);
1227 if (!backend_dev->channel) {
1228 error_setg(errp, "Failed to create IB communication channel");
1229 ret = -EIO;
1230 goto out_close_device;
1231 }
1232 pr_dbg("dev->backend_dev.channel=%p\n", backend_dev->channel);
1233
1234 ret = init_device_caps(backend_dev, dev_attr);
1235 if (ret) {
1236 error_setg(errp, "Failed to initialize device capabilities");
1237 ret = -EIO;
1238 goto out_destroy_comm_channel;
1239 }
1240
1241
1242 ret = mad_init(backend_dev, mad_chr_be);
1243 if (ret) {
1244 error_setg(errp, "Fail to initialize mad");
1245 ret = -EIO;
1246 goto out_destroy_comm_channel;
1247 }
1248
1249 backend_dev->comp_thread.run = false;
1250 backend_dev->comp_thread.is_running = false;
1251
1252 ah_cache_init();
1253
1254 goto out_free_dev_list;
1255
1256 out_destroy_comm_channel:
1257 ibv_destroy_comp_channel(backend_dev->channel);
1258
1259 out_close_device:
1260 ibv_close_device(backend_dev->context);
1261
1262 out_free_dev_list:
1263 ibv_free_device_list(dev_list);
1264
1265 out:
1266 return ret;
1267 }
1268
1269
1270 void rdma_backend_start(RdmaBackendDev *backend_dev)
1271 {
1272 pr_dbg("Starting rdma_backend\n");
1273 start_comp_thread(backend_dev);
1274 }
1275
1276 void rdma_backend_stop(RdmaBackendDev *backend_dev)
1277 {
1278 pr_dbg("Stopping rdma_backend\n");
1279 stop_backend_thread(&backend_dev->comp_thread);
1280 }
1281
1282 void rdma_backend_fini(RdmaBackendDev *backend_dev)
1283 {
1284 rdma_backend_stop(backend_dev);
1285 mad_fini(backend_dev);
1286 g_hash_table_destroy(ah_hash);
1287 ibv_destroy_comp_channel(backend_dev->channel);
1288 ibv_close_device(backend_dev->context);
1289 }