qdev: don't access name through info
[qemu.git] / hw / realview.c
1 /*
2 * ARM RealView Baseboard System emulation.
3 *
4 * Copyright (c) 2006-2007 CodeSourcery.
5 * Written by Paul Brook
6 *
7 * This code is licensed under the GPL.
8 */
9
10 #include "sysbus.h"
11 #include "arm-misc.h"
12 #include "primecell.h"
13 #include "devices.h"
14 #include "pci.h"
15 #include "usb-ohci.h"
16 #include "net.h"
17 #include "sysemu.h"
18 #include "boards.h"
19 #include "bitbang_i2c.h"
20 #include "blockdev.h"
21 #include "exec-memory.h"
22
23 #define SMP_BOOT_ADDR 0xe0000000
24 #define SMP_BOOTREG_ADDR 0x10000030
25
26 typedef struct {
27 SysBusDevice busdev;
28 MemoryRegion iomem;
29 bitbang_i2c_interface *bitbang;
30 int out;
31 int in;
32 } RealViewI2CState;
33
34 static uint64_t realview_i2c_read(void *opaque, target_phys_addr_t offset,
35 unsigned size)
36 {
37 RealViewI2CState *s = (RealViewI2CState *)opaque;
38
39 if (offset == 0) {
40 return (s->out & 1) | (s->in << 1);
41 } else {
42 hw_error("realview_i2c_read: Bad offset 0x%x\n", (int)offset);
43 return -1;
44 }
45 }
46
47 static void realview_i2c_write(void *opaque, target_phys_addr_t offset,
48 uint64_t value, unsigned size)
49 {
50 RealViewI2CState *s = (RealViewI2CState *)opaque;
51
52 switch (offset) {
53 case 0:
54 s->out |= value & 3;
55 break;
56 case 4:
57 s->out &= ~value;
58 break;
59 default:
60 hw_error("realview_i2c_write: Bad offset 0x%x\n", (int)offset);
61 }
62 bitbang_i2c_set(s->bitbang, BITBANG_I2C_SCL, (s->out & 1) != 0);
63 s->in = bitbang_i2c_set(s->bitbang, BITBANG_I2C_SDA, (s->out & 2) != 0);
64 }
65
66 static const MemoryRegionOps realview_i2c_ops = {
67 .read = realview_i2c_read,
68 .write = realview_i2c_write,
69 .endianness = DEVICE_NATIVE_ENDIAN,
70 };
71
72 static int realview_i2c_init(SysBusDevice *dev)
73 {
74 RealViewI2CState *s = FROM_SYSBUS(RealViewI2CState, dev);
75 i2c_bus *bus;
76
77 bus = i2c_init_bus(&dev->qdev, "i2c");
78 s->bitbang = bitbang_i2c_init(bus);
79 memory_region_init_io(&s->iomem, &realview_i2c_ops, s,
80 "realview-i2c", 0x1000);
81 sysbus_init_mmio(dev, &s->iomem);
82 return 0;
83 }
84
85 static SysBusDeviceInfo realview_i2c_info = {
86 .init = realview_i2c_init,
87 .qdev.name = "realview_i2c",
88 .qdev.size = sizeof(RealViewI2CState),
89 };
90
91 static void realview_register_devices(void)
92 {
93 sysbus_register_withprop(&realview_i2c_info);
94 }
95
96 /* Board init. */
97
98 static struct arm_boot_info realview_binfo = {
99 .smp_loader_start = SMP_BOOT_ADDR,
100 .smp_bootreg_addr = SMP_BOOTREG_ADDR,
101 };
102
103 /* The following two lists must be consistent. */
104 enum realview_board_type {
105 BOARD_EB,
106 BOARD_EB_MPCORE,
107 BOARD_PB_A8,
108 BOARD_PBX_A9,
109 };
110
111 static const int realview_board_id[] = {
112 0x33b,
113 0x33b,
114 0x769,
115 0x76d
116 };
117
118 static void realview_init(ram_addr_t ram_size,
119 const char *boot_device,
120 const char *kernel_filename, const char *kernel_cmdline,
121 const char *initrd_filename, const char *cpu_model,
122 enum realview_board_type board_type)
123 {
124 CPUState *env = NULL;
125 MemoryRegion *sysmem = get_system_memory();
126 MemoryRegion *ram_lo = g_new(MemoryRegion, 1);
127 MemoryRegion *ram_hi = g_new(MemoryRegion, 1);
128 MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
129 MemoryRegion *ram_hack = g_new(MemoryRegion, 1);
130 DeviceState *dev, *sysctl, *gpio2, *pl041;
131 SysBusDevice *busdev;
132 qemu_irq *irqp;
133 qemu_irq pic[64];
134 qemu_irq mmc_irq[2];
135 PCIBus *pci_bus;
136 NICInfo *nd;
137 i2c_bus *i2c;
138 int n;
139 int done_nic = 0;
140 qemu_irq cpu_irq[4];
141 int is_mpcore = 0;
142 int is_pb = 0;
143 uint32_t proc_id = 0;
144 uint32_t sys_id;
145 ram_addr_t low_ram_size;
146
147 switch (board_type) {
148 case BOARD_EB:
149 break;
150 case BOARD_EB_MPCORE:
151 is_mpcore = 1;
152 break;
153 case BOARD_PB_A8:
154 is_pb = 1;
155 break;
156 case BOARD_PBX_A9:
157 is_mpcore = 1;
158 is_pb = 1;
159 break;
160 }
161 for (n = 0; n < smp_cpus; n++) {
162 env = cpu_init(cpu_model);
163 if (!env) {
164 fprintf(stderr, "Unable to find CPU definition\n");
165 exit(1);
166 }
167 irqp = arm_pic_init_cpu(env);
168 cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
169 }
170 if (arm_feature(env, ARM_FEATURE_V7)) {
171 if (is_mpcore) {
172 proc_id = 0x0c000000;
173 } else {
174 proc_id = 0x0e000000;
175 }
176 } else if (arm_feature(env, ARM_FEATURE_V6K)) {
177 proc_id = 0x06000000;
178 } else if (arm_feature(env, ARM_FEATURE_V6)) {
179 proc_id = 0x04000000;
180 } else {
181 proc_id = 0x02000000;
182 }
183
184 if (is_pb && ram_size > 0x20000000) {
185 /* Core tile RAM. */
186 low_ram_size = ram_size - 0x20000000;
187 ram_size = 0x20000000;
188 memory_region_init_ram(ram_lo, "realview.lowmem", low_ram_size);
189 vmstate_register_ram_global(ram_lo);
190 memory_region_add_subregion(sysmem, 0x20000000, ram_lo);
191 }
192
193 memory_region_init_ram(ram_hi, "realview.highmem", ram_size);
194 vmstate_register_ram_global(ram_hi);
195 low_ram_size = ram_size;
196 if (low_ram_size > 0x10000000)
197 low_ram_size = 0x10000000;
198 /* SDRAM at address zero. */
199 memory_region_init_alias(ram_alias, "realview.alias",
200 ram_hi, 0, low_ram_size);
201 memory_region_add_subregion(sysmem, 0, ram_alias);
202 if (is_pb) {
203 /* And again at a high address. */
204 memory_region_add_subregion(sysmem, 0x70000000, ram_hi);
205 } else {
206 ram_size = low_ram_size;
207 }
208
209 sys_id = is_pb ? 0x01780500 : 0xc1400400;
210 sysctl = qdev_create(NULL, "realview_sysctl");
211 qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
212 qdev_init_nofail(sysctl);
213 qdev_prop_set_uint32(sysctl, "proc_id", proc_id);
214 sysbus_mmio_map(sysbus_from_qdev(sysctl), 0, 0x10000000);
215
216 if (is_mpcore) {
217 dev = qdev_create(NULL, is_pb ? "a9mpcore_priv": "realview_mpcore");
218 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
219 qdev_init_nofail(dev);
220 busdev = sysbus_from_qdev(dev);
221 if (is_pb) {
222 realview_binfo.smp_priv_base = 0x1f000000;
223 } else {
224 realview_binfo.smp_priv_base = 0x10100000;
225 }
226 sysbus_mmio_map(busdev, 0, realview_binfo.smp_priv_base);
227 for (n = 0; n < smp_cpus; n++) {
228 sysbus_connect_irq(busdev, n, cpu_irq[n]);
229 }
230 sysbus_create_varargs("l2x0", realview_binfo.smp_priv_base + 0x2000,
231 NULL);
232 } else {
233 uint32_t gic_addr = is_pb ? 0x1e000000 : 0x10040000;
234 /* For now just create the nIRQ GIC, and ignore the others. */
235 dev = sysbus_create_simple("realview_gic", gic_addr, cpu_irq[0]);
236 }
237 for (n = 0; n < 64; n++) {
238 pic[n] = qdev_get_gpio_in(dev, n);
239 }
240
241 pl041 = qdev_create(NULL, "pl041");
242 qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
243 qdev_init_nofail(pl041);
244 sysbus_mmio_map(sysbus_from_qdev(pl041), 0, 0x10004000);
245 sysbus_connect_irq(sysbus_from_qdev(pl041), 0, pic[19]);
246
247 sysbus_create_simple("pl050_keyboard", 0x10006000, pic[20]);
248 sysbus_create_simple("pl050_mouse", 0x10007000, pic[21]);
249
250 sysbus_create_simple("pl011", 0x10009000, pic[12]);
251 sysbus_create_simple("pl011", 0x1000a000, pic[13]);
252 sysbus_create_simple("pl011", 0x1000b000, pic[14]);
253 sysbus_create_simple("pl011", 0x1000c000, pic[15]);
254
255 /* DMA controller is optional, apparently. */
256 sysbus_create_simple("pl081", 0x10030000, pic[24]);
257
258 sysbus_create_simple("sp804", 0x10011000, pic[4]);
259 sysbus_create_simple("sp804", 0x10012000, pic[5]);
260
261 sysbus_create_simple("pl061", 0x10013000, pic[6]);
262 sysbus_create_simple("pl061", 0x10014000, pic[7]);
263 gpio2 = sysbus_create_simple("pl061", 0x10015000, pic[8]);
264
265 sysbus_create_simple("pl111", 0x10020000, pic[23]);
266
267 dev = sysbus_create_varargs("pl181", 0x10005000, pic[17], pic[18], NULL);
268 /* Wire up MMC card detect and read-only signals. These have
269 * to go to both the PL061 GPIO and the sysctl register.
270 * Note that the PL181 orders these lines (readonly,inserted)
271 * and the PL061 has them the other way about. Also the card
272 * detect line is inverted.
273 */
274 mmc_irq[0] = qemu_irq_split(
275 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT),
276 qdev_get_gpio_in(gpio2, 1));
277 mmc_irq[1] = qemu_irq_split(
278 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN),
279 qemu_irq_invert(qdev_get_gpio_in(gpio2, 0)));
280 qdev_connect_gpio_out(dev, 0, mmc_irq[0]);
281 qdev_connect_gpio_out(dev, 1, mmc_irq[1]);
282
283 sysbus_create_simple("pl031", 0x10017000, pic[10]);
284
285 if (!is_pb) {
286 dev = qdev_create(NULL, "realview_pci");
287 busdev = sysbus_from_qdev(dev);
288 qdev_init_nofail(dev);
289 sysbus_mmio_map(busdev, 0, 0x61000000); /* PCI self-config */
290 sysbus_mmio_map(busdev, 1, 0x62000000); /* PCI config */
291 sysbus_mmio_map(busdev, 2, 0x63000000); /* PCI I/O */
292 sysbus_connect_irq(busdev, 0, pic[48]);
293 sysbus_connect_irq(busdev, 1, pic[49]);
294 sysbus_connect_irq(busdev, 2, pic[50]);
295 sysbus_connect_irq(busdev, 3, pic[51]);
296 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci");
297 if (usb_enabled) {
298 usb_ohci_init_pci(pci_bus, -1);
299 }
300 n = drive_get_max_bus(IF_SCSI);
301 while (n >= 0) {
302 pci_create_simple(pci_bus, -1, "lsi53c895a");
303 n--;
304 }
305 }
306 for(n = 0; n < nb_nics; n++) {
307 nd = &nd_table[n];
308
309 if (!done_nic && (!nd->model ||
310 strcmp(nd->model, is_pb ? "lan9118" : "smc91c111") == 0)) {
311 if (is_pb) {
312 lan9118_init(nd, 0x4e000000, pic[28]);
313 } else {
314 smc91c111_init(nd, 0x4e000000, pic[28]);
315 }
316 done_nic = 1;
317 } else {
318 pci_nic_init_nofail(nd, "rtl8139", NULL);
319 }
320 }
321
322 dev = sysbus_create_simple("realview_i2c", 0x10002000, NULL);
323 i2c = (i2c_bus *)qdev_get_child_bus(dev, "i2c");
324 i2c_create_slave(i2c, "ds1338", 0x68);
325
326 /* Memory map for RealView Emulation Baseboard: */
327 /* 0x10000000 System registers. */
328 /* 0x10001000 System controller. */
329 /* 0x10002000 Two-Wire Serial Bus. */
330 /* 0x10003000 Reserved. */
331 /* 0x10004000 AACI. */
332 /* 0x10005000 MCI. */
333 /* 0x10006000 KMI0. */
334 /* 0x10007000 KMI1. */
335 /* 0x10008000 Character LCD. (EB) */
336 /* 0x10009000 UART0. */
337 /* 0x1000a000 UART1. */
338 /* 0x1000b000 UART2. */
339 /* 0x1000c000 UART3. */
340 /* 0x1000d000 SSPI. */
341 /* 0x1000e000 SCI. */
342 /* 0x1000f000 Reserved. */
343 /* 0x10010000 Watchdog. */
344 /* 0x10011000 Timer 0+1. */
345 /* 0x10012000 Timer 2+3. */
346 /* 0x10013000 GPIO 0. */
347 /* 0x10014000 GPIO 1. */
348 /* 0x10015000 GPIO 2. */
349 /* 0x10002000 Two-Wire Serial Bus - DVI. (PB) */
350 /* 0x10017000 RTC. */
351 /* 0x10018000 DMC. */
352 /* 0x10019000 PCI controller config. */
353 /* 0x10020000 CLCD. */
354 /* 0x10030000 DMA Controller. */
355 /* 0x10040000 GIC1. (EB) */
356 /* 0x10050000 GIC2. (EB) */
357 /* 0x10060000 GIC3. (EB) */
358 /* 0x10070000 GIC4. (EB) */
359 /* 0x10080000 SMC. */
360 /* 0x1e000000 GIC1. (PB) */
361 /* 0x1e001000 GIC2. (PB) */
362 /* 0x1e002000 GIC3. (PB) */
363 /* 0x1e003000 GIC4. (PB) */
364 /* 0x40000000 NOR flash. */
365 /* 0x44000000 DoC flash. */
366 /* 0x48000000 SRAM. */
367 /* 0x4c000000 Configuration flash. */
368 /* 0x4e000000 Ethernet. */
369 /* 0x4f000000 USB. */
370 /* 0x50000000 PISMO. */
371 /* 0x54000000 PISMO. */
372 /* 0x58000000 PISMO. */
373 /* 0x5c000000 PISMO. */
374 /* 0x60000000 PCI. */
375 /* 0x61000000 PCI Self Config. */
376 /* 0x62000000 PCI Config. */
377 /* 0x63000000 PCI IO. */
378 /* 0x64000000 PCI mem 0. */
379 /* 0x68000000 PCI mem 1. */
380 /* 0x6c000000 PCI mem 2. */
381
382 /* ??? Hack to map an additional page of ram for the secondary CPU
383 startup code. I guess this works on real hardware because the
384 BootROM happens to be in ROM/flash or in memory that isn't clobbered
385 until after Linux boots the secondary CPUs. */
386 memory_region_init_ram(ram_hack, "realview.hack", 0x1000);
387 vmstate_register_ram_global(ram_hack);
388 memory_region_add_subregion(sysmem, SMP_BOOT_ADDR, ram_hack);
389
390 realview_binfo.ram_size = ram_size;
391 realview_binfo.kernel_filename = kernel_filename;
392 realview_binfo.kernel_cmdline = kernel_cmdline;
393 realview_binfo.initrd_filename = initrd_filename;
394 realview_binfo.nb_cpus = smp_cpus;
395 realview_binfo.board_id = realview_board_id[board_type];
396 realview_binfo.loader_start = (board_type == BOARD_PB_A8 ? 0x70000000 : 0);
397 arm_load_kernel(first_cpu, &realview_binfo);
398 }
399
400 static void realview_eb_init(ram_addr_t ram_size,
401 const char *boot_device,
402 const char *kernel_filename, const char *kernel_cmdline,
403 const char *initrd_filename, const char *cpu_model)
404 {
405 if (!cpu_model) {
406 cpu_model = "arm926";
407 }
408 realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
409 initrd_filename, cpu_model, BOARD_EB);
410 }
411
412 static void realview_eb_mpcore_init(ram_addr_t ram_size,
413 const char *boot_device,
414 const char *kernel_filename, const char *kernel_cmdline,
415 const char *initrd_filename, const char *cpu_model)
416 {
417 if (!cpu_model) {
418 cpu_model = "arm11mpcore";
419 }
420 realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
421 initrd_filename, cpu_model, BOARD_EB_MPCORE);
422 }
423
424 static void realview_pb_a8_init(ram_addr_t ram_size,
425 const char *boot_device,
426 const char *kernel_filename, const char *kernel_cmdline,
427 const char *initrd_filename, const char *cpu_model)
428 {
429 if (!cpu_model) {
430 cpu_model = "cortex-a8";
431 }
432 realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
433 initrd_filename, cpu_model, BOARD_PB_A8);
434 }
435
436 static void realview_pbx_a9_init(ram_addr_t ram_size,
437 const char *boot_device,
438 const char *kernel_filename, const char *kernel_cmdline,
439 const char *initrd_filename, const char *cpu_model)
440 {
441 if (!cpu_model) {
442 cpu_model = "cortex-a9";
443 }
444 realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
445 initrd_filename, cpu_model, BOARD_PBX_A9);
446 }
447
448 static QEMUMachine realview_eb_machine = {
449 .name = "realview-eb",
450 .desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)",
451 .init = realview_eb_init,
452 .use_scsi = 1,
453 };
454
455 static QEMUMachine realview_eb_mpcore_machine = {
456 .name = "realview-eb-mpcore",
457 .desc = "ARM RealView Emulation Baseboard (ARM11MPCore)",
458 .init = realview_eb_mpcore_init,
459 .use_scsi = 1,
460 .max_cpus = 4,
461 };
462
463 static QEMUMachine realview_pb_a8_machine = {
464 .name = "realview-pb-a8",
465 .desc = "ARM RealView Platform Baseboard for Cortex-A8",
466 .init = realview_pb_a8_init,
467 };
468
469 static QEMUMachine realview_pbx_a9_machine = {
470 .name = "realview-pbx-a9",
471 .desc = "ARM RealView Platform Baseboard Explore for Cortex-A9",
472 .init = realview_pbx_a9_init,
473 .use_scsi = 1,
474 .max_cpus = 4,
475 };
476
477 static void realview_machine_init(void)
478 {
479 qemu_register_machine(&realview_eb_machine);
480 qemu_register_machine(&realview_eb_mpcore_machine);
481 qemu_register_machine(&realview_pb_a8_machine);
482 qemu_register_machine(&realview_pbx_a9_machine);
483 }
484
485 machine_init(realview_machine_init);
486 device_init(realview_register_devices)