hw/arm/bcm2836: Only provide "enabled-cpus" property to multicore SoCs
[qemu.git] / hw / riscv / boot.c
1 /*
2 * QEMU RISC-V Boot Helper
3 *
4 * Copyright (c) 2017 SiFive, Inc.
5 * Copyright (c) 2019 Alistair Francis <alistair.francis@wdc.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2 or later, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu-common.h"
22 #include "qemu/units.h"
23 #include "qemu/error-report.h"
24 #include "exec/cpu-defs.h"
25 #include "hw/boards.h"
26 #include "hw/loader.h"
27 #include "hw/riscv/boot.h"
28 #include "hw/riscv/boot_opensbi.h"
29 #include "elf.h"
30 #include "sysemu/device_tree.h"
31 #include "sysemu/qtest.h"
32
33 #include <libfdt.h>
34
35 #if defined(TARGET_RISCV32)
36 #define fw_dynamic_info_data(__val) cpu_to_le32(__val)
37 #else
38 #define fw_dynamic_info_data(__val) cpu_to_le64(__val)
39 #endif
40
41 bool riscv_is_32_bit(MachineState *machine)
42 {
43 if (!strncmp(machine->cpu_type, "rv32", 4)) {
44 return true;
45 } else {
46 return false;
47 }
48 }
49
50 target_ulong riscv_calc_kernel_start_addr(MachineState *machine,
51 target_ulong firmware_end_addr) {
52 if (riscv_is_32_bit(machine)) {
53 return QEMU_ALIGN_UP(firmware_end_addr, 4 * MiB);
54 } else {
55 return QEMU_ALIGN_UP(firmware_end_addr, 2 * MiB);
56 }
57 }
58
59 target_ulong riscv_find_and_load_firmware(MachineState *machine,
60 const char *default_machine_firmware,
61 hwaddr firmware_load_addr,
62 symbol_fn_t sym_cb)
63 {
64 char *firmware_filename = NULL;
65 target_ulong firmware_end_addr = firmware_load_addr;
66
67 if ((!machine->firmware) || (!strcmp(machine->firmware, "default"))) {
68 /*
69 * The user didn't specify -bios, or has specified "-bios default".
70 * That means we are going to load the OpenSBI binary included in
71 * the QEMU source.
72 */
73 firmware_filename = riscv_find_firmware(default_machine_firmware);
74 } else if (strcmp(machine->firmware, "none")) {
75 firmware_filename = riscv_find_firmware(machine->firmware);
76 }
77
78 if (firmware_filename) {
79 /* If not "none" load the firmware */
80 firmware_end_addr = riscv_load_firmware(firmware_filename,
81 firmware_load_addr, sym_cb);
82 g_free(firmware_filename);
83 }
84
85 return firmware_end_addr;
86 }
87
88 char *riscv_find_firmware(const char *firmware_filename)
89 {
90 char *filename;
91
92 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, firmware_filename);
93 if (filename == NULL) {
94 if (!qtest_enabled()) {
95 /*
96 * We only ship plain binary bios images in the QEMU source.
97 * With Spike machine that uses ELF images as the default bios,
98 * running QEMU test will complain hence let's suppress the error
99 * report for QEMU testing.
100 */
101 error_report("Unable to load the RISC-V firmware \"%s\"",
102 firmware_filename);
103 exit(1);
104 }
105 }
106
107 return filename;
108 }
109
110 target_ulong riscv_load_firmware(const char *firmware_filename,
111 hwaddr firmware_load_addr,
112 symbol_fn_t sym_cb)
113 {
114 uint64_t firmware_entry, firmware_size, firmware_end;
115
116 if (load_elf_ram_sym(firmware_filename, NULL, NULL, NULL,
117 &firmware_entry, NULL, &firmware_end, NULL,
118 0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) {
119 return firmware_end;
120 }
121
122 firmware_size = load_image_targphys_as(firmware_filename,
123 firmware_load_addr, ram_size, NULL);
124
125 if (firmware_size > 0) {
126 return firmware_load_addr + firmware_size;
127 }
128
129 error_report("could not load firmware '%s'", firmware_filename);
130 exit(1);
131 }
132
133 target_ulong riscv_load_kernel(const char *kernel_filename,
134 target_ulong kernel_start_addr,
135 symbol_fn_t sym_cb)
136 {
137 uint64_t kernel_entry;
138
139 if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL,
140 &kernel_entry, NULL, NULL, NULL, 0,
141 EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) {
142 return kernel_entry;
143 }
144
145 if (load_uimage_as(kernel_filename, &kernel_entry, NULL, NULL,
146 NULL, NULL, NULL) > 0) {
147 return kernel_entry;
148 }
149
150 if (load_image_targphys_as(kernel_filename, kernel_start_addr,
151 ram_size, NULL) > 0) {
152 return kernel_start_addr;
153 }
154
155 error_report("could not load kernel '%s'", kernel_filename);
156 exit(1);
157 }
158
159 hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
160 uint64_t kernel_entry, hwaddr *start)
161 {
162 int size;
163
164 /*
165 * We want to put the initrd far enough into RAM that when the
166 * kernel is uncompressed it will not clobber the initrd. However
167 * on boards without much RAM we must ensure that we still leave
168 * enough room for a decent sized initrd, and on boards with large
169 * amounts of RAM we must avoid the initrd being so far up in RAM
170 * that it is outside lowmem and inaccessible to the kernel.
171 * So for boards with less than 256MB of RAM we put the initrd
172 * halfway into RAM, and for boards with 256MB of RAM or more we put
173 * the initrd at 128MB.
174 */
175 *start = kernel_entry + MIN(mem_size / 2, 128 * MiB);
176
177 size = load_ramdisk(filename, *start, mem_size - *start);
178 if (size == -1) {
179 size = load_image_targphys(filename, *start, mem_size - *start);
180 if (size == -1) {
181 error_report("could not load ramdisk '%s'", filename);
182 exit(1);
183 }
184 }
185
186 return *start + size;
187 }
188
189 uint32_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)
190 {
191 uint32_t temp, fdt_addr;
192 hwaddr dram_end = dram_base + mem_size;
193 int fdtsize = fdt_totalsize(fdt);
194
195 if (fdtsize <= 0) {
196 error_report("invalid device-tree");
197 exit(1);
198 }
199
200 /*
201 * We should put fdt as far as possible to avoid kernel/initrd overwriting
202 * its content. But it should be addressable by 32 bit system as well.
203 * Thus, put it at an aligned address that less than fdt size from end of
204 * dram or 4GB whichever is lesser.
205 */
206 temp = MIN(dram_end, 4096 * MiB);
207 fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB);
208
209 fdt_pack(fdt);
210 /* copy in the device tree */
211 qemu_fdt_dumpdtb(fdt, fdtsize);
212
213 rom_add_blob_fixed_as("fdt", fdt, fdtsize, fdt_addr,
214 &address_space_memory);
215
216 return fdt_addr;
217 }
218
219 void riscv_rom_copy_firmware_info(hwaddr rom_base, hwaddr rom_size,
220 uint32_t reset_vec_size, uint64_t kernel_entry)
221 {
222 struct fw_dynamic_info dinfo;
223 size_t dinfo_len;
224
225 dinfo.magic = fw_dynamic_info_data(FW_DYNAMIC_INFO_MAGIC_VALUE);
226 dinfo.version = fw_dynamic_info_data(FW_DYNAMIC_INFO_VERSION);
227 dinfo.next_mode = fw_dynamic_info_data(FW_DYNAMIC_INFO_NEXT_MODE_S);
228 dinfo.next_addr = fw_dynamic_info_data(kernel_entry);
229 dinfo.options = 0;
230 dinfo.boot_hart = 0;
231 dinfo_len = sizeof(dinfo);
232
233 /**
234 * copy the dynamic firmware info. This information is specific to
235 * OpenSBI but doesn't break any other firmware as long as they don't
236 * expect any certain value in "a2" register.
237 */
238 if (dinfo_len > (rom_size - reset_vec_size)) {
239 error_report("not enough space to store dynamic firmware info");
240 exit(1);
241 }
242
243 rom_add_blob_fixed_as("mrom.finfo", &dinfo, dinfo_len,
244 rom_base + reset_vec_size,
245 &address_space_memory);
246 }
247
248 void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base,
249 hwaddr rom_size, uint64_t kernel_entry,
250 uint32_t fdt_load_addr, void *fdt)
251 {
252 int i;
253 uint32_t start_addr_hi32 = 0x00000000;
254
255 #if defined(TARGET_RISCV64)
256 start_addr_hi32 = start_addr >> 32;
257 #endif
258 /* reset vector */
259 uint32_t reset_vec[10] = {
260 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */
261 0x02828613, /* addi a2, t0, %pcrel_lo(1b) */
262 0xf1402573, /* csrr a0, mhartid */
263 #if defined(TARGET_RISCV32)
264 0x0202a583, /* lw a1, 32(t0) */
265 0x0182a283, /* lw t0, 24(t0) */
266 #elif defined(TARGET_RISCV64)
267 0x0202b583, /* ld a1, 32(t0) */
268 0x0182b283, /* ld t0, 24(t0) */
269 #endif
270 0x00028067, /* jr t0 */
271 start_addr, /* start: .dword */
272 start_addr_hi32,
273 fdt_load_addr, /* fdt_laddr: .dword */
274 0x00000000,
275 /* fw_dyn: */
276 };
277
278 /* copy in the reset vector in little_endian byte order */
279 for (i = 0; i < ARRAY_SIZE(reset_vec); i++) {
280 reset_vec[i] = cpu_to_le32(reset_vec[i]);
281 }
282 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
283 rom_base, &address_space_memory);
284 riscv_rom_copy_firmware_info(rom_base, rom_size, sizeof(reset_vec),
285 kernel_entry);
286
287 return;
288 }