Merge tag 'ide-pull-request' of https://gitlab.com/jsnow/qemu into staging
[qemu.git] / hw / riscv / opentitan.c
1 /*
2 * QEMU RISC-V Board Compatible with OpenTitan FPGA platform
3 *
4 * Copyright (c) 2020 Western Digital
5 *
6 * Provides a board compatible with the OpenTitan FPGA platform:
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "hw/riscv/opentitan.h"
23 #include "qapi/error.h"
24 #include "hw/boards.h"
25 #include "hw/misc/unimp.h"
26 #include "hw/riscv/boot.h"
27 #include "qemu/units.h"
28 #include "sysemu/sysemu.h"
29
30 static const MemMapEntry ibex_memmap[] = {
31 [IBEX_DEV_ROM] = { 0x00008000, 16 * KiB },
32 [IBEX_DEV_RAM] = { 0x10000000, 0x10000 },
33 [IBEX_DEV_FLASH] = { 0x20000000, 0x80000 },
34 [IBEX_DEV_UART] = { 0x40000000, 0x1000 },
35 [IBEX_DEV_GPIO] = { 0x40040000, 0x1000 },
36 [IBEX_DEV_SPI] = { 0x40050000, 0x1000 },
37 [IBEX_DEV_I2C] = { 0x40080000, 0x1000 },
38 [IBEX_DEV_PATTGEN] = { 0x400e0000, 0x1000 },
39 [IBEX_DEV_RV_TIMER] = { 0x40100000, 0x1000 },
40 [IBEX_DEV_SENSOR_CTRL] = { 0x40110000, 0x1000 },
41 [IBEX_DEV_OTP_CTRL] = { 0x40130000, 0x4000 },
42 [IBEX_DEV_PWRMGR] = { 0x40400000, 0x1000 },
43 [IBEX_DEV_RSTMGR] = { 0x40410000, 0x1000 },
44 [IBEX_DEV_CLKMGR] = { 0x40420000, 0x1000 },
45 [IBEX_DEV_PINMUX] = { 0x40460000, 0x1000 },
46 [IBEX_DEV_PADCTRL] = { 0x40470000, 0x1000 },
47 [IBEX_DEV_USBDEV] = { 0x40500000, 0x1000 },
48 [IBEX_DEV_FLASH_CTRL] = { 0x41000000, 0x1000 },
49 [IBEX_DEV_PLIC] = { 0x41010000, 0x1000 },
50 [IBEX_DEV_AES] = { 0x41100000, 0x1000 },
51 [IBEX_DEV_HMAC] = { 0x41110000, 0x1000 },
52 [IBEX_DEV_KMAC] = { 0x41120000, 0x1000 },
53 [IBEX_DEV_KEYMGR] = { 0x41130000, 0x1000 },
54 [IBEX_DEV_CSRNG] = { 0x41150000, 0x1000 },
55 [IBEX_DEV_ENTROPY] = { 0x41160000, 0x1000 },
56 [IBEX_DEV_EDNO] = { 0x41170000, 0x1000 },
57 [IBEX_DEV_EDN1] = { 0x41180000, 0x1000 },
58 [IBEX_DEV_ALERT_HANDLER] = { 0x411b0000, 0x1000 },
59 [IBEX_DEV_NMI_GEN] = { 0x411c0000, 0x1000 },
60 [IBEX_DEV_OTBN] = { 0x411d0000, 0x10000 },
61 };
62
63 static void opentitan_board_init(MachineState *machine)
64 {
65 const MemMapEntry *memmap = ibex_memmap;
66 OpenTitanState *s = g_new0(OpenTitanState, 1);
67 MemoryRegion *sys_mem = get_system_memory();
68 MemoryRegion *main_mem = g_new(MemoryRegion, 1);
69
70 /* Initialize SoC */
71 object_initialize_child(OBJECT(machine), "soc", &s->soc,
72 TYPE_RISCV_IBEX_SOC);
73 qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
74
75 memory_region_init_ram(main_mem, NULL, "riscv.lowrisc.ibex.ram",
76 memmap[IBEX_DEV_RAM].size, &error_fatal);
77 memory_region_add_subregion(sys_mem,
78 memmap[IBEX_DEV_RAM].base, main_mem);
79
80 if (machine->firmware) {
81 riscv_load_firmware(machine->firmware, memmap[IBEX_DEV_RAM].base, NULL);
82 }
83
84 if (machine->kernel_filename) {
85 riscv_load_kernel(machine->kernel_filename,
86 memmap[IBEX_DEV_RAM].base, NULL);
87 }
88 }
89
90 static void opentitan_machine_init(MachineClass *mc)
91 {
92 mc->desc = "RISC-V Board compatible with OpenTitan";
93 mc->init = opentitan_board_init;
94 mc->max_cpus = 1;
95 mc->default_cpu_type = TYPE_RISCV_CPU_IBEX;
96 }
97
98 DEFINE_MACHINE("opentitan", opentitan_machine_init)
99
100 static void lowrisc_ibex_soc_init(Object *obj)
101 {
102 LowRISCIbexSoCState *s = RISCV_IBEX_SOC(obj);
103
104 object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
105
106 object_initialize_child(obj, "plic", &s->plic, TYPE_IBEX_PLIC);
107
108 object_initialize_child(obj, "uart", &s->uart, TYPE_IBEX_UART);
109 }
110
111 static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
112 {
113 const MemMapEntry *memmap = ibex_memmap;
114 MachineState *ms = MACHINE(qdev_get_machine());
115 LowRISCIbexSoCState *s = RISCV_IBEX_SOC(dev_soc);
116 MemoryRegion *sys_mem = get_system_memory();
117
118 object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type,
119 &error_abort);
120 object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
121 &error_abort);
122 object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8080, &error_abort);
123 sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
124
125 /* Boot ROM */
126 memory_region_init_rom(&s->rom, OBJECT(dev_soc), "riscv.lowrisc.ibex.rom",
127 memmap[IBEX_DEV_ROM].size, &error_fatal);
128 memory_region_add_subregion(sys_mem,
129 memmap[IBEX_DEV_ROM].base, &s->rom);
130
131 /* Flash memory */
132 memory_region_init_rom(&s->flash_mem, OBJECT(dev_soc), "riscv.lowrisc.ibex.flash",
133 memmap[IBEX_DEV_FLASH].size, &error_fatal);
134 memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_FLASH].base,
135 &s->flash_mem);
136
137 /* PLIC */
138 if (!sysbus_realize(SYS_BUS_DEVICE(&s->plic), errp)) {
139 return;
140 }
141 sysbus_mmio_map(SYS_BUS_DEVICE(&s->plic), 0, memmap[IBEX_DEV_PLIC].base);
142
143 /* UART */
144 qdev_prop_set_chr(DEVICE(&(s->uart)), "chardev", serial_hd(0));
145 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart), errp)) {
146 return;
147 }
148 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart), 0, memmap[IBEX_DEV_UART].base);
149 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
150 0, qdev_get_gpio_in(DEVICE(&s->plic),
151 IBEX_UART0_TX_WATERMARK_IRQ));
152 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
153 1, qdev_get_gpio_in(DEVICE(&s->plic),
154 IBEX_UART0_RX_WATERMARK_IRQ));
155 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
156 2, qdev_get_gpio_in(DEVICE(&s->plic),
157 IBEX_UART0_TX_EMPTY_IRQ));
158 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
159 3, qdev_get_gpio_in(DEVICE(&s->plic),
160 IBEX_UART0_RX_OVERFLOW_IRQ));
161
162 create_unimplemented_device("riscv.lowrisc.ibex.gpio",
163 memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size);
164 create_unimplemented_device("riscv.lowrisc.ibex.spi",
165 memmap[IBEX_DEV_SPI].base, memmap[IBEX_DEV_SPI].size);
166 create_unimplemented_device("riscv.lowrisc.ibex.i2c",
167 memmap[IBEX_DEV_I2C].base, memmap[IBEX_DEV_I2C].size);
168 create_unimplemented_device("riscv.lowrisc.ibex.pattgen",
169 memmap[IBEX_DEV_PATTGEN].base, memmap[IBEX_DEV_PATTGEN].size);
170 create_unimplemented_device("riscv.lowrisc.ibex.rv_timer",
171 memmap[IBEX_DEV_RV_TIMER].base, memmap[IBEX_DEV_RV_TIMER].size);
172 create_unimplemented_device("riscv.lowrisc.ibex.sensor_ctrl",
173 memmap[IBEX_DEV_SENSOR_CTRL].base, memmap[IBEX_DEV_SENSOR_CTRL].size);
174 create_unimplemented_device("riscv.lowrisc.ibex.otp_ctrl",
175 memmap[IBEX_DEV_OTP_CTRL].base, memmap[IBEX_DEV_OTP_CTRL].size);
176 create_unimplemented_device("riscv.lowrisc.ibex.pwrmgr",
177 memmap[IBEX_DEV_PWRMGR].base, memmap[IBEX_DEV_PWRMGR].size);
178 create_unimplemented_device("riscv.lowrisc.ibex.rstmgr",
179 memmap[IBEX_DEV_RSTMGR].base, memmap[IBEX_DEV_RSTMGR].size);
180 create_unimplemented_device("riscv.lowrisc.ibex.clkmgr",
181 memmap[IBEX_DEV_CLKMGR].base, memmap[IBEX_DEV_CLKMGR].size);
182 create_unimplemented_device("riscv.lowrisc.ibex.pinmux",
183 memmap[IBEX_DEV_PINMUX].base, memmap[IBEX_DEV_PINMUX].size);
184 create_unimplemented_device("riscv.lowrisc.ibex.padctrl",
185 memmap[IBEX_DEV_PADCTRL].base, memmap[IBEX_DEV_PADCTRL].size);
186 create_unimplemented_device("riscv.lowrisc.ibex.usbdev",
187 memmap[IBEX_DEV_USBDEV].base, memmap[IBEX_DEV_USBDEV].size);
188 create_unimplemented_device("riscv.lowrisc.ibex.flash_ctrl",
189 memmap[IBEX_DEV_FLASH_CTRL].base, memmap[IBEX_DEV_FLASH_CTRL].size);
190 create_unimplemented_device("riscv.lowrisc.ibex.aes",
191 memmap[IBEX_DEV_AES].base, memmap[IBEX_DEV_AES].size);
192 create_unimplemented_device("riscv.lowrisc.ibex.hmac",
193 memmap[IBEX_DEV_HMAC].base, memmap[IBEX_DEV_HMAC].size);
194 create_unimplemented_device("riscv.lowrisc.ibex.kmac",
195 memmap[IBEX_DEV_KMAC].base, memmap[IBEX_DEV_KMAC].size);
196 create_unimplemented_device("riscv.lowrisc.ibex.keymgr",
197 memmap[IBEX_DEV_KEYMGR].base, memmap[IBEX_DEV_KEYMGR].size);
198 create_unimplemented_device("riscv.lowrisc.ibex.csrng",
199 memmap[IBEX_DEV_CSRNG].base, memmap[IBEX_DEV_CSRNG].size);
200 create_unimplemented_device("riscv.lowrisc.ibex.entropy",
201 memmap[IBEX_DEV_ENTROPY].base, memmap[IBEX_DEV_ENTROPY].size);
202 create_unimplemented_device("riscv.lowrisc.ibex.edn0",
203 memmap[IBEX_DEV_EDNO].base, memmap[IBEX_DEV_EDNO].size);
204 create_unimplemented_device("riscv.lowrisc.ibex.edn1",
205 memmap[IBEX_DEV_EDN1].base, memmap[IBEX_DEV_EDN1].size);
206 create_unimplemented_device("riscv.lowrisc.ibex.alert_handler",
207 memmap[IBEX_DEV_ALERT_HANDLER].base, memmap[IBEX_DEV_ALERT_HANDLER].size);
208 create_unimplemented_device("riscv.lowrisc.ibex.nmi_gen",
209 memmap[IBEX_DEV_NMI_GEN].base, memmap[IBEX_DEV_NMI_GEN].size);
210 create_unimplemented_device("riscv.lowrisc.ibex.otbn",
211 memmap[IBEX_DEV_OTBN].base, memmap[IBEX_DEV_OTBN].size);
212 }
213
214 static void lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data)
215 {
216 DeviceClass *dc = DEVICE_CLASS(oc);
217
218 dc->realize = lowrisc_ibex_soc_realize;
219 /* Reason: Uses serial_hds in realize function, thus can't be used twice */
220 dc->user_creatable = false;
221 }
222
223 static const TypeInfo lowrisc_ibex_soc_type_info = {
224 .name = TYPE_RISCV_IBEX_SOC,
225 .parent = TYPE_DEVICE,
226 .instance_size = sizeof(LowRISCIbexSoCState),
227 .instance_init = lowrisc_ibex_soc_init,
228 .class_init = lowrisc_ibex_soc_class_init,
229 };
230
231 static void lowrisc_ibex_soc_register_types(void)
232 {
233 type_register_static(&lowrisc_ibex_soc_type_info);
234 }
235
236 type_init(lowrisc_ibex_soc_register_types)