Merge remote-tracking branch 'remotes/philmd-gitlab/tags/renesas-20201027' into staging
[qemu.git] / hw / riscv / opentitan.c
1 /*
2 * QEMU RISC-V Board Compatible with OpenTitan FPGA platform
3 *
4 * Copyright (c) 2020 Western Digital
5 *
6 * Provides a board compatible with the OpenTitan FPGA platform:
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "hw/riscv/opentitan.h"
23 #include "qapi/error.h"
24 #include "hw/boards.h"
25 #include "hw/misc/unimp.h"
26 #include "hw/riscv/boot.h"
27 #include "exec/address-spaces.h"
28 #include "qemu/units.h"
29 #include "sysemu/sysemu.h"
30
31 static const struct MemmapEntry {
32 hwaddr base;
33 hwaddr size;
34 } ibex_memmap[] = {
35 [IBEX_DEV_ROM] = { 0x00008000, 16 * KiB },
36 [IBEX_DEV_RAM] = { 0x10000000, 0x10000 },
37 [IBEX_DEV_FLASH] = { 0x20000000, 0x80000 },
38 [IBEX_DEV_UART] = { 0x40000000, 0x10000 },
39 [IBEX_DEV_GPIO] = { 0x40010000, 0x10000 },
40 [IBEX_DEV_SPI] = { 0x40020000, 0x10000 },
41 [IBEX_DEV_FLASH_CTRL] = { 0x40030000, 0x10000 },
42 [IBEX_DEV_PINMUX] = { 0x40070000, 0x10000 },
43 [IBEX_DEV_RV_TIMER] = { 0x40080000, 0x10000 },
44 [IBEX_DEV_PLIC] = { 0x40090000, 0x10000 },
45 [IBEX_DEV_PWRMGR] = { 0x400A0000, 0x10000 },
46 [IBEX_DEV_RSTMGR] = { 0x400B0000, 0x10000 },
47 [IBEX_DEV_CLKMGR] = { 0x400C0000, 0x10000 },
48 [IBEX_DEV_AES] = { 0x40110000, 0x10000 },
49 [IBEX_DEV_HMAC] = { 0x40120000, 0x10000 },
50 [IBEX_DEV_ALERT_HANDLER] = { 0x40130000, 0x10000 },
51 [IBEX_DEV_NMI_GEN] = { 0x40140000, 0x10000 },
52 [IBEX_DEV_USBDEV] = { 0x40150000, 0x10000 },
53 [IBEX_DEV_PADCTRL] = { 0x40160000, 0x10000 }
54 };
55
56 static void opentitan_board_init(MachineState *machine)
57 {
58 const struct MemmapEntry *memmap = ibex_memmap;
59 OpenTitanState *s = g_new0(OpenTitanState, 1);
60 MemoryRegion *sys_mem = get_system_memory();
61 MemoryRegion *main_mem = g_new(MemoryRegion, 1);
62
63 /* Initialize SoC */
64 object_initialize_child(OBJECT(machine), "soc", &s->soc,
65 TYPE_RISCV_IBEX_SOC);
66 qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
67
68 memory_region_init_ram(main_mem, NULL, "riscv.lowrisc.ibex.ram",
69 memmap[IBEX_DEV_RAM].size, &error_fatal);
70 memory_region_add_subregion(sys_mem,
71 memmap[IBEX_DEV_RAM].base, main_mem);
72
73 if (machine->firmware) {
74 riscv_load_firmware(machine->firmware, memmap[IBEX_DEV_RAM].base, NULL);
75 }
76
77 if (machine->kernel_filename) {
78 riscv_load_kernel(machine->kernel_filename,
79 memmap[IBEX_DEV_RAM].base, NULL);
80 }
81 }
82
83 static void opentitan_machine_init(MachineClass *mc)
84 {
85 mc->desc = "RISC-V Board compatible with OpenTitan";
86 mc->init = opentitan_board_init;
87 mc->max_cpus = 1;
88 mc->default_cpu_type = TYPE_RISCV_CPU_IBEX;
89 }
90
91 DEFINE_MACHINE("opentitan", opentitan_machine_init)
92
93 static void lowrisc_ibex_soc_init(Object *obj)
94 {
95 LowRISCIbexSoCState *s = RISCV_IBEX_SOC(obj);
96
97 object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
98
99 object_initialize_child(obj, "plic", &s->plic, TYPE_IBEX_PLIC);
100
101 object_initialize_child(obj, "uart", &s->uart, TYPE_IBEX_UART);
102 }
103
104 static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
105 {
106 const struct MemmapEntry *memmap = ibex_memmap;
107 MachineState *ms = MACHINE(qdev_get_machine());
108 LowRISCIbexSoCState *s = RISCV_IBEX_SOC(dev_soc);
109 MemoryRegion *sys_mem = get_system_memory();
110
111 object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type,
112 &error_abort);
113 object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
114 &error_abort);
115 object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8090, &error_abort);
116 sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
117
118 /* Boot ROM */
119 memory_region_init_rom(&s->rom, OBJECT(dev_soc), "riscv.lowrisc.ibex.rom",
120 memmap[IBEX_DEV_ROM].size, &error_fatal);
121 memory_region_add_subregion(sys_mem,
122 memmap[IBEX_DEV_ROM].base, &s->rom);
123
124 /* Flash memory */
125 memory_region_init_rom(&s->flash_mem, OBJECT(dev_soc), "riscv.lowrisc.ibex.flash",
126 memmap[IBEX_DEV_FLASH].size, &error_fatal);
127 memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_FLASH].base,
128 &s->flash_mem);
129
130 /* PLIC */
131 if (!sysbus_realize(SYS_BUS_DEVICE(&s->plic), errp)) {
132 return;
133 }
134 sysbus_mmio_map(SYS_BUS_DEVICE(&s->plic), 0, memmap[IBEX_DEV_PLIC].base);
135
136 /* UART */
137 qdev_prop_set_chr(DEVICE(&(s->uart)), "chardev", serial_hd(0));
138 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart), errp)) {
139 return;
140 }
141 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart), 0, memmap[IBEX_DEV_UART].base);
142 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
143 0, qdev_get_gpio_in(DEVICE(&s->plic),
144 IBEX_UART_TX_WATERMARK_IRQ));
145 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
146 1, qdev_get_gpio_in(DEVICE(&s->plic),
147 IBEX_UART_RX_WATERMARK_IRQ));
148 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
149 2, qdev_get_gpio_in(DEVICE(&s->plic),
150 IBEX_UART_TX_EMPTY_IRQ));
151 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
152 3, qdev_get_gpio_in(DEVICE(&s->plic),
153 IBEX_UART_RX_OVERFLOW_IRQ));
154
155 create_unimplemented_device("riscv.lowrisc.ibex.gpio",
156 memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size);
157 create_unimplemented_device("riscv.lowrisc.ibex.spi",
158 memmap[IBEX_DEV_SPI].base, memmap[IBEX_DEV_SPI].size);
159 create_unimplemented_device("riscv.lowrisc.ibex.flash_ctrl",
160 memmap[IBEX_DEV_FLASH_CTRL].base, memmap[IBEX_DEV_FLASH_CTRL].size);
161 create_unimplemented_device("riscv.lowrisc.ibex.rv_timer",
162 memmap[IBEX_DEV_RV_TIMER].base, memmap[IBEX_DEV_RV_TIMER].size);
163 create_unimplemented_device("riscv.lowrisc.ibex.pwrmgr",
164 memmap[IBEX_DEV_PWRMGR].base, memmap[IBEX_DEV_PWRMGR].size);
165 create_unimplemented_device("riscv.lowrisc.ibex.rstmgr",
166 memmap[IBEX_DEV_RSTMGR].base, memmap[IBEX_DEV_RSTMGR].size);
167 create_unimplemented_device("riscv.lowrisc.ibex.clkmgr",
168 memmap[IBEX_DEV_CLKMGR].base, memmap[IBEX_DEV_CLKMGR].size);
169 create_unimplemented_device("riscv.lowrisc.ibex.aes",
170 memmap[IBEX_DEV_AES].base, memmap[IBEX_DEV_AES].size);
171 create_unimplemented_device("riscv.lowrisc.ibex.hmac",
172 memmap[IBEX_DEV_HMAC].base, memmap[IBEX_DEV_HMAC].size);
173 create_unimplemented_device("riscv.lowrisc.ibex.pinmux",
174 memmap[IBEX_DEV_PINMUX].base, memmap[IBEX_DEV_PINMUX].size);
175 create_unimplemented_device("riscv.lowrisc.ibex.alert_handler",
176 memmap[IBEX_DEV_ALERT_HANDLER].base, memmap[IBEX_DEV_ALERT_HANDLER].size);
177 create_unimplemented_device("riscv.lowrisc.ibex.nmi_gen",
178 memmap[IBEX_DEV_NMI_GEN].base, memmap[IBEX_DEV_NMI_GEN].size);
179 create_unimplemented_device("riscv.lowrisc.ibex.usbdev",
180 memmap[IBEX_DEV_USBDEV].base, memmap[IBEX_DEV_USBDEV].size);
181 create_unimplemented_device("riscv.lowrisc.ibex.padctrl",
182 memmap[IBEX_DEV_PADCTRL].base, memmap[IBEX_DEV_PADCTRL].size);
183 }
184
185 static void lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data)
186 {
187 DeviceClass *dc = DEVICE_CLASS(oc);
188
189 dc->realize = lowrisc_ibex_soc_realize;
190 /* Reason: Uses serial_hds in realize function, thus can't be used twice */
191 dc->user_creatable = false;
192 }
193
194 static const TypeInfo lowrisc_ibex_soc_type_info = {
195 .name = TYPE_RISCV_IBEX_SOC,
196 .parent = TYPE_DEVICE,
197 .instance_size = sizeof(LowRISCIbexSoCState),
198 .instance_init = lowrisc_ibex_soc_init,
199 .class_init = lowrisc_ibex_soc_class_init,
200 };
201
202 static void lowrisc_ibex_soc_register_types(void)
203 {
204 type_register_static(&lowrisc_ibex_soc_type_info);
205 }
206
207 type_init(lowrisc_ibex_soc_register_types)