Merge remote-tracking branch 'remotes/philmd-gitlab/tags/renesas-20201027' into staging
[qemu.git] / hw / riscv / riscv_hart.c
1 /*
2 * QEMU RISCV Hart Array
3 *
4 * Copyright (c) 2017 SiFive, Inc.
5 *
6 * Holds the state of a homogeneous array of RISC-V harts
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "qapi/error.h"
23 #include "qemu/module.h"
24 #include "sysemu/reset.h"
25 #include "hw/sysbus.h"
26 #include "target/riscv/cpu.h"
27 #include "hw/qdev-properties.h"
28 #include "hw/riscv/riscv_hart.h"
29
30 static Property riscv_harts_props[] = {
31 DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1),
32 DEFINE_PROP_UINT32("hartid-base", RISCVHartArrayState, hartid_base, 0),
33 DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type),
34 DEFINE_PROP_UINT64("resetvec", RISCVHartArrayState, resetvec,
35 DEFAULT_RSTVEC),
36 DEFINE_PROP_END_OF_LIST(),
37 };
38
39 static void riscv_harts_cpu_reset(void *opaque)
40 {
41 RISCVCPU *cpu = opaque;
42 cpu_reset(CPU(cpu));
43 }
44
45 static bool riscv_hart_realize(RISCVHartArrayState *s, int idx,
46 char *cpu_type, Error **errp)
47 {
48 object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx], cpu_type);
49 qdev_prop_set_uint64(DEVICE(&s->harts[idx]), "resetvec", s->resetvec);
50 s->harts[idx].env.mhartid = s->hartid_base + idx;
51 qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]);
52 return qdev_realize(DEVICE(&s->harts[idx]), NULL, errp);
53 }
54
55 static void riscv_harts_realize(DeviceState *dev, Error **errp)
56 {
57 RISCVHartArrayState *s = RISCV_HART_ARRAY(dev);
58 int n;
59
60 s->harts = g_new0(RISCVCPU, s->num_harts);
61
62 for (n = 0; n < s->num_harts; n++) {
63 if (!riscv_hart_realize(s, n, s->cpu_type, errp)) {
64 return;
65 }
66 }
67 }
68
69 static void riscv_harts_class_init(ObjectClass *klass, void *data)
70 {
71 DeviceClass *dc = DEVICE_CLASS(klass);
72
73 device_class_set_props(dc, riscv_harts_props);
74 dc->realize = riscv_harts_realize;
75 }
76
77 static const TypeInfo riscv_harts_info = {
78 .name = TYPE_RISCV_HART_ARRAY,
79 .parent = TYPE_SYS_BUS_DEVICE,
80 .instance_size = sizeof(RISCVHartArrayState),
81 .class_init = riscv_harts_class_init,
82 };
83
84 static void riscv_harts_register_types(void)
85 {
86 type_register_static(&riscv_harts_info);
87 }
88
89 type_init(riscv_harts_register_types)