meson: convert qapi-specific to meson
[qemu.git] / hw / riscv / sifive_e.c
1 /*
2 * QEMU RISC-V Board Compatible with SiFive Freedom E SDK
3 *
4 * Copyright (c) 2017 SiFive, Inc.
5 *
6 * Provides a board compatible with the SiFive Freedom E SDK:
7 *
8 * 0) UART
9 * 1) CLINT (Core Level Interruptor)
10 * 2) PLIC (Platform Level Interrupt Controller)
11 * 3) PRCI (Power, Reset, Clock, Interrupt)
12 * 4) Registers emulated as RAM: AON, GPIO, QSPI, PWM
13 * 5) Flash memory emulated as RAM
14 *
15 * The Mask ROM reset vector jumps to the flash payload at 0x2040_0000.
16 * The OTP ROM and Flash boot code will be emulated in a future version.
17 *
18 * This program is free software; you can redistribute it and/or modify it
19 * under the terms and conditions of the GNU General Public License,
20 * version 2 or later, as published by the Free Software Foundation.
21 *
22 * This program is distributed in the hope it will be useful, but WITHOUT
23 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
24 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
25 * more details.
26 *
27 * You should have received a copy of the GNU General Public License along with
28 * this program. If not, see <http://www.gnu.org/licenses/>.
29 */
30
31 #include "qemu/osdep.h"
32 #include "qemu/log.h"
33 #include "qemu/error-report.h"
34 #include "qapi/error.h"
35 #include "hw/boards.h"
36 #include "hw/loader.h"
37 #include "hw/sysbus.h"
38 #include "hw/char/serial.h"
39 #include "hw/misc/unimp.h"
40 #include "target/riscv/cpu.h"
41 #include "hw/riscv/riscv_hart.h"
42 #include "hw/riscv/sifive_plic.h"
43 #include "hw/riscv/sifive_clint.h"
44 #include "hw/riscv/sifive_uart.h"
45 #include "hw/riscv/sifive_e.h"
46 #include "hw/riscv/sifive_e_prci.h"
47 #include "hw/riscv/boot.h"
48 #include "chardev/char.h"
49 #include "sysemu/arch_init.h"
50 #include "sysemu/sysemu.h"
51 #include "exec/address-spaces.h"
52
53 static const struct MemmapEntry {
54 hwaddr base;
55 hwaddr size;
56 } sifive_e_memmap[] = {
57 [SIFIVE_E_DEBUG] = { 0x0, 0x1000 },
58 [SIFIVE_E_MROM] = { 0x1000, 0x2000 },
59 [SIFIVE_E_OTP] = { 0x20000, 0x2000 },
60 [SIFIVE_E_CLINT] = { 0x2000000, 0x10000 },
61 [SIFIVE_E_PLIC] = { 0xc000000, 0x4000000 },
62 [SIFIVE_E_AON] = { 0x10000000, 0x8000 },
63 [SIFIVE_E_PRCI] = { 0x10008000, 0x8000 },
64 [SIFIVE_E_OTP_CTRL] = { 0x10010000, 0x1000 },
65 [SIFIVE_E_GPIO0] = { 0x10012000, 0x1000 },
66 [SIFIVE_E_UART0] = { 0x10013000, 0x1000 },
67 [SIFIVE_E_QSPI0] = { 0x10014000, 0x1000 },
68 [SIFIVE_E_PWM0] = { 0x10015000, 0x1000 },
69 [SIFIVE_E_UART1] = { 0x10023000, 0x1000 },
70 [SIFIVE_E_QSPI1] = { 0x10024000, 0x1000 },
71 [SIFIVE_E_PWM1] = { 0x10025000, 0x1000 },
72 [SIFIVE_E_QSPI2] = { 0x10034000, 0x1000 },
73 [SIFIVE_E_PWM2] = { 0x10035000, 0x1000 },
74 [SIFIVE_E_XIP] = { 0x20000000, 0x20000000 },
75 [SIFIVE_E_DTIM] = { 0x80000000, 0x4000 }
76 };
77
78 static void sifive_e_machine_init(MachineState *machine)
79 {
80 const struct MemmapEntry *memmap = sifive_e_memmap;
81
82 SiFiveEState *s = RISCV_E_MACHINE(machine);
83 MemoryRegion *sys_mem = get_system_memory();
84 MemoryRegion *main_mem = g_new(MemoryRegion, 1);
85 int i;
86
87 /* Initialize SoC */
88 object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_E_SOC);
89 qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
90
91 /* Data Tightly Integrated Memory */
92 memory_region_init_ram(main_mem, NULL, "riscv.sifive.e.ram",
93 memmap[SIFIVE_E_DTIM].size, &error_fatal);
94 memory_region_add_subregion(sys_mem,
95 memmap[SIFIVE_E_DTIM].base, main_mem);
96
97 /* Mask ROM reset vector */
98 uint32_t reset_vec[4];
99
100 if (s->revb) {
101 reset_vec[1] = 0x200102b7; /* 0x1004: lui t0,0x20010 */
102 } else {
103 reset_vec[1] = 0x204002b7; /* 0x1004: lui t0,0x20400 */
104 }
105 reset_vec[2] = 0x00028067; /* 0x1008: jr t0 */
106
107 reset_vec[0] = reset_vec[3] = 0;
108
109 /* copy in the reset vector in little_endian byte order */
110 for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
111 reset_vec[i] = cpu_to_le32(reset_vec[i]);
112 }
113 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
114 memmap[SIFIVE_E_MROM].base, &address_space_memory);
115
116 if (machine->kernel_filename) {
117 riscv_load_kernel(machine->kernel_filename, NULL);
118 }
119 }
120
121 static bool sifive_e_machine_get_revb(Object *obj, Error **errp)
122 {
123 SiFiveEState *s = RISCV_E_MACHINE(obj);
124
125 return s->revb;
126 }
127
128 static void sifive_e_machine_set_revb(Object *obj, bool value, Error **errp)
129 {
130 SiFiveEState *s = RISCV_E_MACHINE(obj);
131
132 s->revb = value;
133 }
134
135 static void sifive_e_machine_instance_init(Object *obj)
136 {
137 SiFiveEState *s = RISCV_E_MACHINE(obj);
138
139 s->revb = false;
140 object_property_add_bool(obj, "revb", sifive_e_machine_get_revb,
141 sifive_e_machine_set_revb);
142 object_property_set_description(obj, "revb",
143 "Set on to tell QEMU that it should model "
144 "the revB HiFive1 board");
145 }
146
147 static void sifive_e_machine_class_init(ObjectClass *oc, void *data)
148 {
149 MachineClass *mc = MACHINE_CLASS(oc);
150
151 mc->desc = "RISC-V Board compatible with SiFive E SDK";
152 mc->init = sifive_e_machine_init;
153 mc->max_cpus = 1;
154 mc->default_cpu_type = SIFIVE_E_CPU;
155 }
156
157 static const TypeInfo sifive_e_machine_typeinfo = {
158 .name = MACHINE_TYPE_NAME("sifive_e"),
159 .parent = TYPE_MACHINE,
160 .class_init = sifive_e_machine_class_init,
161 .instance_init = sifive_e_machine_instance_init,
162 .instance_size = sizeof(SiFiveEState),
163 };
164
165 static void sifive_e_machine_init_register_types(void)
166 {
167 type_register_static(&sifive_e_machine_typeinfo);
168 }
169
170 type_init(sifive_e_machine_init_register_types)
171
172 static void sifive_e_soc_init(Object *obj)
173 {
174 MachineState *ms = MACHINE(qdev_get_machine());
175 SiFiveESoCState *s = RISCV_E_SOC(obj);
176
177 object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
178 object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
179 &error_abort);
180 object_initialize_child(obj, "riscv.sifive.e.gpio0", &s->gpio,
181 TYPE_SIFIVE_GPIO);
182 }
183
184 static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
185 {
186 MachineState *ms = MACHINE(qdev_get_machine());
187 const struct MemmapEntry *memmap = sifive_e_memmap;
188 SiFiveESoCState *s = RISCV_E_SOC(dev);
189 MemoryRegion *sys_mem = get_system_memory();
190
191 object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type,
192 &error_abort);
193 sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
194
195 /* Mask ROM */
196 memory_region_init_rom(&s->mask_rom, OBJECT(dev), "riscv.sifive.e.mrom",
197 memmap[SIFIVE_E_MROM].size, &error_fatal);
198 memory_region_add_subregion(sys_mem,
199 memmap[SIFIVE_E_MROM].base, &s->mask_rom);
200
201 /* MMIO */
202 s->plic = sifive_plic_create(memmap[SIFIVE_E_PLIC].base,
203 (char *)SIFIVE_E_PLIC_HART_CONFIG,
204 SIFIVE_E_PLIC_NUM_SOURCES,
205 SIFIVE_E_PLIC_NUM_PRIORITIES,
206 SIFIVE_E_PLIC_PRIORITY_BASE,
207 SIFIVE_E_PLIC_PENDING_BASE,
208 SIFIVE_E_PLIC_ENABLE_BASE,
209 SIFIVE_E_PLIC_ENABLE_STRIDE,
210 SIFIVE_E_PLIC_CONTEXT_BASE,
211 SIFIVE_E_PLIC_CONTEXT_STRIDE,
212 memmap[SIFIVE_E_PLIC].size);
213 sifive_clint_create(memmap[SIFIVE_E_CLINT].base,
214 memmap[SIFIVE_E_CLINT].size, ms->smp.cpus,
215 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
216 create_unimplemented_device("riscv.sifive.e.aon",
217 memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size);
218 sifive_e_prci_create(memmap[SIFIVE_E_PRCI].base);
219
220 /* GPIO */
221
222 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
223 return;
224 }
225
226 /* Map GPIO registers */
227 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_E_GPIO0].base);
228
229 /* Pass all GPIOs to the SOC layer so they are available to the board */
230 qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL);
231
232 /* Connect GPIO interrupts to the PLIC */
233 for (int i = 0; i < 32; i++) {
234 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i,
235 qdev_get_gpio_in(DEVICE(s->plic),
236 SIFIVE_E_GPIO0_IRQ0 + i));
237 }
238
239 sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART0].base,
240 serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART0_IRQ));
241 create_unimplemented_device("riscv.sifive.e.qspi0",
242 memmap[SIFIVE_E_QSPI0].base, memmap[SIFIVE_E_QSPI0].size);
243 create_unimplemented_device("riscv.sifive.e.pwm0",
244 memmap[SIFIVE_E_PWM0].base, memmap[SIFIVE_E_PWM0].size);
245 sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART1].base,
246 serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART1_IRQ));
247 create_unimplemented_device("riscv.sifive.e.qspi1",
248 memmap[SIFIVE_E_QSPI1].base, memmap[SIFIVE_E_QSPI1].size);
249 create_unimplemented_device("riscv.sifive.e.pwm1",
250 memmap[SIFIVE_E_PWM1].base, memmap[SIFIVE_E_PWM1].size);
251 create_unimplemented_device("riscv.sifive.e.qspi2",
252 memmap[SIFIVE_E_QSPI2].base, memmap[SIFIVE_E_QSPI2].size);
253 create_unimplemented_device("riscv.sifive.e.pwm2",
254 memmap[SIFIVE_E_PWM2].base, memmap[SIFIVE_E_PWM2].size);
255
256 /* Flash memory */
257 memory_region_init_rom(&s->xip_mem, OBJECT(dev), "riscv.sifive.e.xip",
258 memmap[SIFIVE_E_XIP].size, &error_fatal);
259 memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_XIP].base,
260 &s->xip_mem);
261 }
262
263 static void sifive_e_soc_class_init(ObjectClass *oc, void *data)
264 {
265 DeviceClass *dc = DEVICE_CLASS(oc);
266
267 dc->realize = sifive_e_soc_realize;
268 /* Reason: Uses serial_hds in realize function, thus can't be used twice */
269 dc->user_creatable = false;
270 }
271
272 static const TypeInfo sifive_e_soc_type_info = {
273 .name = TYPE_RISCV_E_SOC,
274 .parent = TYPE_DEVICE,
275 .instance_size = sizeof(SiFiveESoCState),
276 .instance_init = sifive_e_soc_init,
277 .class_init = sifive_e_soc_class_init,
278 };
279
280 static void sifive_e_soc_register_types(void)
281 {
282 type_register_static(&sifive_e_soc_type_info);
283 }
284
285 type_init(sifive_e_soc_register_types)