meson: convert qapi-specific to meson
[qemu.git] / hw / riscv / sifive_e_prci.c
1 /*
2 * QEMU SiFive E PRCI (Power, Reset, Clock, Interrupt)
3 *
4 * Copyright (c) 2017 SiFive, Inc.
5 *
6 * Simple model of the PRCI to emulate register reads made by the SDK BSP
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "hw/sysbus.h"
23 #include "qapi/error.h"
24 #include "qemu/log.h"
25 #include "qemu/module.h"
26 #include "hw/hw.h"
27 #include "hw/riscv/sifive_e_prci.h"
28
29 static uint64_t sifive_e_prci_read(void *opaque, hwaddr addr, unsigned int size)
30 {
31 SiFiveEPRCIState *s = opaque;
32 switch (addr) {
33 case SIFIVE_E_PRCI_HFROSCCFG:
34 return s->hfrosccfg;
35 case SIFIVE_E_PRCI_HFXOSCCFG:
36 return s->hfxosccfg;
37 case SIFIVE_E_PRCI_PLLCFG:
38 return s->pllcfg;
39 case SIFIVE_E_PRCI_PLLOUTDIV:
40 return s->plloutdiv;
41 }
42 qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=0x%x\n",
43 __func__, (int)addr);
44 return 0;
45 }
46
47 static void sifive_e_prci_write(void *opaque, hwaddr addr,
48 uint64_t val64, unsigned int size)
49 {
50 SiFiveEPRCIState *s = opaque;
51 switch (addr) {
52 case SIFIVE_E_PRCI_HFROSCCFG:
53 s->hfrosccfg = (uint32_t) val64;
54 /* OSC stays ready */
55 s->hfrosccfg |= SIFIVE_E_PRCI_HFROSCCFG_RDY;
56 break;
57 case SIFIVE_E_PRCI_HFXOSCCFG:
58 s->hfxosccfg = (uint32_t) val64;
59 /* OSC stays ready */
60 s->hfxosccfg |= SIFIVE_E_PRCI_HFXOSCCFG_RDY;
61 break;
62 case SIFIVE_E_PRCI_PLLCFG:
63 s->pllcfg = (uint32_t) val64;
64 /* PLL stays locked */
65 s->pllcfg |= SIFIVE_E_PRCI_PLLCFG_LOCK;
66 break;
67 case SIFIVE_E_PRCI_PLLOUTDIV:
68 s->plloutdiv = (uint32_t) val64;
69 break;
70 default:
71 qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%x v=0x%x\n",
72 __func__, (int)addr, (int)val64);
73 }
74 }
75
76 static const MemoryRegionOps sifive_e_prci_ops = {
77 .read = sifive_e_prci_read,
78 .write = sifive_e_prci_write,
79 .endianness = DEVICE_NATIVE_ENDIAN,
80 .valid = {
81 .min_access_size = 4,
82 .max_access_size = 4
83 }
84 };
85
86 static void sifive_e_prci_init(Object *obj)
87 {
88 SiFiveEPRCIState *s = SIFIVE_E_PRCI(obj);
89
90 memory_region_init_io(&s->mmio, obj, &sifive_e_prci_ops, s,
91 TYPE_SIFIVE_E_PRCI, SIFIVE_E_PRCI_REG_SIZE);
92 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
93
94 s->hfrosccfg = (SIFIVE_E_PRCI_HFROSCCFG_RDY | SIFIVE_E_PRCI_HFROSCCFG_EN);
95 s->hfxosccfg = (SIFIVE_E_PRCI_HFXOSCCFG_RDY | SIFIVE_E_PRCI_HFXOSCCFG_EN);
96 s->pllcfg = (SIFIVE_E_PRCI_PLLCFG_REFSEL | SIFIVE_E_PRCI_PLLCFG_BYPASS |
97 SIFIVE_E_PRCI_PLLCFG_LOCK);
98 s->plloutdiv = SIFIVE_E_PRCI_PLLOUTDIV_DIV1;
99 }
100
101 static const TypeInfo sifive_e_prci_info = {
102 .name = TYPE_SIFIVE_E_PRCI,
103 .parent = TYPE_SYS_BUS_DEVICE,
104 .instance_size = sizeof(SiFiveEPRCIState),
105 .instance_init = sifive_e_prci_init,
106 };
107
108 static void sifive_e_prci_register_types(void)
109 {
110 type_register_static(&sifive_e_prci_info);
111 }
112
113 type_init(sifive_e_prci_register_types)
114
115
116 /*
117 * Create PRCI device.
118 */
119 DeviceState *sifive_e_prci_create(hwaddr addr)
120 {
121 DeviceState *dev = qdev_new(TYPE_SIFIVE_E_PRCI);
122 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
123 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
124 return dev;
125 }