4299bdf480285a8262fb067d49c50c5476c59638
[qemu.git] / hw / riscv / sifive_u.c
1 /*
2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017 SiFive, Inc.
6 * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
7 *
8 * Provides a board compatible with the SiFive Freedom U SDK:
9 *
10 * 0) UART
11 * 1) CLINT (Core Level Interruptor)
12 * 2) PLIC (Platform Level Interrupt Controller)
13 * 3) PRCI (Power, Reset, Clock, Interrupt)
14 * 4) OTP (One-Time Programmable) memory with stored serial number
15 * 5) GEM (Gigabit Ethernet Controller) and management block
16 *
17 * This board currently generates devicetree dynamically that indicates at least
18 * two harts and up to five harts.
19 *
20 * This program is free software; you can redistribute it and/or modify it
21 * under the terms and conditions of the GNU General Public License,
22 * version 2 or later, as published by the Free Software Foundation.
23 *
24 * This program is distributed in the hope it will be useful, but WITHOUT
25 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
26 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
27 * more details.
28 *
29 * You should have received a copy of the GNU General Public License along with
30 * this program. If not, see <http://www.gnu.org/licenses/>.
31 */
32
33 #include "qemu/osdep.h"
34 #include "qemu/log.h"
35 #include "qemu/error-report.h"
36 #include "qapi/error.h"
37 #include "qapi/visitor.h"
38 #include "hw/boards.h"
39 #include "hw/loader.h"
40 #include "hw/sysbus.h"
41 #include "hw/char/serial.h"
42 #include "hw/cpu/cluster.h"
43 #include "hw/misc/unimp.h"
44 #include "target/riscv/cpu.h"
45 #include "hw/riscv/riscv_hart.h"
46 #include "hw/riscv/sifive_plic.h"
47 #include "hw/riscv/sifive_clint.h"
48 #include "hw/riscv/sifive_uart.h"
49 #include "hw/riscv/sifive_u.h"
50 #include "hw/riscv/boot.h"
51 #include "chardev/char.h"
52 #include "net/eth.h"
53 #include "sysemu/arch_init.h"
54 #include "sysemu/device_tree.h"
55 #include "sysemu/sysemu.h"
56 #include "exec/address-spaces.h"
57
58 #include <libfdt.h>
59
60 #if defined(TARGET_RISCV32)
61 # define BIOS_FILENAME "opensbi-riscv32-sifive_u-fw_jump.bin"
62 #else
63 # define BIOS_FILENAME "opensbi-riscv64-sifive_u-fw_jump.bin"
64 #endif
65
66 static const struct MemmapEntry {
67 hwaddr base;
68 hwaddr size;
69 } sifive_u_memmap[] = {
70 [SIFIVE_U_DEBUG] = { 0x0, 0x100 },
71 [SIFIVE_U_MROM] = { 0x1000, 0x11000 },
72 [SIFIVE_U_CLINT] = { 0x2000000, 0x10000 },
73 [SIFIVE_U_L2LIM] = { 0x8000000, 0x2000000 },
74 [SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 },
75 [SIFIVE_U_PRCI] = { 0x10000000, 0x1000 },
76 [SIFIVE_U_UART0] = { 0x10010000, 0x1000 },
77 [SIFIVE_U_UART1] = { 0x10011000, 0x1000 },
78 [SIFIVE_U_OTP] = { 0x10070000, 0x1000 },
79 [SIFIVE_U_FLASH0] = { 0x20000000, 0x10000000 },
80 [SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
81 [SIFIVE_U_GEM] = { 0x10090000, 0x2000 },
82 [SIFIVE_U_GEM_MGMT] = { 0x100a0000, 0x1000 },
83 };
84
85 #define OTP_SERIAL 1
86 #define GEM_REVISION 0x10070109
87
88 static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
89 uint64_t mem_size, const char *cmdline)
90 {
91 MachineState *ms = MACHINE(qdev_get_machine());
92 void *fdt;
93 int cpu;
94 uint32_t *cells;
95 char *nodename;
96 char ethclk_names[] = "pclk\0hclk";
97 uint32_t plic_phandle, prci_phandle, phandle = 1;
98 uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle;
99
100 fdt = s->fdt = create_device_tree(&s->fdt_size);
101 if (!fdt) {
102 error_report("create_device_tree() failed");
103 exit(1);
104 }
105
106 qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A00");
107 qemu_fdt_setprop_string(fdt, "/", "compatible",
108 "sifive,hifive-unleashed-a00");
109 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
110 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
111
112 qemu_fdt_add_subnode(fdt, "/soc");
113 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
114 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
115 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
116 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
117
118 hfclk_phandle = phandle++;
119 nodename = g_strdup_printf("/hfclk");
120 qemu_fdt_add_subnode(fdt, nodename);
121 qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle);
122 qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk");
123 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
124 SIFIVE_U_HFCLK_FREQ);
125 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
126 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
127 g_free(nodename);
128
129 rtcclk_phandle = phandle++;
130 nodename = g_strdup_printf("/rtcclk");
131 qemu_fdt_add_subnode(fdt, nodename);
132 qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle);
133 qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk");
134 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
135 SIFIVE_U_RTCCLK_FREQ);
136 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
137 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
138 g_free(nodename);
139
140 nodename = g_strdup_printf("/memory@%lx",
141 (long)memmap[SIFIVE_U_DRAM].base);
142 qemu_fdt_add_subnode(fdt, nodename);
143 qemu_fdt_setprop_cells(fdt, nodename, "reg",
144 memmap[SIFIVE_U_DRAM].base >> 32, memmap[SIFIVE_U_DRAM].base,
145 mem_size >> 32, mem_size);
146 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
147 g_free(nodename);
148
149 qemu_fdt_add_subnode(fdt, "/cpus");
150 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
151 SIFIVE_CLINT_TIMEBASE_FREQ);
152 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
153 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
154
155 for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) {
156 int cpu_phandle = phandle++;
157 nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
158 char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
159 char *isa;
160 qemu_fdt_add_subnode(fdt, nodename);
161 /* cpu 0 is the management hart that does not have mmu */
162 if (cpu != 0) {
163 #if defined(TARGET_RISCV32)
164 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32");
165 #else
166 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
167 #endif
168 isa = riscv_isa_string(&s->soc.u_cpus.harts[cpu - 1]);
169 } else {
170 isa = riscv_isa_string(&s->soc.e_cpus.harts[0]);
171 }
172 qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
173 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
174 qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
175 qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
176 qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
177 qemu_fdt_add_subnode(fdt, intc);
178 qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle);
179 qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
180 qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
181 qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
182 g_free(isa);
183 g_free(intc);
184 g_free(nodename);
185 }
186
187 cells = g_new0(uint32_t, ms->smp.cpus * 4);
188 for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
189 nodename =
190 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
191 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
192 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
193 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
194 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
195 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
196 g_free(nodename);
197 }
198 nodename = g_strdup_printf("/soc/clint@%lx",
199 (long)memmap[SIFIVE_U_CLINT].base);
200 qemu_fdt_add_subnode(fdt, nodename);
201 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
202 qemu_fdt_setprop_cells(fdt, nodename, "reg",
203 0x0, memmap[SIFIVE_U_CLINT].base,
204 0x0, memmap[SIFIVE_U_CLINT].size);
205 qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
206 cells, ms->smp.cpus * sizeof(uint32_t) * 4);
207 g_free(cells);
208 g_free(nodename);
209
210 prci_phandle = phandle++;
211 nodename = g_strdup_printf("/soc/clock-controller@%lx",
212 (long)memmap[SIFIVE_U_PRCI].base);
213 qemu_fdt_add_subnode(fdt, nodename);
214 qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle);
215 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1);
216 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
217 hfclk_phandle, rtcclk_phandle);
218 qemu_fdt_setprop_cells(fdt, nodename, "reg",
219 0x0, memmap[SIFIVE_U_PRCI].base,
220 0x0, memmap[SIFIVE_U_PRCI].size);
221 qemu_fdt_setprop_string(fdt, nodename, "compatible",
222 "sifive,fu540-c000-prci");
223 g_free(nodename);
224
225 plic_phandle = phandle++;
226 cells = g_new0(uint32_t, ms->smp.cpus * 4 - 2);
227 for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
228 nodename =
229 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
230 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
231 /* cpu 0 is the management hart that does not have S-mode */
232 if (cpu == 0) {
233 cells[0] = cpu_to_be32(intc_phandle);
234 cells[1] = cpu_to_be32(IRQ_M_EXT);
235 } else {
236 cells[cpu * 4 - 2] = cpu_to_be32(intc_phandle);
237 cells[cpu * 4 - 1] = cpu_to_be32(IRQ_M_EXT);
238 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
239 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_S_EXT);
240 }
241 g_free(nodename);
242 }
243 nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
244 (long)memmap[SIFIVE_U_PLIC].base);
245 qemu_fdt_add_subnode(fdt, nodename);
246 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
247 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
248 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
249 qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
250 cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t));
251 qemu_fdt_setprop_cells(fdt, nodename, "reg",
252 0x0, memmap[SIFIVE_U_PLIC].base,
253 0x0, memmap[SIFIVE_U_PLIC].size);
254 qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
255 qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
256 plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
257 g_free(cells);
258 g_free(nodename);
259
260 phy_phandle = phandle++;
261 nodename = g_strdup_printf("/soc/ethernet@%lx",
262 (long)memmap[SIFIVE_U_GEM].base);
263 qemu_fdt_add_subnode(fdt, nodename);
264 qemu_fdt_setprop_string(fdt, nodename, "compatible",
265 "sifive,fu540-c000-gem");
266 qemu_fdt_setprop_cells(fdt, nodename, "reg",
267 0x0, memmap[SIFIVE_U_GEM].base,
268 0x0, memmap[SIFIVE_U_GEM].size,
269 0x0, memmap[SIFIVE_U_GEM_MGMT].base,
270 0x0, memmap[SIFIVE_U_GEM_MGMT].size);
271 qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
272 qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii");
273 qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle);
274 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
275 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ);
276 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
277 prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL);
278 qemu_fdt_setprop(fdt, nodename, "clock-names", ethclk_names,
279 sizeof(ethclk_names));
280 qemu_fdt_setprop(fdt, nodename, "local-mac-address",
281 s->soc.gem.conf.macaddr.a, ETH_ALEN);
282 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
283 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0);
284
285 qemu_fdt_add_subnode(fdt, "/aliases");
286 qemu_fdt_setprop_string(fdt, "/aliases", "ethernet0", nodename);
287
288 g_free(nodename);
289
290 nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0",
291 (long)memmap[SIFIVE_U_GEM].base);
292 qemu_fdt_add_subnode(fdt, nodename);
293 qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle);
294 qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);
295 g_free(nodename);
296
297 nodename = g_strdup_printf("/soc/serial@%lx",
298 (long)memmap[SIFIVE_U_UART0].base);
299 qemu_fdt_add_subnode(fdt, nodename);
300 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
301 qemu_fdt_setprop_cells(fdt, nodename, "reg",
302 0x0, memmap[SIFIVE_U_UART0].base,
303 0x0, memmap[SIFIVE_U_UART0].size);
304 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
305 prci_phandle, PRCI_CLK_TLCLK);
306 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
307 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ);
308
309 qemu_fdt_add_subnode(fdt, "/chosen");
310 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
311 if (cmdline) {
312 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
313 }
314
315 qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename);
316
317 g_free(nodename);
318 }
319
320 static void sifive_u_machine_init(MachineState *machine)
321 {
322 const struct MemmapEntry *memmap = sifive_u_memmap;
323 SiFiveUState *s = RISCV_U_MACHINE(machine);
324 MemoryRegion *system_memory = get_system_memory();
325 MemoryRegion *main_mem = g_new(MemoryRegion, 1);
326 MemoryRegion *flash0 = g_new(MemoryRegion, 1);
327 target_ulong start_addr = memmap[SIFIVE_U_DRAM].base;
328 int i;
329
330 /* Initialize SoC */
331 object_initialize_child(OBJECT(machine), "soc", &s->soc,
332 sizeof(s->soc), TYPE_RISCV_U_SOC,
333 &error_abort, NULL);
334 object_property_set_uint(OBJECT(&s->soc), s->serial, "serial",
335 &error_abort);
336 object_property_set_bool(OBJECT(&s->soc), true, "realized",
337 &error_abort);
338
339 /* register RAM */
340 memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram",
341 machine->ram_size, &error_fatal);
342 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base,
343 main_mem);
344
345 /* register QSPI0 Flash */
346 memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0",
347 memmap[SIFIVE_U_FLASH0].size, &error_fatal);
348 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_FLASH0].base,
349 flash0);
350
351 /* create device tree */
352 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
353
354 riscv_find_and_load_firmware(machine, BIOS_FILENAME,
355 memmap[SIFIVE_U_DRAM].base, NULL);
356
357 if (machine->kernel_filename) {
358 uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename,
359 NULL);
360
361 if (machine->initrd_filename) {
362 hwaddr start;
363 hwaddr end = riscv_load_initrd(machine->initrd_filename,
364 machine->ram_size, kernel_entry,
365 &start);
366 qemu_fdt_setprop_cell(s->fdt, "/chosen",
367 "linux,initrd-start", start);
368 qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
369 end);
370 }
371 }
372
373 if (s->start_in_flash) {
374 start_addr = memmap[SIFIVE_U_FLASH0].base;
375 }
376
377 /* reset vector */
378 uint32_t reset_vec[8] = {
379 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
380 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */
381 0xf1402573, /* csrr a0, mhartid */
382 #if defined(TARGET_RISCV32)
383 0x0182a283, /* lw t0, 24(t0) */
384 #elif defined(TARGET_RISCV64)
385 0x0182b283, /* ld t0, 24(t0) */
386 #endif
387 0x00028067, /* jr t0 */
388 0x00000000,
389 start_addr, /* start: .dword */
390 0x00000000,
391 /* dtb: */
392 };
393
394 /* copy in the reset vector in little_endian byte order */
395 for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
396 reset_vec[i] = cpu_to_le32(reset_vec[i]);
397 }
398 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
399 memmap[SIFIVE_U_MROM].base, &address_space_memory);
400
401 /* copy in the device tree */
402 if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) >
403 memmap[SIFIVE_U_MROM].size - sizeof(reset_vec)) {
404 error_report("not enough space to store device-tree");
405 exit(1);
406 }
407 qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
408 rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
409 memmap[SIFIVE_U_MROM].base + sizeof(reset_vec),
410 &address_space_memory);
411 }
412
413 static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp)
414 {
415 SiFiveUState *s = RISCV_U_MACHINE(obj);
416
417 return s->start_in_flash;
418 }
419
420 static void sifive_u_machine_set_start_in_flash(Object *obj, bool value, Error **errp)
421 {
422 SiFiveUState *s = RISCV_U_MACHINE(obj);
423
424 s->start_in_flash = value;
425 }
426
427 static void sifive_u_machine_get_serial(Object *obj, Visitor *v, const char *name,
428 void *opaque, Error **errp)
429 {
430 visit_type_uint32(v, name, (uint32_t *)opaque, errp);
431 }
432
433 static void sifive_u_machine_set_serial(Object *obj, Visitor *v, const char *name,
434 void *opaque, Error **errp)
435 {
436 visit_type_uint32(v, name, (uint32_t *)opaque, errp);
437 }
438
439 static void sifive_u_machine_instance_init(Object *obj)
440 {
441 SiFiveUState *s = RISCV_U_MACHINE(obj);
442
443 s->start_in_flash = false;
444 object_property_add_bool(obj, "start-in-flash",
445 sifive_u_machine_get_start_in_flash,
446 sifive_u_machine_set_start_in_flash);
447 object_property_set_description(obj, "start-in-flash",
448 "Set on to tell QEMU's ROM to jump to "
449 "flash. Otherwise QEMU will jump to DRAM");
450
451 s->serial = OTP_SERIAL;
452 object_property_add(obj, "serial", "uint32",
453 sifive_u_machine_get_serial,
454 sifive_u_machine_set_serial, NULL, &s->serial);
455 object_property_set_description(obj, "serial", "Board serial number");
456 }
457
458 static void sifive_u_machine_class_init(ObjectClass *oc, void *data)
459 {
460 MachineClass *mc = MACHINE_CLASS(oc);
461
462 mc->desc = "RISC-V Board compatible with SiFive U SDK";
463 mc->init = sifive_u_machine_init;
464 mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT;
465 mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
466 mc->default_cpus = mc->min_cpus;
467 }
468
469 static const TypeInfo sifive_u_machine_typeinfo = {
470 .name = MACHINE_TYPE_NAME("sifive_u"),
471 .parent = TYPE_MACHINE,
472 .class_init = sifive_u_machine_class_init,
473 .instance_init = sifive_u_machine_instance_init,
474 .instance_size = sizeof(SiFiveUState),
475 };
476
477 static void sifive_u_machine_init_register_types(void)
478 {
479 type_register_static(&sifive_u_machine_typeinfo);
480 }
481
482 type_init(sifive_u_machine_init_register_types)
483
484 static void riscv_sifive_u_soc_init(Object *obj)
485 {
486 MachineState *ms = MACHINE(qdev_get_machine());
487 SiFiveUSoCState *s = RISCV_U_SOC(obj);
488
489 object_initialize_child(obj, "e-cluster", &s->e_cluster,
490 sizeof(s->e_cluster), TYPE_CPU_CLUSTER,
491 &error_abort, NULL);
492 qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0);
493
494 object_initialize_child(OBJECT(&s->e_cluster), "e-cpus",
495 &s->e_cpus, sizeof(s->e_cpus),
496 TYPE_RISCV_HART_ARRAY, &error_abort,
497 NULL);
498 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1);
499 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0);
500 qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU);
501
502 object_initialize_child(obj, "u-cluster", &s->u_cluster,
503 sizeof(s->u_cluster), TYPE_CPU_CLUSTER,
504 &error_abort, NULL);
505 qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1);
506
507 object_initialize_child(OBJECT(&s->u_cluster), "u-cpus",
508 &s->u_cpus, sizeof(s->u_cpus),
509 TYPE_RISCV_HART_ARRAY, &error_abort,
510 NULL);
511 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1);
512 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1);
513 qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", SIFIVE_U_CPU);
514
515 sysbus_init_child_obj(obj, "prci", &s->prci, sizeof(s->prci),
516 TYPE_SIFIVE_U_PRCI);
517 sysbus_init_child_obj(obj, "otp", &s->otp, sizeof(s->otp),
518 TYPE_SIFIVE_U_OTP);
519 sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem),
520 TYPE_CADENCE_GEM);
521 }
522
523 static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
524 {
525 MachineState *ms = MACHINE(qdev_get_machine());
526 SiFiveUSoCState *s = RISCV_U_SOC(dev);
527 const struct MemmapEntry *memmap = sifive_u_memmap;
528 MemoryRegion *system_memory = get_system_memory();
529 MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
530 MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
531 qemu_irq plic_gpios[SIFIVE_U_PLIC_NUM_SOURCES];
532 char *plic_hart_config;
533 size_t plic_hart_config_len;
534 int i;
535 Error *err = NULL;
536 NICInfo *nd = &nd_table[0];
537
538 object_property_set_bool(OBJECT(&s->e_cpus), true, "realized",
539 &error_abort);
540 object_property_set_bool(OBJECT(&s->u_cpus), true, "realized",
541 &error_abort);
542 /*
543 * The cluster must be realized after the RISC-V hart array container,
544 * as the container's CPU object is only created on realize, and the
545 * CPU must exist and have been parented into the cluster before the
546 * cluster is realized.
547 */
548 object_property_set_bool(OBJECT(&s->e_cluster), true, "realized",
549 &error_abort);
550 object_property_set_bool(OBJECT(&s->u_cluster), true, "realized",
551 &error_abort);
552
553 /* boot rom */
554 memory_region_init_rom(mask_rom, OBJECT(dev), "riscv.sifive.u.mrom",
555 memmap[SIFIVE_U_MROM].size, &error_fatal);
556 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base,
557 mask_rom);
558
559 /*
560 * Add L2-LIM at reset size.
561 * This should be reduced in size as the L2 Cache Controller WayEnable
562 * register is incremented. Unfortunately I don't see a nice (or any) way
563 * to handle reducing or blocking out the L2 LIM while still allowing it
564 * be re returned to all enabled after a reset. For the time being, just
565 * leave it enabled all the time. This won't break anything, but will be
566 * too generous to misbehaving guests.
567 */
568 memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim",
569 memmap[SIFIVE_U_L2LIM].size, &error_fatal);
570 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_L2LIM].base,
571 l2lim_mem);
572
573 /* create PLIC hart topology configuration string */
574 plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) *
575 ms->smp.cpus;
576 plic_hart_config = g_malloc0(plic_hart_config_len);
577 for (i = 0; i < ms->smp.cpus; i++) {
578 if (i != 0) {
579 strncat(plic_hart_config, "," SIFIVE_U_PLIC_HART_CONFIG,
580 plic_hart_config_len);
581 } else {
582 strncat(plic_hart_config, "M", plic_hart_config_len);
583 }
584 plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1);
585 }
586
587 /* MMIO */
588 s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base,
589 plic_hart_config,
590 SIFIVE_U_PLIC_NUM_SOURCES,
591 SIFIVE_U_PLIC_NUM_PRIORITIES,
592 SIFIVE_U_PLIC_PRIORITY_BASE,
593 SIFIVE_U_PLIC_PENDING_BASE,
594 SIFIVE_U_PLIC_ENABLE_BASE,
595 SIFIVE_U_PLIC_ENABLE_STRIDE,
596 SIFIVE_U_PLIC_CONTEXT_BASE,
597 SIFIVE_U_PLIC_CONTEXT_STRIDE,
598 memmap[SIFIVE_U_PLIC].size);
599 g_free(plic_hart_config);
600 sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base,
601 serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
602 sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,
603 serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ));
604 sifive_clint_create(memmap[SIFIVE_U_CLINT].base,
605 memmap[SIFIVE_U_CLINT].size, ms->smp.cpus,
606 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
607
608 object_property_set_bool(OBJECT(&s->prci), true, "realized", &err);
609 sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_PRCI].base);
610
611 qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial);
612 object_property_set_bool(OBJECT(&s->otp), true, "realized", &err);
613 sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_OTP].base);
614
615 for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) {
616 plic_gpios[i] = qdev_get_gpio_in(DEVICE(s->plic), i);
617 }
618
619 if (nd->used) {
620 qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
621 qdev_set_nic_properties(DEVICE(&s->gem), nd);
622 }
623 object_property_set_int(OBJECT(&s->gem), GEM_REVISION, "revision",
624 &error_abort);
625 object_property_set_bool(OBJECT(&s->gem), true, "realized", &err);
626 if (err) {
627 error_propagate(errp, err);
628 return;
629 }
630 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base);
631 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0,
632 plic_gpios[SIFIVE_U_GEM_IRQ]);
633
634 create_unimplemented_device("riscv.sifive.u.gem-mgmt",
635 memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size);
636 }
637
638 static Property riscv_sifive_u_soc_props[] = {
639 DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL),
640 DEFINE_PROP_END_OF_LIST()
641 };
642
643 static void riscv_sifive_u_soc_class_init(ObjectClass *oc, void *data)
644 {
645 DeviceClass *dc = DEVICE_CLASS(oc);
646
647 device_class_set_props(dc, riscv_sifive_u_soc_props);
648 dc->realize = riscv_sifive_u_soc_realize;
649 /* Reason: Uses serial_hds in realize function, thus can't be used twice */
650 dc->user_creatable = false;
651 }
652
653 static const TypeInfo riscv_sifive_u_soc_type_info = {
654 .name = TYPE_RISCV_U_SOC,
655 .parent = TYPE_DEVICE,
656 .instance_size = sizeof(SiFiveUSoCState),
657 .instance_init = riscv_sifive_u_soc_init,
658 .class_init = riscv_sifive_u_soc_class_init,
659 };
660
661 static void riscv_sifive_u_soc_register_types(void)
662 {
663 type_register_static(&riscv_sifive_u_soc_type_info);
664 }
665
666 type_init(riscv_sifive_u_soc_register_types)