Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging
[qemu.git] / hw / riscv / spike.c
1 /*
2 * QEMU RISC-V Spike Board
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
6 *
7 * This provides a RISC-V Board with the following devices:
8 *
9 * 0) HTIF Console and Poweroff
10 * 1) CLINT (Timer and IPI)
11 * 2) PLIC (Platform Level Interrupt Controller)
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms and conditions of the GNU General Public License,
15 * version 2 or later, as published by the Free Software Foundation.
16 *
17 * This program is distributed in the hope it will be useful, but WITHOUT
18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
20 * more details.
21 *
22 * You should have received a copy of the GNU General Public License along with
23 * this program. If not, see <http://www.gnu.org/licenses/>.
24 */
25
26 #include "qemu/osdep.h"
27 #include "qemu/error-report.h"
28 #include "qapi/error.h"
29 #include "hw/boards.h"
30 #include "hw/loader.h"
31 #include "hw/sysbus.h"
32 #include "target/riscv/cpu.h"
33 #include "hw/riscv/riscv_hart.h"
34 #include "hw/riscv/spike.h"
35 #include "hw/riscv/boot.h"
36 #include "hw/riscv/numa.h"
37 #include "hw/char/riscv_htif.h"
38 #include "hw/intc/sifive_clint.h"
39 #include "chardev/char.h"
40 #include "sysemu/arch_init.h"
41 #include "sysemu/device_tree.h"
42 #include "sysemu/sysemu.h"
43
44 static const MemMapEntry spike_memmap[] = {
45 [SPIKE_MROM] = { 0x1000, 0xf000 },
46 [SPIKE_CLINT] = { 0x2000000, 0x10000 },
47 [SPIKE_DRAM] = { 0x80000000, 0x0 },
48 };
49
50 static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
51 uint64_t mem_size, const char *cmdline, bool is_32_bit)
52 {
53 void *fdt;
54 uint64_t addr, size;
55 unsigned long clint_addr;
56 int cpu, socket;
57 MachineState *mc = MACHINE(s);
58 uint32_t *clint_cells;
59 uint32_t cpu_phandle, intc_phandle, phandle = 1;
60 char *name, *mem_name, *clint_name, *clust_name;
61 char *core_name, *cpu_name, *intc_name;
62 static const char * const clint_compat[2] = {
63 "sifive,clint0", "riscv,clint0"
64 };
65
66 fdt = s->fdt = create_device_tree(&s->fdt_size);
67 if (!fdt) {
68 error_report("create_device_tree() failed");
69 exit(1);
70 }
71
72 qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu");
73 qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev");
74 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
75 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
76
77 qemu_fdt_add_subnode(fdt, "/htif");
78 qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0");
79
80 qemu_fdt_add_subnode(fdt, "/soc");
81 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
82 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
83 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
84 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
85
86 qemu_fdt_add_subnode(fdt, "/cpus");
87 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
88 SIFIVE_CLINT_TIMEBASE_FREQ);
89 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
90 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
91 qemu_fdt_add_subnode(fdt, "/cpus/cpu-map");
92
93 for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) {
94 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket);
95 qemu_fdt_add_subnode(fdt, clust_name);
96
97 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
98
99 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {
100 cpu_phandle = phandle++;
101
102 cpu_name = g_strdup_printf("/cpus/cpu@%d",
103 s->soc[socket].hartid_base + cpu);
104 qemu_fdt_add_subnode(fdt, cpu_name);
105 if (is_32_bit) {
106 qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32");
107 } else {
108 qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48");
109 }
110 name = riscv_isa_string(&s->soc[socket].harts[cpu]);
111 qemu_fdt_setprop_string(fdt, cpu_name, "riscv,isa", name);
112 g_free(name);
113 qemu_fdt_setprop_string(fdt, cpu_name, "compatible", "riscv");
114 qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay");
115 qemu_fdt_setprop_cell(fdt, cpu_name, "reg",
116 s->soc[socket].hartid_base + cpu);
117 qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu");
118 riscv_socket_fdt_write_id(mc, fdt, cpu_name, socket);
119 qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle);
120
121 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name);
122 qemu_fdt_add_subnode(fdt, intc_name);
123 intc_phandle = phandle++;
124 qemu_fdt_setprop_cell(fdt, intc_name, "phandle", intc_phandle);
125 qemu_fdt_setprop_string(fdt, intc_name, "compatible",
126 "riscv,cpu-intc");
127 qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0);
128 qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1);
129
130 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
131 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
132 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
133 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
134
135 core_name = g_strdup_printf("%s/core%d", clust_name, cpu);
136 qemu_fdt_add_subnode(fdt, core_name);
137 qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle);
138
139 g_free(core_name);
140 g_free(intc_name);
141 g_free(cpu_name);
142 }
143
144 addr = memmap[SPIKE_DRAM].base + riscv_socket_mem_offset(mc, socket);
145 size = riscv_socket_mem_size(mc, socket);
146 mem_name = g_strdup_printf("/memory@%lx", (long)addr);
147 qemu_fdt_add_subnode(fdt, mem_name);
148 qemu_fdt_setprop_cells(fdt, mem_name, "reg",
149 addr >> 32, addr, size >> 32, size);
150 qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory");
151 riscv_socket_fdt_write_id(mc, fdt, mem_name, socket);
152 g_free(mem_name);
153
154 clint_addr = memmap[SPIKE_CLINT].base +
155 (memmap[SPIKE_CLINT].size * socket);
156 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
157 qemu_fdt_add_subnode(fdt, clint_name);
158 qemu_fdt_setprop_string_array(fdt, clint_name, "compatible",
159 (char **)&clint_compat, ARRAY_SIZE(clint_compat));
160 qemu_fdt_setprop_cells(fdt, clint_name, "reg",
161 0x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size);
162 qemu_fdt_setprop(fdt, clint_name, "interrupts-extended",
163 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
164 riscv_socket_fdt_write_id(mc, fdt, clint_name, socket);
165
166 g_free(clint_name);
167 g_free(clint_cells);
168 g_free(clust_name);
169 }
170
171 riscv_socket_fdt_write_distance_matrix(mc, fdt);
172
173 if (cmdline) {
174 qemu_fdt_add_subnode(fdt, "/chosen");
175 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
176 }
177 }
178
179 static void spike_board_init(MachineState *machine)
180 {
181 const MemMapEntry *memmap = spike_memmap;
182 SpikeState *s = SPIKE_MACHINE(machine);
183 MemoryRegion *system_memory = get_system_memory();
184 MemoryRegion *main_mem = g_new(MemoryRegion, 1);
185 MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
186 target_ulong firmware_end_addr, kernel_start_addr;
187 uint32_t fdt_load_addr;
188 uint64_t kernel_entry;
189 char *soc_name;
190 int i, base_hartid, hart_count;
191
192 /* Check socket count limit */
193 if (SPIKE_SOCKETS_MAX < riscv_socket_count(machine)) {
194 error_report("number of sockets/nodes should be less than %d",
195 SPIKE_SOCKETS_MAX);
196 exit(1);
197 }
198
199 /* Initialize sockets */
200 for (i = 0; i < riscv_socket_count(machine); i++) {
201 if (!riscv_socket_check_hartids(machine, i)) {
202 error_report("discontinuous hartids in socket%d", i);
203 exit(1);
204 }
205
206 base_hartid = riscv_socket_first_hartid(machine, i);
207 if (base_hartid < 0) {
208 error_report("can't find hartid base for socket%d", i);
209 exit(1);
210 }
211
212 hart_count = riscv_socket_hart_count(machine, i);
213 if (hart_count < 0) {
214 error_report("can't find hart count for socket%d", i);
215 exit(1);
216 }
217
218 soc_name = g_strdup_printf("soc%d", i);
219 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i],
220 TYPE_RISCV_HART_ARRAY);
221 g_free(soc_name);
222 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type",
223 machine->cpu_type, &error_abort);
224 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base",
225 base_hartid, &error_abort);
226 object_property_set_int(OBJECT(&s->soc[i]), "num-harts",
227 hart_count, &error_abort);
228 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort);
229
230 /* Core Local Interruptor (timer and IPI) for each socket */
231 sifive_clint_create(
232 memmap[SPIKE_CLINT].base + i * memmap[SPIKE_CLINT].size,
233 memmap[SPIKE_CLINT].size, base_hartid, hart_count,
234 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
235 SIFIVE_CLINT_TIMEBASE_FREQ, false);
236 }
237
238 /* register system main memory (actual RAM) */
239 memory_region_init_ram(main_mem, NULL, "riscv.spike.ram",
240 machine->ram_size, &error_fatal);
241 memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
242 main_mem);
243
244 /* create device tree */
245 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
246 riscv_is_32bit(&s->soc[0]));
247
248 /* boot rom */
249 memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
250 memmap[SPIKE_MROM].size, &error_fatal);
251 memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
252 mask_rom);
253
254 /*
255 * Not like other RISC-V machines that use plain binary bios images,
256 * keeping ELF files here was intentional because BIN files don't work
257 * for the Spike machine as HTIF emulation depends on ELF parsing.
258 */
259 if (riscv_is_32bit(&s->soc[0])) {
260 firmware_end_addr = riscv_find_and_load_firmware(machine,
261 RISCV32_BIOS_ELF, memmap[SPIKE_DRAM].base,
262 htif_symbol_callback);
263 } else {
264 firmware_end_addr = riscv_find_and_load_firmware(machine,
265 RISCV64_BIOS_ELF, memmap[SPIKE_DRAM].base,
266 htif_symbol_callback);
267 }
268
269 if (machine->kernel_filename) {
270 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
271 firmware_end_addr);
272
273 kernel_entry = riscv_load_kernel(machine->kernel_filename,
274 kernel_start_addr,
275 htif_symbol_callback);
276
277 if (machine->initrd_filename) {
278 hwaddr start;
279 hwaddr end = riscv_load_initrd(machine->initrd_filename,
280 machine->ram_size, kernel_entry,
281 &start);
282 qemu_fdt_setprop_cell(s->fdt, "/chosen",
283 "linux,initrd-start", start);
284 qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
285 end);
286 }
287 } else {
288 /*
289 * If dynamic firmware is used, it doesn't know where is the next mode
290 * if kernel argument is not set.
291 */
292 kernel_entry = 0;
293 }
294
295 /* Compute the fdt load address in dram */
296 fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base,
297 machine->ram_size, s->fdt);
298 /* load the reset vector */
299 riscv_setup_rom_reset_vec(machine, &s->soc[0], memmap[SPIKE_DRAM].base,
300 memmap[SPIKE_MROM].base,
301 memmap[SPIKE_MROM].size, kernel_entry,
302 fdt_load_addr, s->fdt);
303
304 /* initialize HTIF using symbols found in load_kernel */
305 htif_mm_init(system_memory, mask_rom,
306 &s->soc[0].harts[0].env, serial_hd(0));
307 }
308
309 static void spike_machine_instance_init(Object *obj)
310 {
311 }
312
313 static void spike_machine_class_init(ObjectClass *oc, void *data)
314 {
315 MachineClass *mc = MACHINE_CLASS(oc);
316
317 mc->desc = "RISC-V Spike board";
318 mc->init = spike_board_init;
319 mc->max_cpus = SPIKE_CPUS_MAX;
320 mc->is_default = true;
321 mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
322 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;
323 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
324 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
325 mc->numa_mem_supported = true;
326 }
327
328 static const TypeInfo spike_machine_typeinfo = {
329 .name = MACHINE_TYPE_NAME("spike"),
330 .parent = TYPE_MACHINE,
331 .class_init = spike_machine_class_init,
332 .instance_init = spike_machine_instance_init,
333 .instance_size = sizeof(SpikeState),
334 };
335
336 static void spike_machine_init_register_types(void)
337 {
338 type_register_static(&spike_machine_typeinfo);
339 }
340
341 type_init(spike_machine_init_register_types)