Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20220121...
[qemu.git] / hw / riscv / spike.c
1 /*
2 * QEMU RISC-V Spike Board
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
6 *
7 * This provides a RISC-V Board with the following devices:
8 *
9 * 0) HTIF Console and Poweroff
10 * 1) CLINT (Timer and IPI)
11 * 2) PLIC (Platform Level Interrupt Controller)
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms and conditions of the GNU General Public License,
15 * version 2 or later, as published by the Free Software Foundation.
16 *
17 * This program is distributed in the hope it will be useful, but WITHOUT
18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
20 * more details.
21 *
22 * You should have received a copy of the GNU General Public License along with
23 * this program. If not, see <http://www.gnu.org/licenses/>.
24 */
25
26 #include "qemu/osdep.h"
27 #include "qemu/error-report.h"
28 #include "qapi/error.h"
29 #include "hw/boards.h"
30 #include "hw/loader.h"
31 #include "hw/sysbus.h"
32 #include "target/riscv/cpu.h"
33 #include "hw/riscv/riscv_hart.h"
34 #include "hw/riscv/spike.h"
35 #include "hw/riscv/boot.h"
36 #include "hw/riscv/numa.h"
37 #include "hw/char/riscv_htif.h"
38 #include "hw/intc/riscv_aclint.h"
39 #include "chardev/char.h"
40 #include "sysemu/device_tree.h"
41 #include "sysemu/sysemu.h"
42
43 static const MemMapEntry spike_memmap[] = {
44 [SPIKE_MROM] = { 0x1000, 0xf000 },
45 [SPIKE_HTIF] = { 0x1000000, 0x1000 },
46 [SPIKE_CLINT] = { 0x2000000, 0x10000 },
47 [SPIKE_DRAM] = { 0x80000000, 0x0 },
48 };
49
50 static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
51 uint64_t mem_size, const char *cmdline, bool is_32_bit)
52 {
53 void *fdt;
54 uint64_t addr, size;
55 unsigned long clint_addr;
56 int cpu, socket;
57 MachineState *mc = MACHINE(s);
58 uint32_t *clint_cells;
59 uint32_t cpu_phandle, intc_phandle, phandle = 1;
60 char *name, *mem_name, *clint_name, *clust_name;
61 char *core_name, *cpu_name, *intc_name;
62 static const char * const clint_compat[2] = {
63 "sifive,clint0", "riscv,clint0"
64 };
65
66 fdt = s->fdt = create_device_tree(&s->fdt_size);
67 if (!fdt) {
68 error_report("create_device_tree() failed");
69 exit(1);
70 }
71
72 qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu");
73 qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev");
74 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
75 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
76
77 qemu_fdt_add_subnode(fdt, "/htif");
78 qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0");
79 if (!htif_uses_elf_symbols()) {
80 qemu_fdt_setprop_cells(fdt, "/htif", "reg",
81 0x0, memmap[SPIKE_HTIF].base, 0x0, memmap[SPIKE_HTIF].size);
82 }
83
84 qemu_fdt_add_subnode(fdt, "/soc");
85 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
86 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
87 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
88 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
89
90 qemu_fdt_add_subnode(fdt, "/cpus");
91 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
92 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ);
93 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
94 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
95 qemu_fdt_add_subnode(fdt, "/cpus/cpu-map");
96
97 for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) {
98 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket);
99 qemu_fdt_add_subnode(fdt, clust_name);
100
101 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
102
103 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {
104 cpu_phandle = phandle++;
105
106 cpu_name = g_strdup_printf("/cpus/cpu@%d",
107 s->soc[socket].hartid_base + cpu);
108 qemu_fdt_add_subnode(fdt, cpu_name);
109 if (is_32_bit) {
110 qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32");
111 } else {
112 qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48");
113 }
114 name = riscv_isa_string(&s->soc[socket].harts[cpu]);
115 qemu_fdt_setprop_string(fdt, cpu_name, "riscv,isa", name);
116 g_free(name);
117 qemu_fdt_setprop_string(fdt, cpu_name, "compatible", "riscv");
118 qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay");
119 qemu_fdt_setprop_cell(fdt, cpu_name, "reg",
120 s->soc[socket].hartid_base + cpu);
121 qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu");
122 riscv_socket_fdt_write_id(mc, fdt, cpu_name, socket);
123 qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle);
124
125 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name);
126 qemu_fdt_add_subnode(fdt, intc_name);
127 intc_phandle = phandle++;
128 qemu_fdt_setprop_cell(fdt, intc_name, "phandle", intc_phandle);
129 qemu_fdt_setprop_string(fdt, intc_name, "compatible",
130 "riscv,cpu-intc");
131 qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0);
132 qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1);
133
134 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
135 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
136 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
137 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
138
139 core_name = g_strdup_printf("%s/core%d", clust_name, cpu);
140 qemu_fdt_add_subnode(fdt, core_name);
141 qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle);
142
143 g_free(core_name);
144 g_free(intc_name);
145 g_free(cpu_name);
146 }
147
148 addr = memmap[SPIKE_DRAM].base + riscv_socket_mem_offset(mc, socket);
149 size = riscv_socket_mem_size(mc, socket);
150 mem_name = g_strdup_printf("/memory@%lx", (long)addr);
151 qemu_fdt_add_subnode(fdt, mem_name);
152 qemu_fdt_setprop_cells(fdt, mem_name, "reg",
153 addr >> 32, addr, size >> 32, size);
154 qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory");
155 riscv_socket_fdt_write_id(mc, fdt, mem_name, socket);
156 g_free(mem_name);
157
158 clint_addr = memmap[SPIKE_CLINT].base +
159 (memmap[SPIKE_CLINT].size * socket);
160 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
161 qemu_fdt_add_subnode(fdt, clint_name);
162 qemu_fdt_setprop_string_array(fdt, clint_name, "compatible",
163 (char **)&clint_compat, ARRAY_SIZE(clint_compat));
164 qemu_fdt_setprop_cells(fdt, clint_name, "reg",
165 0x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size);
166 qemu_fdt_setprop(fdt, clint_name, "interrupts-extended",
167 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
168 riscv_socket_fdt_write_id(mc, fdt, clint_name, socket);
169
170 g_free(clint_name);
171 g_free(clint_cells);
172 g_free(clust_name);
173 }
174
175 riscv_socket_fdt_write_distance_matrix(mc, fdt);
176
177 if (cmdline) {
178 qemu_fdt_add_subnode(fdt, "/chosen");
179 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
180 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif");
181 }
182 }
183
184 static void spike_board_init(MachineState *machine)
185 {
186 const MemMapEntry *memmap = spike_memmap;
187 SpikeState *s = SPIKE_MACHINE(machine);
188 MemoryRegion *system_memory = get_system_memory();
189 MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
190 target_ulong firmware_end_addr, kernel_start_addr;
191 uint32_t fdt_load_addr;
192 uint64_t kernel_entry;
193 char *soc_name;
194 int i, base_hartid, hart_count;
195
196 /* Check socket count limit */
197 if (SPIKE_SOCKETS_MAX < riscv_socket_count(machine)) {
198 error_report("number of sockets/nodes should be less than %d",
199 SPIKE_SOCKETS_MAX);
200 exit(1);
201 }
202
203 /* Initialize sockets */
204 for (i = 0; i < riscv_socket_count(machine); i++) {
205 if (!riscv_socket_check_hartids(machine, i)) {
206 error_report("discontinuous hartids in socket%d", i);
207 exit(1);
208 }
209
210 base_hartid = riscv_socket_first_hartid(machine, i);
211 if (base_hartid < 0) {
212 error_report("can't find hartid base for socket%d", i);
213 exit(1);
214 }
215
216 hart_count = riscv_socket_hart_count(machine, i);
217 if (hart_count < 0) {
218 error_report("can't find hart count for socket%d", i);
219 exit(1);
220 }
221
222 soc_name = g_strdup_printf("soc%d", i);
223 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i],
224 TYPE_RISCV_HART_ARRAY);
225 g_free(soc_name);
226 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type",
227 machine->cpu_type, &error_abort);
228 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base",
229 base_hartid, &error_abort);
230 object_property_set_int(OBJECT(&s->soc[i]), "num-harts",
231 hart_count, &error_abort);
232 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort);
233
234 /* Core Local Interruptor (timer and IPI) for each socket */
235 riscv_aclint_swi_create(
236 memmap[SPIKE_CLINT].base + i * memmap[SPIKE_CLINT].size,
237 base_hartid, hart_count, false);
238 riscv_aclint_mtimer_create(
239 memmap[SPIKE_CLINT].base + i * memmap[SPIKE_CLINT].size +
240 RISCV_ACLINT_SWI_SIZE,
241 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count,
242 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
243 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, false);
244 }
245
246 /* register system main memory (actual RAM) */
247 memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
248 machine->ram);
249
250 /* boot rom */
251 memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
252 memmap[SPIKE_MROM].size, &error_fatal);
253 memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
254 mask_rom);
255
256 /*
257 * Not like other RISC-V machines that use plain binary bios images,
258 * keeping ELF files here was intentional because BIN files don't work
259 * for the Spike machine as HTIF emulation depends on ELF parsing.
260 */
261 if (riscv_is_32bit(&s->soc[0])) {
262 firmware_end_addr = riscv_find_and_load_firmware(machine,
263 RISCV32_BIOS_BIN, memmap[SPIKE_DRAM].base,
264 htif_symbol_callback);
265 } else {
266 firmware_end_addr = riscv_find_and_load_firmware(machine,
267 RISCV64_BIOS_BIN, memmap[SPIKE_DRAM].base,
268 htif_symbol_callback);
269 }
270
271 /* Load kernel */
272 if (machine->kernel_filename) {
273 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
274 firmware_end_addr);
275
276 kernel_entry = riscv_load_kernel(machine->kernel_filename,
277 kernel_start_addr,
278 htif_symbol_callback);
279 } else {
280 /*
281 * If dynamic firmware is used, it doesn't know where is the next mode
282 * if kernel argument is not set.
283 */
284 kernel_entry = 0;
285 }
286
287 /* Create device tree */
288 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
289 riscv_is_32bit(&s->soc[0]));
290
291 /* Load initrd */
292 if (machine->kernel_filename && machine->initrd_filename) {
293 hwaddr start;
294 hwaddr end = riscv_load_initrd(machine->initrd_filename,
295 machine->ram_size, kernel_entry,
296 &start);
297 qemu_fdt_setprop_cell(s->fdt, "/chosen",
298 "linux,initrd-start", start);
299 qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
300 end);
301 }
302
303 /* Compute the fdt load address in dram */
304 fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base,
305 machine->ram_size, s->fdt);
306 /* load the reset vector */
307 riscv_setup_rom_reset_vec(machine, &s->soc[0], memmap[SPIKE_DRAM].base,
308 memmap[SPIKE_MROM].base,
309 memmap[SPIKE_MROM].size, kernel_entry,
310 fdt_load_addr, s->fdt);
311
312 /* initialize HTIF using symbols found in load_kernel */
313 htif_mm_init(system_memory, mask_rom,
314 &s->soc[0].harts[0].env, serial_hd(0),
315 memmap[SPIKE_HTIF].base);
316 }
317
318 static void spike_machine_instance_init(Object *obj)
319 {
320 }
321
322 static void spike_machine_class_init(ObjectClass *oc, void *data)
323 {
324 MachineClass *mc = MACHINE_CLASS(oc);
325
326 mc->desc = "RISC-V Spike board";
327 mc->init = spike_board_init;
328 mc->max_cpus = SPIKE_CPUS_MAX;
329 mc->is_default = true;
330 mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
331 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;
332 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
333 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
334 mc->numa_mem_supported = true;
335 mc->default_ram_id = "riscv.spike.ram";
336 }
337
338 static const TypeInfo spike_machine_typeinfo = {
339 .name = MACHINE_TYPE_NAME("spike"),
340 .parent = TYPE_MACHINE,
341 .class_init = spike_machine_class_init,
342 .instance_init = spike_machine_instance_init,
343 .instance_size = sizeof(SpikeState),
344 };
345
346 static void spike_machine_init_register_types(void)
347 {
348 type_register_static(&spike_machine_typeinfo);
349 }
350
351 type_init(spike_machine_init_register_types)