Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging
[qemu.git] / hw / riscv / virt.c
1 /*
2 * QEMU RISC-V VirtIO Board
3 *
4 * Copyright (c) 2017 SiFive, Inc.
5 *
6 * RISC-V machine with 16550a UART and VirtIO MMIO
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "qemu/units.h"
23 #include "qemu/error-report.h"
24 #include "qapi/error.h"
25 #include "hw/boards.h"
26 #include "hw/loader.h"
27 #include "hw/sysbus.h"
28 #include "hw/qdev-properties.h"
29 #include "hw/char/serial.h"
30 #include "target/riscv/cpu.h"
31 #include "hw/riscv/riscv_hart.h"
32 #include "hw/riscv/virt.h"
33 #include "hw/riscv/boot.h"
34 #include "hw/riscv/numa.h"
35 #include "hw/intc/sifive_clint.h"
36 #include "hw/intc/sifive_plic.h"
37 #include "hw/misc/sifive_test.h"
38 #include "chardev/char.h"
39 #include "sysemu/arch_init.h"
40 #include "sysemu/device_tree.h"
41 #include "sysemu/sysemu.h"
42 #include "hw/pci/pci.h"
43 #include "hw/pci-host/gpex.h"
44 #include "hw/display/ramfb.h"
45
46 static const MemMapEntry virt_memmap[] = {
47 [VIRT_DEBUG] = { 0x0, 0x100 },
48 [VIRT_MROM] = { 0x1000, 0xf000 },
49 [VIRT_TEST] = { 0x100000, 0x1000 },
50 [VIRT_RTC] = { 0x101000, 0x1000 },
51 [VIRT_CLINT] = { 0x2000000, 0x10000 },
52 [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 },
53 [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
54 [VIRT_UART0] = { 0x10000000, 0x100 },
55 [VIRT_VIRTIO] = { 0x10001000, 0x1000 },
56 [VIRT_FW_CFG] = { 0x10100000, 0x18 },
57 [VIRT_FLASH] = { 0x20000000, 0x4000000 },
58 [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 },
59 [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 },
60 [VIRT_DRAM] = { 0x80000000, 0x0 },
61 };
62
63 /* PCIe high mmio is fixed for RV32 */
64 #define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL
65 #define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB)
66
67 /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */
68 #define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB)
69
70 static MemMapEntry virt_high_pcie_memmap;
71
72 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
73
74 static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s,
75 const char *name,
76 const char *alias_prop_name)
77 {
78 /*
79 * Create a single flash device. We use the same parameters as
80 * the flash devices on the ARM virt board.
81 */
82 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
83
84 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE);
85 qdev_prop_set_uint8(dev, "width", 4);
86 qdev_prop_set_uint8(dev, "device-width", 2);
87 qdev_prop_set_bit(dev, "big-endian", false);
88 qdev_prop_set_uint16(dev, "id0", 0x89);
89 qdev_prop_set_uint16(dev, "id1", 0x18);
90 qdev_prop_set_uint16(dev, "id2", 0x00);
91 qdev_prop_set_uint16(dev, "id3", 0x00);
92 qdev_prop_set_string(dev, "name", name);
93
94 object_property_add_child(OBJECT(s), name, OBJECT(dev));
95 object_property_add_alias(OBJECT(s), alias_prop_name,
96 OBJECT(dev), "drive");
97
98 return PFLASH_CFI01(dev);
99 }
100
101 static void virt_flash_create(RISCVVirtState *s)
102 {
103 s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0");
104 s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1");
105 }
106
107 static void virt_flash_map1(PFlashCFI01 *flash,
108 hwaddr base, hwaddr size,
109 MemoryRegion *sysmem)
110 {
111 DeviceState *dev = DEVICE(flash);
112
113 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE));
114 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX);
115 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE);
116 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
117
118 memory_region_add_subregion(sysmem, base,
119 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
120 0));
121 }
122
123 static void virt_flash_map(RISCVVirtState *s,
124 MemoryRegion *sysmem)
125 {
126 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
127 hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
128
129 virt_flash_map1(s->flash[0], flashbase, flashsize,
130 sysmem);
131 virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize,
132 sysmem);
133 }
134
135 static void create_pcie_irq_map(void *fdt, char *nodename,
136 uint32_t plic_phandle)
137 {
138 int pin, dev;
139 uint32_t
140 full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * FDT_INT_MAP_WIDTH] = {};
141 uint32_t *irq_map = full_irq_map;
142
143 /* This code creates a standard swizzle of interrupts such that
144 * each device's first interrupt is based on it's PCI_SLOT number.
145 * (See pci_swizzle_map_irq_fn())
146 *
147 * We only need one entry per interrupt in the table (not one per
148 * possible slot) seeing the interrupt-map-mask will allow the table
149 * to wrap to any number of devices.
150 */
151 for (dev = 0; dev < GPEX_NUM_IRQS; dev++) {
152 int devfn = dev * 0x8;
153
154 for (pin = 0; pin < GPEX_NUM_IRQS; pin++) {
155 int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS);
156 int i = 0;
157
158 irq_map[i] = cpu_to_be32(devfn << 8);
159
160 i += FDT_PCI_ADDR_CELLS;
161 irq_map[i] = cpu_to_be32(pin + 1);
162
163 i += FDT_PCI_INT_CELLS;
164 irq_map[i++] = cpu_to_be32(plic_phandle);
165
166 i += FDT_PLIC_ADDR_CELLS;
167 irq_map[i] = cpu_to_be32(irq_nr);
168
169 irq_map += FDT_INT_MAP_WIDTH;
170 }
171 }
172
173 qemu_fdt_setprop(fdt, nodename, "interrupt-map",
174 full_irq_map, sizeof(full_irq_map));
175
176 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask",
177 0x1800, 0, 0, 0x7);
178 }
179
180 static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
181 uint64_t mem_size, const char *cmdline, bool is_32_bit)
182 {
183 void *fdt;
184 int i, cpu, socket;
185 MachineState *mc = MACHINE(s);
186 uint64_t addr, size;
187 uint32_t *clint_cells, *plic_cells;
188 unsigned long clint_addr, plic_addr;
189 uint32_t plic_phandle[MAX_NODES];
190 uint32_t cpu_phandle, intc_phandle, test_phandle;
191 uint32_t phandle = 1, plic_mmio_phandle = 1;
192 uint32_t plic_pcie_phandle = 1, plic_virtio_phandle = 1;
193 char *mem_name, *cpu_name, *core_name, *intc_name;
194 char *name, *clint_name, *plic_name, *clust_name;
195 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
196 hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
197 static const char * const clint_compat[2] = {
198 "sifive,clint0", "riscv,clint0"
199 };
200 static const char * const plic_compat[2] = {
201 "sifive,plic-1.0.0", "riscv,plic0"
202 };
203
204 if (mc->dtb) {
205 fdt = mc->fdt = load_device_tree(mc->dtb, &s->fdt_size);
206 if (!fdt) {
207 error_report("load_device_tree() failed");
208 exit(1);
209 }
210 goto update_bootargs;
211 } else {
212 fdt = mc->fdt = create_device_tree(&s->fdt_size);
213 if (!fdt) {
214 error_report("create_device_tree() failed");
215 exit(1);
216 }
217 }
218
219 qemu_fdt_setprop_string(fdt, "/", "model", "riscv-virtio,qemu");
220 qemu_fdt_setprop_string(fdt, "/", "compatible", "riscv-virtio");
221 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
222 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
223
224 qemu_fdt_add_subnode(fdt, "/soc");
225 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
226 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
227 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
228 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
229
230 qemu_fdt_add_subnode(fdt, "/cpus");
231 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
232 SIFIVE_CLINT_TIMEBASE_FREQ);
233 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
234 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
235 qemu_fdt_add_subnode(fdt, "/cpus/cpu-map");
236
237 for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) {
238 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket);
239 qemu_fdt_add_subnode(fdt, clust_name);
240
241 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
242 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
243
244 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {
245 cpu_phandle = phandle++;
246
247 cpu_name = g_strdup_printf("/cpus/cpu@%d",
248 s->soc[socket].hartid_base + cpu);
249 qemu_fdt_add_subnode(fdt, cpu_name);
250 if (is_32_bit) {
251 qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32");
252 } else {
253 qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48");
254 }
255 name = riscv_isa_string(&s->soc[socket].harts[cpu]);
256 qemu_fdt_setprop_string(fdt, cpu_name, "riscv,isa", name);
257 g_free(name);
258 qemu_fdt_setprop_string(fdt, cpu_name, "compatible", "riscv");
259 qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay");
260 qemu_fdt_setprop_cell(fdt, cpu_name, "reg",
261 s->soc[socket].hartid_base + cpu);
262 qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu");
263 riscv_socket_fdt_write_id(mc, fdt, cpu_name, socket);
264 qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle);
265
266 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name);
267 qemu_fdt_add_subnode(fdt, intc_name);
268 intc_phandle = phandle++;
269 qemu_fdt_setprop_cell(fdt, intc_name, "phandle", intc_phandle);
270 qemu_fdt_setprop_string(fdt, intc_name, "compatible",
271 "riscv,cpu-intc");
272 qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0);
273 qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1);
274
275 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
276 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
277 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
278 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
279
280 plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
281 plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
282 plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
283 plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
284
285 core_name = g_strdup_printf("%s/core%d", clust_name, cpu);
286 qemu_fdt_add_subnode(fdt, core_name);
287 qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle);
288
289 g_free(core_name);
290 g_free(intc_name);
291 g_free(cpu_name);
292 }
293
294 addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(mc, socket);
295 size = riscv_socket_mem_size(mc, socket);
296 mem_name = g_strdup_printf("/memory@%lx", (long)addr);
297 qemu_fdt_add_subnode(fdt, mem_name);
298 qemu_fdt_setprop_cells(fdt, mem_name, "reg",
299 addr >> 32, addr, size >> 32, size);
300 qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory");
301 riscv_socket_fdt_write_id(mc, fdt, mem_name, socket);
302 g_free(mem_name);
303
304 clint_addr = memmap[VIRT_CLINT].base +
305 (memmap[VIRT_CLINT].size * socket);
306 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
307 qemu_fdt_add_subnode(fdt, clint_name);
308 qemu_fdt_setprop_string_array(fdt, clint_name, "compatible",
309 (char **)&clint_compat, ARRAY_SIZE(clint_compat));
310 qemu_fdt_setprop_cells(fdt, clint_name, "reg",
311 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size);
312 qemu_fdt_setprop(fdt, clint_name, "interrupts-extended",
313 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
314 riscv_socket_fdt_write_id(mc, fdt, clint_name, socket);
315 g_free(clint_name);
316
317 plic_phandle[socket] = phandle++;
318 plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket);
319 plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr);
320 qemu_fdt_add_subnode(fdt, plic_name);
321 qemu_fdt_setprop_cell(fdt, plic_name,
322 "#address-cells", FDT_PLIC_ADDR_CELLS);
323 qemu_fdt_setprop_cell(fdt, plic_name,
324 "#interrupt-cells", FDT_PLIC_INT_CELLS);
325 qemu_fdt_setprop_string_array(fdt, plic_name, "compatible",
326 (char **)&plic_compat, ARRAY_SIZE(plic_compat));
327 qemu_fdt_setprop(fdt, plic_name, "interrupt-controller", NULL, 0);
328 qemu_fdt_setprop(fdt, plic_name, "interrupts-extended",
329 plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
330 qemu_fdt_setprop_cells(fdt, plic_name, "reg",
331 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size);
332 qemu_fdt_setprop_cell(fdt, plic_name, "riscv,ndev", VIRTIO_NDEV);
333 riscv_socket_fdt_write_id(mc, fdt, plic_name, socket);
334 qemu_fdt_setprop_cell(fdt, plic_name, "phandle", plic_phandle[socket]);
335 g_free(plic_name);
336
337 g_free(clint_cells);
338 g_free(plic_cells);
339 g_free(clust_name);
340 }
341
342 for (socket = 0; socket < riscv_socket_count(mc); socket++) {
343 if (socket == 0) {
344 plic_mmio_phandle = plic_phandle[socket];
345 plic_virtio_phandle = plic_phandle[socket];
346 plic_pcie_phandle = plic_phandle[socket];
347 }
348 if (socket == 1) {
349 plic_virtio_phandle = plic_phandle[socket];
350 plic_pcie_phandle = plic_phandle[socket];
351 }
352 if (socket == 2) {
353 plic_pcie_phandle = plic_phandle[socket];
354 }
355 }
356
357 riscv_socket_fdt_write_distance_matrix(mc, fdt);
358
359 for (i = 0; i < VIRTIO_COUNT; i++) {
360 name = g_strdup_printf("/soc/virtio_mmio@%lx",
361 (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size));
362 qemu_fdt_add_subnode(fdt, name);
363 qemu_fdt_setprop_string(fdt, name, "compatible", "virtio,mmio");
364 qemu_fdt_setprop_cells(fdt, name, "reg",
365 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
366 0x0, memmap[VIRT_VIRTIO].size);
367 qemu_fdt_setprop_cell(fdt, name, "interrupt-parent",
368 plic_virtio_phandle);
369 qemu_fdt_setprop_cell(fdt, name, "interrupts", VIRTIO_IRQ + i);
370 g_free(name);
371 }
372
373 name = g_strdup_printf("/soc/pci@%lx",
374 (long) memmap[VIRT_PCIE_ECAM].base);
375 qemu_fdt_add_subnode(fdt, name);
376 qemu_fdt_setprop_cell(fdt, name, "#address-cells", FDT_PCI_ADDR_CELLS);
377 qemu_fdt_setprop_cell(fdt, name, "#interrupt-cells", FDT_PCI_INT_CELLS);
378 qemu_fdt_setprop_cell(fdt, name, "#size-cells", 0x2);
379 qemu_fdt_setprop_string(fdt, name, "compatible", "pci-host-ecam-generic");
380 qemu_fdt_setprop_string(fdt, name, "device_type", "pci");
381 qemu_fdt_setprop_cell(fdt, name, "linux,pci-domain", 0);
382 qemu_fdt_setprop_cells(fdt, name, "bus-range", 0,
383 memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1);
384 qemu_fdt_setprop(fdt, name, "dma-coherent", NULL, 0);
385 qemu_fdt_setprop_cells(fdt, name, "reg", 0,
386 memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size);
387 qemu_fdt_setprop_sized_cells(fdt, name, "ranges",
388 1, FDT_PCI_RANGE_IOPORT, 2, 0,
389 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size,
390 1, FDT_PCI_RANGE_MMIO,
391 2, memmap[VIRT_PCIE_MMIO].base,
392 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size,
393 1, FDT_PCI_RANGE_MMIO_64BIT,
394 2, virt_high_pcie_memmap.base,
395 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size);
396
397 create_pcie_irq_map(fdt, name, plic_pcie_phandle);
398 g_free(name);
399
400 test_phandle = phandle++;
401 name = g_strdup_printf("/soc/test@%lx",
402 (long)memmap[VIRT_TEST].base);
403 qemu_fdt_add_subnode(fdt, name);
404 {
405 static const char * const compat[3] = {
406 "sifive,test1", "sifive,test0", "syscon"
407 };
408 qemu_fdt_setprop_string_array(fdt, name, "compatible", (char **)&compat,
409 ARRAY_SIZE(compat));
410 }
411 qemu_fdt_setprop_cells(fdt, name, "reg",
412 0x0, memmap[VIRT_TEST].base,
413 0x0, memmap[VIRT_TEST].size);
414 qemu_fdt_setprop_cell(fdt, name, "phandle", test_phandle);
415 test_phandle = qemu_fdt_get_phandle(fdt, name);
416 g_free(name);
417
418 name = g_strdup_printf("/soc/reboot");
419 qemu_fdt_add_subnode(fdt, name);
420 qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-reboot");
421 qemu_fdt_setprop_cell(fdt, name, "regmap", test_phandle);
422 qemu_fdt_setprop_cell(fdt, name, "offset", 0x0);
423 qemu_fdt_setprop_cell(fdt, name, "value", FINISHER_RESET);
424 g_free(name);
425
426 name = g_strdup_printf("/soc/poweroff");
427 qemu_fdt_add_subnode(fdt, name);
428 qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-poweroff");
429 qemu_fdt_setprop_cell(fdt, name, "regmap", test_phandle);
430 qemu_fdt_setprop_cell(fdt, name, "offset", 0x0);
431 qemu_fdt_setprop_cell(fdt, name, "value", FINISHER_PASS);
432 g_free(name);
433
434 name = g_strdup_printf("/soc/uart@%lx", (long)memmap[VIRT_UART0].base);
435 qemu_fdt_add_subnode(fdt, name);
436 qemu_fdt_setprop_string(fdt, name, "compatible", "ns16550a");
437 qemu_fdt_setprop_cells(fdt, name, "reg",
438 0x0, memmap[VIRT_UART0].base,
439 0x0, memmap[VIRT_UART0].size);
440 qemu_fdt_setprop_cell(fdt, name, "clock-frequency", 3686400);
441 qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", plic_mmio_phandle);
442 qemu_fdt_setprop_cell(fdt, name, "interrupts", UART0_IRQ);
443
444 qemu_fdt_add_subnode(fdt, "/chosen");
445 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", name);
446 g_free(name);
447
448 name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base);
449 qemu_fdt_add_subnode(fdt, name);
450 qemu_fdt_setprop_string(fdt, name, "compatible", "google,goldfish-rtc");
451 qemu_fdt_setprop_cells(fdt, name, "reg",
452 0x0, memmap[VIRT_RTC].base,
453 0x0, memmap[VIRT_RTC].size);
454 qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", plic_mmio_phandle);
455 qemu_fdt_setprop_cell(fdt, name, "interrupts", RTC_IRQ);
456 g_free(name);
457
458 name = g_strdup_printf("/soc/flash@%" PRIx64, flashbase);
459 qemu_fdt_add_subnode(mc->fdt, name);
460 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "cfi-flash");
461 qemu_fdt_setprop_sized_cells(mc->fdt, name, "reg",
462 2, flashbase, 2, flashsize,
463 2, flashbase + flashsize, 2, flashsize);
464 qemu_fdt_setprop_cell(mc->fdt, name, "bank-width", 4);
465 g_free(name);
466
467 update_bootargs:
468 if (cmdline) {
469 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
470 }
471 }
472
473 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
474 hwaddr ecam_base, hwaddr ecam_size,
475 hwaddr mmio_base, hwaddr mmio_size,
476 hwaddr high_mmio_base,
477 hwaddr high_mmio_size,
478 hwaddr pio_base,
479 DeviceState *plic)
480 {
481 DeviceState *dev;
482 MemoryRegion *ecam_alias, *ecam_reg;
483 MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg;
484 qemu_irq irq;
485 int i;
486
487 dev = qdev_new(TYPE_GPEX_HOST);
488
489 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
490
491 ecam_alias = g_new0(MemoryRegion, 1);
492 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
493 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
494 ecam_reg, 0, ecam_size);
495 memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias);
496
497 mmio_alias = g_new0(MemoryRegion, 1);
498 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
499 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
500 mmio_reg, mmio_base, mmio_size);
501 memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias);
502
503 /* Map high MMIO space */
504 high_mmio_alias = g_new0(MemoryRegion, 1);
505 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high",
506 mmio_reg, high_mmio_base, high_mmio_size);
507 memory_region_add_subregion(get_system_memory(), high_mmio_base,
508 high_mmio_alias);
509
510 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base);
511
512 for (i = 0; i < GPEX_NUM_IRQS; i++) {
513 irq = qdev_get_gpio_in(plic, PCIE_IRQ + i);
514
515 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq);
516 gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i);
517 }
518
519 return dev;
520 }
521
522 static FWCfgState *create_fw_cfg(const MachineState *mc)
523 {
524 hwaddr base = virt_memmap[VIRT_FW_CFG].base;
525 hwaddr size = virt_memmap[VIRT_FW_CFG].size;
526 FWCfgState *fw_cfg;
527 char *nodename;
528
529 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16,
530 &address_space_memory);
531 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus);
532
533 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
534 qemu_fdt_add_subnode(mc->fdt, nodename);
535 qemu_fdt_setprop_string(mc->fdt, nodename,
536 "compatible", "qemu,fw-cfg-mmio");
537 qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg",
538 2, base, 2, size);
539 qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0);
540 g_free(nodename);
541 return fw_cfg;
542 }
543
544 static void virt_machine_init(MachineState *machine)
545 {
546 const MemMapEntry *memmap = virt_memmap;
547 RISCVVirtState *s = RISCV_VIRT_MACHINE(machine);
548 MemoryRegion *system_memory = get_system_memory();
549 MemoryRegion *main_mem = g_new(MemoryRegion, 1);
550 MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
551 char *plic_hart_config, *soc_name;
552 size_t plic_hart_config_len;
553 target_ulong start_addr = memmap[VIRT_DRAM].base;
554 target_ulong firmware_end_addr, kernel_start_addr;
555 uint32_t fdt_load_addr;
556 uint64_t kernel_entry;
557 DeviceState *mmio_plic, *virtio_plic, *pcie_plic;
558 int i, j, base_hartid, hart_count;
559
560 /* Check socket count limit */
561 if (VIRT_SOCKETS_MAX < riscv_socket_count(machine)) {
562 error_report("number of sockets/nodes should be less than %d",
563 VIRT_SOCKETS_MAX);
564 exit(1);
565 }
566
567 /* Initialize sockets */
568 mmio_plic = virtio_plic = pcie_plic = NULL;
569 for (i = 0; i < riscv_socket_count(machine); i++) {
570 if (!riscv_socket_check_hartids(machine, i)) {
571 error_report("discontinuous hartids in socket%d", i);
572 exit(1);
573 }
574
575 base_hartid = riscv_socket_first_hartid(machine, i);
576 if (base_hartid < 0) {
577 error_report("can't find hartid base for socket%d", i);
578 exit(1);
579 }
580
581 hart_count = riscv_socket_hart_count(machine, i);
582 if (hart_count < 0) {
583 error_report("can't find hart count for socket%d", i);
584 exit(1);
585 }
586
587 soc_name = g_strdup_printf("soc%d", i);
588 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i],
589 TYPE_RISCV_HART_ARRAY);
590 g_free(soc_name);
591 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type",
592 machine->cpu_type, &error_abort);
593 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base",
594 base_hartid, &error_abort);
595 object_property_set_int(OBJECT(&s->soc[i]), "num-harts",
596 hart_count, &error_abort);
597 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort);
598
599 /* Per-socket CLINT */
600 sifive_clint_create(
601 memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size,
602 memmap[VIRT_CLINT].size, base_hartid, hart_count,
603 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
604 SIFIVE_CLINT_TIMEBASE_FREQ, true);
605
606 /* Per-socket PLIC hart topology configuration string */
607 plic_hart_config_len =
608 (strlen(VIRT_PLIC_HART_CONFIG) + 1) * hart_count;
609 plic_hart_config = g_malloc0(plic_hart_config_len);
610 for (j = 0; j < hart_count; j++) {
611 if (j != 0) {
612 strncat(plic_hart_config, ",", plic_hart_config_len);
613 }
614 strncat(plic_hart_config, VIRT_PLIC_HART_CONFIG,
615 plic_hart_config_len);
616 plic_hart_config_len -= (strlen(VIRT_PLIC_HART_CONFIG) + 1);
617 }
618
619 /* Per-socket PLIC */
620 s->plic[i] = sifive_plic_create(
621 memmap[VIRT_PLIC].base + i * memmap[VIRT_PLIC].size,
622 plic_hart_config, base_hartid,
623 VIRT_PLIC_NUM_SOURCES,
624 VIRT_PLIC_NUM_PRIORITIES,
625 VIRT_PLIC_PRIORITY_BASE,
626 VIRT_PLIC_PENDING_BASE,
627 VIRT_PLIC_ENABLE_BASE,
628 VIRT_PLIC_ENABLE_STRIDE,
629 VIRT_PLIC_CONTEXT_BASE,
630 VIRT_PLIC_CONTEXT_STRIDE,
631 memmap[VIRT_PLIC].size);
632 g_free(plic_hart_config);
633
634 /* Try to use different PLIC instance based device type */
635 if (i == 0) {
636 mmio_plic = s->plic[i];
637 virtio_plic = s->plic[i];
638 pcie_plic = s->plic[i];
639 }
640 if (i == 1) {
641 virtio_plic = s->plic[i];
642 pcie_plic = s->plic[i];
643 }
644 if (i == 2) {
645 pcie_plic = s->plic[i];
646 }
647 }
648
649 if (riscv_is_32bit(&s->soc[0])) {
650 #if HOST_LONG_BITS == 64
651 /* limit RAM size in a 32-bit system */
652 if (machine->ram_size > 10 * GiB) {
653 machine->ram_size = 10 * GiB;
654 error_report("Limiting RAM size to 10 GiB");
655 }
656 #endif
657 virt_high_pcie_memmap.base = VIRT32_HIGH_PCIE_MMIO_BASE;
658 virt_high_pcie_memmap.size = VIRT32_HIGH_PCIE_MMIO_SIZE;
659 } else {
660 virt_high_pcie_memmap.size = VIRT64_HIGH_PCIE_MMIO_SIZE;
661 virt_high_pcie_memmap.base = memmap[VIRT_DRAM].base + machine->ram_size;
662 virt_high_pcie_memmap.base =
663 ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size);
664 }
665
666 /* register system main memory (actual RAM) */
667 memory_region_init_ram(main_mem, NULL, "riscv_virt_board.ram",
668 machine->ram_size, &error_fatal);
669 memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base,
670 main_mem);
671
672 /* create device tree */
673 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
674 riscv_is_32bit(&s->soc[0]));
675
676 /* boot rom */
677 memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom",
678 memmap[VIRT_MROM].size, &error_fatal);
679 memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base,
680 mask_rom);
681
682 if (riscv_is_32bit(&s->soc[0])) {
683 firmware_end_addr = riscv_find_and_load_firmware(machine,
684 RISCV32_BIOS_BIN, start_addr, NULL);
685 } else {
686 firmware_end_addr = riscv_find_and_load_firmware(machine,
687 RISCV64_BIOS_BIN, start_addr, NULL);
688 }
689
690 if (machine->kernel_filename) {
691 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
692 firmware_end_addr);
693
694 kernel_entry = riscv_load_kernel(machine->kernel_filename,
695 kernel_start_addr, NULL);
696
697 if (machine->initrd_filename) {
698 hwaddr start;
699 hwaddr end = riscv_load_initrd(machine->initrd_filename,
700 machine->ram_size, kernel_entry,
701 &start);
702 qemu_fdt_setprop_cell(machine->fdt, "/chosen",
703 "linux,initrd-start", start);
704 qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end",
705 end);
706 }
707 } else {
708 /*
709 * If dynamic firmware is used, it doesn't know where is the next mode
710 * if kernel argument is not set.
711 */
712 kernel_entry = 0;
713 }
714
715 if (drive_get(IF_PFLASH, 0, 0)) {
716 /*
717 * Pflash was supplied, let's overwrite the address we jump to after
718 * reset to the base of the flash.
719 */
720 start_addr = virt_memmap[VIRT_FLASH].base;
721 }
722
723 /*
724 * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the device
725 * tree cannot be altered and we get FDT_ERR_NOSPACE.
726 */
727 s->fw_cfg = create_fw_cfg(machine);
728 rom_set_fw(s->fw_cfg);
729
730 /* Compute the fdt load address in dram */
731 fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
732 machine->ram_size, machine->fdt);
733 /* load the reset vector */
734 riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr,
735 virt_memmap[VIRT_MROM].base,
736 virt_memmap[VIRT_MROM].size, kernel_entry,
737 fdt_load_addr, machine->fdt);
738
739 /* SiFive Test MMIO device */
740 sifive_test_create(memmap[VIRT_TEST].base);
741
742 /* VirtIO MMIO devices */
743 for (i = 0; i < VIRTIO_COUNT; i++) {
744 sysbus_create_simple("virtio-mmio",
745 memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
746 qdev_get_gpio_in(DEVICE(virtio_plic), VIRTIO_IRQ + i));
747 }
748
749 gpex_pcie_init(system_memory,
750 memmap[VIRT_PCIE_ECAM].base,
751 memmap[VIRT_PCIE_ECAM].size,
752 memmap[VIRT_PCIE_MMIO].base,
753 memmap[VIRT_PCIE_MMIO].size,
754 virt_high_pcie_memmap.base,
755 virt_high_pcie_memmap.size,
756 memmap[VIRT_PCIE_PIO].base,
757 DEVICE(pcie_plic));
758
759 serial_mm_init(system_memory, memmap[VIRT_UART0].base,
760 0, qdev_get_gpio_in(DEVICE(mmio_plic), UART0_IRQ), 399193,
761 serial_hd(0), DEVICE_LITTLE_ENDIAN);
762
763 sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base,
764 qdev_get_gpio_in(DEVICE(mmio_plic), RTC_IRQ));
765
766 virt_flash_create(s);
767
768 for (i = 0; i < ARRAY_SIZE(s->flash); i++) {
769 /* Map legacy -drive if=pflash to machine properties */
770 pflash_cfi01_legacy_drive(s->flash[i],
771 drive_get(IF_PFLASH, 0, i));
772 }
773 virt_flash_map(s, system_memory);
774 }
775
776 static void virt_machine_instance_init(Object *obj)
777 {
778 }
779
780 static void virt_machine_class_init(ObjectClass *oc, void *data)
781 {
782 MachineClass *mc = MACHINE_CLASS(oc);
783
784 mc->desc = "RISC-V VirtIO board";
785 mc->init = virt_machine_init;
786 mc->max_cpus = VIRT_CPUS_MAX;
787 mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
788 mc->pci_allow_0_address = true;
789 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;
790 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
791 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
792 mc->numa_mem_supported = true;
793
794 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
795 }
796
797 static const TypeInfo virt_machine_typeinfo = {
798 .name = MACHINE_TYPE_NAME("virt"),
799 .parent = TYPE_MACHINE,
800 .class_init = virt_machine_class_init,
801 .instance_init = virt_machine_instance_init,
802 .instance_size = sizeof(RISCVVirtState),
803 };
804
805 static void virt_machine_init_register_types(void)
806 {
807 type_register_static(&virt_machine_typeinfo);
808 }
809
810 type_init(virt_machine_init_register_types)