s390x/pci: use a PCI Group structure
[qemu.git] / hw / s390x / s390-pci-bus.c
1 /*
2 * s390 PCI BUS
3 *
4 * Copyright 2014 IBM Corp.
5 * Author(s): Frank Blaschka <frank.blaschka@de.ibm.com>
6 * Hong Bo Li <lihbbj@cn.ibm.com>
7 * Yi Min Zhao <zyimin@cn.ibm.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2 or (at
10 * your option) any later version. See the COPYING file in the top-level
11 * directory.
12 */
13
14 #include "qemu/osdep.h"
15 #include "qapi/error.h"
16 #include "qapi/visitor.h"
17 #include "cpu.h"
18 #include "hw/s390x/s390-pci-bus.h"
19 #include "hw/s390x/s390-pci-inst.h"
20 #include "hw/s390x/s390-pci-vfio.h"
21 #include "hw/pci/pci_bus.h"
22 #include "hw/qdev-properties.h"
23 #include "hw/pci/pci_bridge.h"
24 #include "hw/pci/msi.h"
25 #include "qemu/error-report.h"
26 #include "qemu/module.h"
27
28 #ifndef DEBUG_S390PCI_BUS
29 #define DEBUG_S390PCI_BUS 0
30 #endif
31
32 #define DPRINTF(fmt, ...) \
33 do { \
34 if (DEBUG_S390PCI_BUS) { \
35 fprintf(stderr, "S390pci-bus: " fmt, ## __VA_ARGS__); \
36 } \
37 } while (0)
38
39 S390pciState *s390_get_phb(void)
40 {
41 static S390pciState *phb;
42
43 if (!phb) {
44 phb = S390_PCI_HOST_BRIDGE(
45 object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE, NULL));
46 assert(phb != NULL);
47 }
48
49 return phb;
50 }
51
52 int pci_chsc_sei_nt2_get_event(void *res)
53 {
54 ChscSeiNt2Res *nt2_res = (ChscSeiNt2Res *)res;
55 PciCcdfAvail *accdf;
56 PciCcdfErr *eccdf;
57 int rc = 1;
58 SeiContainer *sei_cont;
59 S390pciState *s = s390_get_phb();
60
61 sei_cont = QTAILQ_FIRST(&s->pending_sei);
62 if (sei_cont) {
63 QTAILQ_REMOVE(&s->pending_sei, sei_cont, link);
64 nt2_res->nt = 2;
65 nt2_res->cc = sei_cont->cc;
66 nt2_res->length = cpu_to_be16(sizeof(ChscSeiNt2Res));
67 switch (sei_cont->cc) {
68 case 1: /* error event */
69 eccdf = (PciCcdfErr *)nt2_res->ccdf;
70 eccdf->fid = cpu_to_be32(sei_cont->fid);
71 eccdf->fh = cpu_to_be32(sei_cont->fh);
72 eccdf->e = cpu_to_be32(sei_cont->e);
73 eccdf->faddr = cpu_to_be64(sei_cont->faddr);
74 eccdf->pec = cpu_to_be16(sei_cont->pec);
75 break;
76 case 2: /* availability event */
77 accdf = (PciCcdfAvail *)nt2_res->ccdf;
78 accdf->fid = cpu_to_be32(sei_cont->fid);
79 accdf->fh = cpu_to_be32(sei_cont->fh);
80 accdf->pec = cpu_to_be16(sei_cont->pec);
81 break;
82 default:
83 abort();
84 }
85 g_free(sei_cont);
86 rc = 0;
87 }
88
89 return rc;
90 }
91
92 int pci_chsc_sei_nt2_have_event(void)
93 {
94 S390pciState *s = s390_get_phb();
95
96 return !QTAILQ_EMPTY(&s->pending_sei);
97 }
98
99 S390PCIBusDevice *s390_pci_find_next_avail_dev(S390pciState *s,
100 S390PCIBusDevice *pbdev)
101 {
102 S390PCIBusDevice *ret = pbdev ? QTAILQ_NEXT(pbdev, link) :
103 QTAILQ_FIRST(&s->zpci_devs);
104
105 while (ret && ret->state == ZPCI_FS_RESERVED) {
106 ret = QTAILQ_NEXT(ret, link);
107 }
108
109 return ret;
110 }
111
112 S390PCIBusDevice *s390_pci_find_dev_by_fid(S390pciState *s, uint32_t fid)
113 {
114 S390PCIBusDevice *pbdev;
115
116 QTAILQ_FOREACH(pbdev, &s->zpci_devs, link) {
117 if (pbdev->fid == fid) {
118 return pbdev;
119 }
120 }
121
122 return NULL;
123 }
124
125 void s390_pci_sclp_configure(SCCB *sccb)
126 {
127 IoaCfgSccb *psccb = (IoaCfgSccb *)sccb;
128 S390PCIBusDevice *pbdev = s390_pci_find_dev_by_fid(s390_get_phb(),
129 be32_to_cpu(psccb->aid));
130 uint16_t rc;
131
132 if (!pbdev) {
133 DPRINTF("sclp config no dev found\n");
134 rc = SCLP_RC_ADAPTER_ID_NOT_RECOGNIZED;
135 goto out;
136 }
137
138 switch (pbdev->state) {
139 case ZPCI_FS_RESERVED:
140 rc = SCLP_RC_ADAPTER_IN_RESERVED_STATE;
141 break;
142 case ZPCI_FS_STANDBY:
143 pbdev->state = ZPCI_FS_DISABLED;
144 rc = SCLP_RC_NORMAL_COMPLETION;
145 break;
146 default:
147 rc = SCLP_RC_NO_ACTION_REQUIRED;
148 }
149 out:
150 psccb->header.response_code = cpu_to_be16(rc);
151 }
152
153 static void s390_pci_perform_unplug(S390PCIBusDevice *pbdev)
154 {
155 HotplugHandler *hotplug_ctrl;
156
157 /* Unplug the PCI device */
158 if (pbdev->pdev) {
159 DeviceState *pdev = DEVICE(pbdev->pdev);
160
161 hotplug_ctrl = qdev_get_hotplug_handler(pdev);
162 hotplug_handler_unplug(hotplug_ctrl, pdev, &error_abort);
163 object_unparent(OBJECT(pdev));
164 }
165
166 /* Unplug the zPCI device */
167 hotplug_ctrl = qdev_get_hotplug_handler(DEVICE(pbdev));
168 hotplug_handler_unplug(hotplug_ctrl, DEVICE(pbdev), &error_abort);
169 object_unparent(OBJECT(pbdev));
170 }
171
172 void s390_pci_sclp_deconfigure(SCCB *sccb)
173 {
174 IoaCfgSccb *psccb = (IoaCfgSccb *)sccb;
175 S390PCIBusDevice *pbdev = s390_pci_find_dev_by_fid(s390_get_phb(),
176 be32_to_cpu(psccb->aid));
177 uint16_t rc;
178
179 if (!pbdev) {
180 DPRINTF("sclp deconfig no dev found\n");
181 rc = SCLP_RC_ADAPTER_ID_NOT_RECOGNIZED;
182 goto out;
183 }
184
185 switch (pbdev->state) {
186 case ZPCI_FS_RESERVED:
187 rc = SCLP_RC_ADAPTER_IN_RESERVED_STATE;
188 break;
189 case ZPCI_FS_STANDBY:
190 rc = SCLP_RC_NO_ACTION_REQUIRED;
191 break;
192 default:
193 if (pbdev->summary_ind) {
194 pci_dereg_irqs(pbdev);
195 }
196 if (pbdev->iommu->enabled) {
197 pci_dereg_ioat(pbdev->iommu);
198 }
199 pbdev->state = ZPCI_FS_STANDBY;
200 rc = SCLP_RC_NORMAL_COMPLETION;
201
202 if (pbdev->unplug_requested) {
203 s390_pci_perform_unplug(pbdev);
204 }
205 }
206 out:
207 psccb->header.response_code = cpu_to_be16(rc);
208 }
209
210 static S390PCIBusDevice *s390_pci_find_dev_by_uid(S390pciState *s, uint16_t uid)
211 {
212 S390PCIBusDevice *pbdev;
213
214 QTAILQ_FOREACH(pbdev, &s->zpci_devs, link) {
215 if (pbdev->uid == uid) {
216 return pbdev;
217 }
218 }
219
220 return NULL;
221 }
222
223 S390PCIBusDevice *s390_pci_find_dev_by_target(S390pciState *s,
224 const char *target)
225 {
226 S390PCIBusDevice *pbdev;
227
228 if (!target) {
229 return NULL;
230 }
231
232 QTAILQ_FOREACH(pbdev, &s->zpci_devs, link) {
233 if (!strcmp(pbdev->target, target)) {
234 return pbdev;
235 }
236 }
237
238 return NULL;
239 }
240
241 static S390PCIBusDevice *s390_pci_find_dev_by_pci(S390pciState *s,
242 PCIDevice *pci_dev)
243 {
244 S390PCIBusDevice *pbdev;
245
246 if (!pci_dev) {
247 return NULL;
248 }
249
250 QTAILQ_FOREACH(pbdev, &s->zpci_devs, link) {
251 if (pbdev->pdev == pci_dev) {
252 return pbdev;
253 }
254 }
255
256 return NULL;
257 }
258
259 S390PCIBusDevice *s390_pci_find_dev_by_idx(S390pciState *s, uint32_t idx)
260 {
261 return g_hash_table_lookup(s->zpci_table, &idx);
262 }
263
264 S390PCIBusDevice *s390_pci_find_dev_by_fh(S390pciState *s, uint32_t fh)
265 {
266 uint32_t idx = FH_MASK_INDEX & fh;
267 S390PCIBusDevice *pbdev = s390_pci_find_dev_by_idx(s, idx);
268
269 if (pbdev && pbdev->fh == fh) {
270 return pbdev;
271 }
272
273 return NULL;
274 }
275
276 static void s390_pci_generate_event(uint8_t cc, uint16_t pec, uint32_t fh,
277 uint32_t fid, uint64_t faddr, uint32_t e)
278 {
279 SeiContainer *sei_cont;
280 S390pciState *s = s390_get_phb();
281
282 sei_cont = g_new0(SeiContainer, 1);
283 sei_cont->fh = fh;
284 sei_cont->fid = fid;
285 sei_cont->cc = cc;
286 sei_cont->pec = pec;
287 sei_cont->faddr = faddr;
288 sei_cont->e = e;
289
290 QTAILQ_INSERT_TAIL(&s->pending_sei, sei_cont, link);
291 css_generate_css_crws(0);
292 }
293
294 static void s390_pci_generate_plug_event(uint16_t pec, uint32_t fh,
295 uint32_t fid)
296 {
297 s390_pci_generate_event(2, pec, fh, fid, 0, 0);
298 }
299
300 void s390_pci_generate_error_event(uint16_t pec, uint32_t fh, uint32_t fid,
301 uint64_t faddr, uint32_t e)
302 {
303 s390_pci_generate_event(1, pec, fh, fid, faddr, e);
304 }
305
306 static void s390_pci_set_irq(void *opaque, int irq, int level)
307 {
308 /* nothing to do */
309 }
310
311 static int s390_pci_map_irq(PCIDevice *pci_dev, int irq_num)
312 {
313 /* nothing to do */
314 return 0;
315 }
316
317 static uint64_t s390_pci_get_table_origin(uint64_t iota)
318 {
319 return iota & ~ZPCI_IOTA_RTTO_FLAG;
320 }
321
322 static unsigned int calc_rtx(dma_addr_t ptr)
323 {
324 return ((unsigned long) ptr >> ZPCI_RT_SHIFT) & ZPCI_INDEX_MASK;
325 }
326
327 static unsigned int calc_sx(dma_addr_t ptr)
328 {
329 return ((unsigned long) ptr >> ZPCI_ST_SHIFT) & ZPCI_INDEX_MASK;
330 }
331
332 static unsigned int calc_px(dma_addr_t ptr)
333 {
334 return ((unsigned long) ptr >> PAGE_SHIFT) & ZPCI_PT_MASK;
335 }
336
337 static uint64_t get_rt_sto(uint64_t entry)
338 {
339 return ((entry & ZPCI_TABLE_TYPE_MASK) == ZPCI_TABLE_TYPE_RTX)
340 ? (entry & ZPCI_RTE_ADDR_MASK)
341 : 0;
342 }
343
344 static uint64_t get_st_pto(uint64_t entry)
345 {
346 return ((entry & ZPCI_TABLE_TYPE_MASK) == ZPCI_TABLE_TYPE_SX)
347 ? (entry & ZPCI_STE_ADDR_MASK)
348 : 0;
349 }
350
351 static bool rt_entry_isvalid(uint64_t entry)
352 {
353 return (entry & ZPCI_TABLE_VALID_MASK) == ZPCI_TABLE_VALID;
354 }
355
356 static bool pt_entry_isvalid(uint64_t entry)
357 {
358 return (entry & ZPCI_PTE_VALID_MASK) == ZPCI_PTE_VALID;
359 }
360
361 static bool entry_isprotected(uint64_t entry)
362 {
363 return (entry & ZPCI_TABLE_PROT_MASK) == ZPCI_TABLE_PROTECTED;
364 }
365
366 /* ett is expected table type, -1 page table, 0 segment table, 1 region table */
367 static uint64_t get_table_index(uint64_t iova, int8_t ett)
368 {
369 switch (ett) {
370 case ZPCI_ETT_PT:
371 return calc_px(iova);
372 case ZPCI_ETT_ST:
373 return calc_sx(iova);
374 case ZPCI_ETT_RT:
375 return calc_rtx(iova);
376 }
377
378 return -1;
379 }
380
381 static bool entry_isvalid(uint64_t entry, int8_t ett)
382 {
383 switch (ett) {
384 case ZPCI_ETT_PT:
385 return pt_entry_isvalid(entry);
386 case ZPCI_ETT_ST:
387 case ZPCI_ETT_RT:
388 return rt_entry_isvalid(entry);
389 }
390
391 return false;
392 }
393
394 /* Return true if address translation is done */
395 static bool translate_iscomplete(uint64_t entry, int8_t ett)
396 {
397 switch (ett) {
398 case 0:
399 return (entry & ZPCI_TABLE_FC) ? true : false;
400 case 1:
401 return false;
402 }
403
404 return true;
405 }
406
407 static uint64_t get_frame_size(int8_t ett)
408 {
409 switch (ett) {
410 case ZPCI_ETT_PT:
411 return 1ULL << 12;
412 case ZPCI_ETT_ST:
413 return 1ULL << 20;
414 case ZPCI_ETT_RT:
415 return 1ULL << 31;
416 }
417
418 return 0;
419 }
420
421 static uint64_t get_next_table_origin(uint64_t entry, int8_t ett)
422 {
423 switch (ett) {
424 case ZPCI_ETT_PT:
425 return entry & ZPCI_PTE_ADDR_MASK;
426 case ZPCI_ETT_ST:
427 return get_st_pto(entry);
428 case ZPCI_ETT_RT:
429 return get_rt_sto(entry);
430 }
431
432 return 0;
433 }
434
435 /**
436 * table_translate: do translation within one table and return the following
437 * table origin
438 *
439 * @entry: the entry being translated, the result is stored in this.
440 * @to: the address of table origin.
441 * @ett: expected table type, 1 region table, 0 segment table and -1 page table.
442 * @error: error code
443 */
444 static uint64_t table_translate(S390IOTLBEntry *entry, uint64_t to, int8_t ett,
445 uint16_t *error)
446 {
447 uint64_t tx, te, nto = 0;
448 uint16_t err = 0;
449
450 tx = get_table_index(entry->iova, ett);
451 te = address_space_ldq(&address_space_memory, to + tx * sizeof(uint64_t),
452 MEMTXATTRS_UNSPECIFIED, NULL);
453
454 if (!te) {
455 err = ERR_EVENT_INVALTE;
456 goto out;
457 }
458
459 if (!entry_isvalid(te, ett)) {
460 entry->perm &= IOMMU_NONE;
461 goto out;
462 }
463
464 if (ett == ZPCI_ETT_RT && ((te & ZPCI_TABLE_LEN_RTX) != ZPCI_TABLE_LEN_RTX
465 || te & ZPCI_TABLE_OFFSET_MASK)) {
466 err = ERR_EVENT_INVALTL;
467 goto out;
468 }
469
470 nto = get_next_table_origin(te, ett);
471 if (!nto) {
472 err = ERR_EVENT_TT;
473 goto out;
474 }
475
476 if (entry_isprotected(te)) {
477 entry->perm &= IOMMU_RO;
478 } else {
479 entry->perm &= IOMMU_RW;
480 }
481
482 if (translate_iscomplete(te, ett)) {
483 switch (ett) {
484 case ZPCI_ETT_PT:
485 entry->translated_addr = te & ZPCI_PTE_ADDR_MASK;
486 break;
487 case ZPCI_ETT_ST:
488 entry->translated_addr = (te & ZPCI_SFAA_MASK) |
489 (entry->iova & ~ZPCI_SFAA_MASK);
490 break;
491 }
492 nto = 0;
493 }
494 out:
495 if (err) {
496 entry->perm = IOMMU_NONE;
497 *error = err;
498 }
499 entry->len = get_frame_size(ett);
500 return nto;
501 }
502
503 uint16_t s390_guest_io_table_walk(uint64_t g_iota, hwaddr addr,
504 S390IOTLBEntry *entry)
505 {
506 uint64_t to = s390_pci_get_table_origin(g_iota);
507 int8_t ett = 1;
508 uint16_t error = 0;
509
510 entry->iova = addr & PAGE_MASK;
511 entry->translated_addr = 0;
512 entry->perm = IOMMU_RW;
513
514 if (entry_isprotected(g_iota)) {
515 entry->perm &= IOMMU_RO;
516 }
517
518 while (to) {
519 to = table_translate(entry, to, ett--, &error);
520 }
521
522 return error;
523 }
524
525 static IOMMUTLBEntry s390_translate_iommu(IOMMUMemoryRegion *mr, hwaddr addr,
526 IOMMUAccessFlags flag, int iommu_idx)
527 {
528 S390PCIIOMMU *iommu = container_of(mr, S390PCIIOMMU, iommu_mr);
529 S390IOTLBEntry *entry;
530 uint64_t iova = addr & PAGE_MASK;
531 uint16_t error = 0;
532 IOMMUTLBEntry ret = {
533 .target_as = &address_space_memory,
534 .iova = 0,
535 .translated_addr = 0,
536 .addr_mask = ~(hwaddr)0,
537 .perm = IOMMU_NONE,
538 };
539
540 switch (iommu->pbdev->state) {
541 case ZPCI_FS_ENABLED:
542 case ZPCI_FS_BLOCKED:
543 if (!iommu->enabled) {
544 return ret;
545 }
546 break;
547 default:
548 return ret;
549 }
550
551 DPRINTF("iommu trans addr 0x%" PRIx64 "\n", addr);
552
553 if (addr < iommu->pba || addr > iommu->pal) {
554 error = ERR_EVENT_OORANGE;
555 goto err;
556 }
557
558 entry = g_hash_table_lookup(iommu->iotlb, &iova);
559 if (entry) {
560 ret.iova = entry->iova;
561 ret.translated_addr = entry->translated_addr;
562 ret.addr_mask = entry->len - 1;
563 ret.perm = entry->perm;
564 } else {
565 ret.iova = iova;
566 ret.addr_mask = ~PAGE_MASK;
567 ret.perm = IOMMU_NONE;
568 }
569
570 if (flag != IOMMU_NONE && !(flag & ret.perm)) {
571 error = ERR_EVENT_TPROTE;
572 }
573 err:
574 if (error) {
575 iommu->pbdev->state = ZPCI_FS_ERROR;
576 s390_pci_generate_error_event(error, iommu->pbdev->fh,
577 iommu->pbdev->fid, addr, 0);
578 }
579 return ret;
580 }
581
582 static void s390_pci_iommu_replay(IOMMUMemoryRegion *iommu,
583 IOMMUNotifier *notifier)
584 {
585 /* It's impossible to plug a pci device on s390x that already has iommu
586 * mappings which need to be replayed, that is due to the "one iommu per
587 * zpci device" construct. But when we support migration of vfio-pci
588 * devices in future, we need to revisit this.
589 */
590 return;
591 }
592
593 static S390PCIIOMMU *s390_pci_get_iommu(S390pciState *s, PCIBus *bus,
594 int devfn)
595 {
596 uint64_t key = (uintptr_t)bus;
597 S390PCIIOMMUTable *table = g_hash_table_lookup(s->iommu_table, &key);
598 S390PCIIOMMU *iommu;
599
600 if (!table) {
601 table = g_new0(S390PCIIOMMUTable, 1);
602 table->key = key;
603 g_hash_table_insert(s->iommu_table, &table->key, table);
604 }
605
606 iommu = table->iommu[PCI_SLOT(devfn)];
607 if (!iommu) {
608 iommu = S390_PCI_IOMMU(object_new(TYPE_S390_PCI_IOMMU));
609
610 char *mr_name = g_strdup_printf("iommu-root-%02x:%02x.%01x",
611 pci_bus_num(bus),
612 PCI_SLOT(devfn),
613 PCI_FUNC(devfn));
614 char *as_name = g_strdup_printf("iommu-pci-%02x:%02x.%01x",
615 pci_bus_num(bus),
616 PCI_SLOT(devfn),
617 PCI_FUNC(devfn));
618 memory_region_init(&iommu->mr, OBJECT(iommu), mr_name, UINT64_MAX);
619 address_space_init(&iommu->as, &iommu->mr, as_name);
620 iommu->iotlb = g_hash_table_new_full(g_int64_hash, g_int64_equal,
621 NULL, g_free);
622 table->iommu[PCI_SLOT(devfn)] = iommu;
623
624 g_free(mr_name);
625 g_free(as_name);
626 }
627
628 return iommu;
629 }
630
631 static AddressSpace *s390_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn)
632 {
633 S390pciState *s = opaque;
634 S390PCIIOMMU *iommu = s390_pci_get_iommu(s, bus, devfn);
635
636 return &iommu->as;
637 }
638
639 static uint8_t set_ind_atomic(uint64_t ind_loc, uint8_t to_be_set)
640 {
641 uint8_t expected, actual;
642 hwaddr len = 1;
643 /* avoid multiple fetches */
644 uint8_t volatile *ind_addr;
645
646 ind_addr = cpu_physical_memory_map(ind_loc, &len, true);
647 if (!ind_addr) {
648 s390_pci_generate_error_event(ERR_EVENT_AIRERR, 0, 0, 0, 0);
649 return -1;
650 }
651 actual = *ind_addr;
652 do {
653 expected = actual;
654 actual = qatomic_cmpxchg(ind_addr, expected, expected | to_be_set);
655 } while (actual != expected);
656 cpu_physical_memory_unmap((void *)ind_addr, len, 1, len);
657
658 return actual;
659 }
660
661 static void s390_msi_ctrl_write(void *opaque, hwaddr addr, uint64_t data,
662 unsigned int size)
663 {
664 S390PCIBusDevice *pbdev = opaque;
665 uint32_t vec = data & ZPCI_MSI_VEC_MASK;
666 uint64_t ind_bit;
667 uint32_t sum_bit;
668
669 assert(pbdev);
670 DPRINTF("write_msix data 0x%" PRIx64 " idx %d vec 0x%x\n", data,
671 pbdev->idx, vec);
672
673 if (pbdev->state != ZPCI_FS_ENABLED) {
674 return;
675 }
676
677 ind_bit = pbdev->routes.adapter.ind_offset;
678 sum_bit = pbdev->routes.adapter.summary_offset;
679
680 set_ind_atomic(pbdev->routes.adapter.ind_addr + (ind_bit + vec) / 8,
681 0x80 >> ((ind_bit + vec) % 8));
682 if (!set_ind_atomic(pbdev->routes.adapter.summary_addr + sum_bit / 8,
683 0x80 >> (sum_bit % 8))) {
684 css_adapter_interrupt(CSS_IO_ADAPTER_PCI, pbdev->isc);
685 }
686 }
687
688 static uint64_t s390_msi_ctrl_read(void *opaque, hwaddr addr, unsigned size)
689 {
690 return 0xffffffff;
691 }
692
693 static const MemoryRegionOps s390_msi_ctrl_ops = {
694 .write = s390_msi_ctrl_write,
695 .read = s390_msi_ctrl_read,
696 .endianness = DEVICE_LITTLE_ENDIAN,
697 };
698
699 void s390_pci_iommu_enable(S390PCIIOMMU *iommu)
700 {
701 /*
702 * The iommu region is initialized against a 0-mapped address space,
703 * so the smallest IOMMU region we can define runs from 0 to the end
704 * of the PCI address space.
705 */
706 char *name = g_strdup_printf("iommu-s390-%04x", iommu->pbdev->uid);
707 memory_region_init_iommu(&iommu->iommu_mr, sizeof(iommu->iommu_mr),
708 TYPE_S390_IOMMU_MEMORY_REGION, OBJECT(&iommu->mr),
709 name, iommu->pal + 1);
710 iommu->enabled = true;
711 memory_region_add_subregion(&iommu->mr, 0, MEMORY_REGION(&iommu->iommu_mr));
712 g_free(name);
713 }
714
715 void s390_pci_iommu_disable(S390PCIIOMMU *iommu)
716 {
717 iommu->enabled = false;
718 g_hash_table_remove_all(iommu->iotlb);
719 memory_region_del_subregion(&iommu->mr, MEMORY_REGION(&iommu->iommu_mr));
720 object_unparent(OBJECT(&iommu->iommu_mr));
721 }
722
723 static void s390_pci_iommu_free(S390pciState *s, PCIBus *bus, int32_t devfn)
724 {
725 uint64_t key = (uintptr_t)bus;
726 S390PCIIOMMUTable *table = g_hash_table_lookup(s->iommu_table, &key);
727 S390PCIIOMMU *iommu = table ? table->iommu[PCI_SLOT(devfn)] : NULL;
728
729 if (!table || !iommu) {
730 return;
731 }
732
733 table->iommu[PCI_SLOT(devfn)] = NULL;
734 g_hash_table_destroy(iommu->iotlb);
735 address_space_destroy(&iommu->as);
736 object_unparent(OBJECT(&iommu->mr));
737 object_unparent(OBJECT(iommu));
738 object_unref(OBJECT(iommu));
739 }
740
741 static S390PCIGroup *s390_group_create(int id)
742 {
743 S390PCIGroup *group;
744 S390pciState *s = s390_get_phb();
745
746 group = g_new0(S390PCIGroup, 1);
747 group->id = id;
748 QTAILQ_INSERT_TAIL(&s->zpci_groups, group, link);
749 return group;
750 }
751
752 S390PCIGroup *s390_group_find(int id)
753 {
754 S390PCIGroup *group;
755 S390pciState *s = s390_get_phb();
756
757 QTAILQ_FOREACH(group, &s->zpci_groups, link) {
758 if (group->id == id) {
759 return group;
760 }
761 }
762 return NULL;
763 }
764
765 static void s390_pci_init_default_group(void)
766 {
767 S390PCIGroup *group;
768 ClpRspQueryPciGrp *resgrp;
769
770 group = s390_group_create(ZPCI_DEFAULT_FN_GRP);
771 resgrp = &group->zpci_group;
772 resgrp->fr = 1;
773 stq_p(&resgrp->dasm, 0);
774 stq_p(&resgrp->msia, ZPCI_MSI_ADDR);
775 stw_p(&resgrp->mui, DEFAULT_MUI);
776 stw_p(&resgrp->i, 128);
777 stw_p(&resgrp->maxstbl, 128);
778 resgrp->version = 0;
779 }
780
781 static void s390_pcihost_realize(DeviceState *dev, Error **errp)
782 {
783 PCIBus *b;
784 BusState *bus;
785 PCIHostState *phb = PCI_HOST_BRIDGE(dev);
786 S390pciState *s = S390_PCI_HOST_BRIDGE(dev);
787
788 DPRINTF("host_init\n");
789
790 b = pci_register_root_bus(dev, NULL, s390_pci_set_irq, s390_pci_map_irq,
791 NULL, get_system_memory(), get_system_io(), 0,
792 64, TYPE_PCI_BUS);
793 pci_setup_iommu(b, s390_pci_dma_iommu, s);
794
795 bus = BUS(b);
796 qbus_set_hotplug_handler(bus, OBJECT(dev));
797 phb->bus = b;
798
799 s->bus = S390_PCI_BUS(qbus_create(TYPE_S390_PCI_BUS, dev, NULL));
800 qbus_set_hotplug_handler(BUS(s->bus), OBJECT(dev));
801
802 s->iommu_table = g_hash_table_new_full(g_int64_hash, g_int64_equal,
803 NULL, g_free);
804 s->zpci_table = g_hash_table_new_full(g_int_hash, g_int_equal, NULL, NULL);
805 s->bus_no = 0;
806 QTAILQ_INIT(&s->pending_sei);
807 QTAILQ_INIT(&s->zpci_devs);
808 QTAILQ_INIT(&s->zpci_dma_limit);
809 QTAILQ_INIT(&s->zpci_groups);
810
811 s390_pci_init_default_group();
812 css_register_io_adapters(CSS_IO_ADAPTER_PCI, true, false,
813 S390_ADAPTER_SUPPRESSIBLE, errp);
814 }
815
816 static int s390_pci_msix_init(S390PCIBusDevice *pbdev)
817 {
818 char *name;
819 uint8_t pos;
820 uint16_t ctrl;
821 uint32_t table, pba;
822
823 pos = pci_find_capability(pbdev->pdev, PCI_CAP_ID_MSIX);
824 if (!pos) {
825 return -1;
826 }
827
828 ctrl = pci_host_config_read_common(pbdev->pdev, pos + PCI_MSIX_FLAGS,
829 pci_config_size(pbdev->pdev), sizeof(ctrl));
830 table = pci_host_config_read_common(pbdev->pdev, pos + PCI_MSIX_TABLE,
831 pci_config_size(pbdev->pdev), sizeof(table));
832 pba = pci_host_config_read_common(pbdev->pdev, pos + PCI_MSIX_PBA,
833 pci_config_size(pbdev->pdev), sizeof(pba));
834
835 pbdev->msix.table_bar = table & PCI_MSIX_FLAGS_BIRMASK;
836 pbdev->msix.table_offset = table & ~PCI_MSIX_FLAGS_BIRMASK;
837 pbdev->msix.pba_bar = pba & PCI_MSIX_FLAGS_BIRMASK;
838 pbdev->msix.pba_offset = pba & ~PCI_MSIX_FLAGS_BIRMASK;
839 pbdev->msix.entries = (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
840
841 name = g_strdup_printf("msix-s390-%04x", pbdev->uid);
842 memory_region_init_io(&pbdev->msix_notify_mr, OBJECT(pbdev),
843 &s390_msi_ctrl_ops, pbdev, name, PAGE_SIZE);
844 memory_region_add_subregion(&pbdev->iommu->mr, ZPCI_MSI_ADDR,
845 &pbdev->msix_notify_mr);
846 g_free(name);
847
848 return 0;
849 }
850
851 static void s390_pci_msix_free(S390PCIBusDevice *pbdev)
852 {
853 memory_region_del_subregion(&pbdev->iommu->mr, &pbdev->msix_notify_mr);
854 object_unparent(OBJECT(&pbdev->msix_notify_mr));
855 }
856
857 static S390PCIBusDevice *s390_pci_device_new(S390pciState *s,
858 const char *target, Error **errp)
859 {
860 Error *local_err = NULL;
861 DeviceState *dev;
862
863 dev = qdev_try_new(TYPE_S390_PCI_DEVICE);
864 if (!dev) {
865 error_setg(errp, "zPCI device could not be created");
866 return NULL;
867 }
868
869 if (!object_property_set_str(OBJECT(dev), "target", target, &local_err)) {
870 object_unparent(OBJECT(dev));
871 error_propagate_prepend(errp, local_err,
872 "zPCI device could not be created: ");
873 return NULL;
874 }
875 if (!qdev_realize_and_unref(dev, BUS(s->bus), &local_err)) {
876 object_unparent(OBJECT(dev));
877 error_propagate_prepend(errp, local_err,
878 "zPCI device could not be created: ");
879 return NULL;
880 }
881
882 return S390_PCI_DEVICE(dev);
883 }
884
885 static bool s390_pci_alloc_idx(S390pciState *s, S390PCIBusDevice *pbdev)
886 {
887 uint32_t idx;
888
889 idx = s->next_idx;
890 while (s390_pci_find_dev_by_idx(s, idx)) {
891 idx = (idx + 1) & FH_MASK_INDEX;
892 if (idx == s->next_idx) {
893 return false;
894 }
895 }
896
897 pbdev->idx = idx;
898 return true;
899 }
900
901 static void s390_pcihost_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
902 Error **errp)
903 {
904 S390pciState *s = S390_PCI_HOST_BRIDGE(hotplug_dev);
905
906 if (!s390_has_feat(S390_FEAT_ZPCI)) {
907 warn_report("Plugging a PCI/zPCI device without the 'zpci' CPU "
908 "feature enabled; the guest will not be able to see/use "
909 "this device");
910 }
911
912 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
913 PCIDevice *pdev = PCI_DEVICE(dev);
914
915 if (pdev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
916 error_setg(errp, "multifunction not supported in s390");
917 return;
918 }
919 } else if (object_dynamic_cast(OBJECT(dev), TYPE_S390_PCI_DEVICE)) {
920 S390PCIBusDevice *pbdev = S390_PCI_DEVICE(dev);
921
922 if (!s390_pci_alloc_idx(s, pbdev)) {
923 error_setg(errp, "no slot for plugging zpci device");
924 return;
925 }
926 }
927 }
928
929 static void s390_pci_update_subordinate(PCIDevice *dev, uint32_t nr)
930 {
931 uint32_t old_nr;
932
933 pci_default_write_config(dev, PCI_SUBORDINATE_BUS, nr, 1);
934 while (!pci_bus_is_root(pci_get_bus(dev))) {
935 dev = pci_get_bus(dev)->parent_dev;
936
937 old_nr = pci_default_read_config(dev, PCI_SUBORDINATE_BUS, 1);
938 if (old_nr < nr) {
939 pci_default_write_config(dev, PCI_SUBORDINATE_BUS, nr, 1);
940 }
941 }
942 }
943
944 static void s390_pcihost_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
945 Error **errp)
946 {
947 S390pciState *s = S390_PCI_HOST_BRIDGE(hotplug_dev);
948 PCIDevice *pdev = NULL;
949 S390PCIBusDevice *pbdev = NULL;
950
951 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) {
952 PCIBridge *pb = PCI_BRIDGE(dev);
953
954 pdev = PCI_DEVICE(dev);
955 pci_bridge_map_irq(pb, dev->id, s390_pci_map_irq);
956 pci_setup_iommu(&pb->sec_bus, s390_pci_dma_iommu, s);
957
958 qbus_set_hotplug_handler(BUS(&pb->sec_bus), OBJECT(s));
959
960 if (dev->hotplugged) {
961 pci_default_write_config(pdev, PCI_PRIMARY_BUS,
962 pci_dev_bus_num(pdev), 1);
963 s->bus_no += 1;
964 pci_default_write_config(pdev, PCI_SECONDARY_BUS, s->bus_no, 1);
965
966 s390_pci_update_subordinate(pdev, s->bus_no);
967 }
968 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
969 pdev = PCI_DEVICE(dev);
970
971 if (!dev->id) {
972 /* In the case the PCI device does not define an id */
973 /* we generate one based on the PCI address */
974 dev->id = g_strdup_printf("auto_%02x:%02x.%01x",
975 pci_dev_bus_num(pdev),
976 PCI_SLOT(pdev->devfn),
977 PCI_FUNC(pdev->devfn));
978 }
979
980 pbdev = s390_pci_find_dev_by_target(s, dev->id);
981 if (!pbdev) {
982 pbdev = s390_pci_device_new(s, dev->id, errp);
983 if (!pbdev) {
984 return;
985 }
986 }
987
988 pbdev->pdev = pdev;
989 pbdev->iommu = s390_pci_get_iommu(s, pci_get_bus(pdev), pdev->devfn);
990 pbdev->iommu->pbdev = pbdev;
991 pbdev->state = ZPCI_FS_DISABLED;
992
993 if (object_dynamic_cast(OBJECT(dev), "vfio-pci")) {
994 pbdev->fh |= FH_SHM_VFIO;
995 pbdev->iommu->dma_limit = s390_pci_start_dma_count(s, pbdev);
996 } else {
997 pbdev->fh |= FH_SHM_EMUL;
998 }
999
1000 if (s390_pci_msix_init(pbdev)) {
1001 error_setg(errp, "MSI-X support is mandatory "
1002 "in the S390 architecture");
1003 return;
1004 }
1005
1006 if (dev->hotplugged) {
1007 s390_pci_generate_plug_event(HP_EVENT_TO_CONFIGURED ,
1008 pbdev->fh, pbdev->fid);
1009 }
1010 } else if (object_dynamic_cast(OBJECT(dev), TYPE_S390_PCI_DEVICE)) {
1011 pbdev = S390_PCI_DEVICE(dev);
1012
1013 /* the allocated idx is actually getting used */
1014 s->next_idx = (pbdev->idx + 1) & FH_MASK_INDEX;
1015 pbdev->fh = pbdev->idx;
1016 QTAILQ_INSERT_TAIL(&s->zpci_devs, pbdev, link);
1017 g_hash_table_insert(s->zpci_table, &pbdev->idx, pbdev);
1018 } else {
1019 g_assert_not_reached();
1020 }
1021 }
1022
1023 static void s390_pcihost_unplug(HotplugHandler *hotplug_dev, DeviceState *dev,
1024 Error **errp)
1025 {
1026 S390pciState *s = S390_PCI_HOST_BRIDGE(hotplug_dev);
1027 S390PCIBusDevice *pbdev = NULL;
1028
1029 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
1030 PCIDevice *pci_dev = PCI_DEVICE(dev);
1031 PCIBus *bus;
1032 int32_t devfn;
1033
1034 pbdev = s390_pci_find_dev_by_pci(s, PCI_DEVICE(dev));
1035 g_assert(pbdev);
1036
1037 s390_pci_generate_plug_event(HP_EVENT_STANDBY_TO_RESERVED,
1038 pbdev->fh, pbdev->fid);
1039 bus = pci_get_bus(pci_dev);
1040 devfn = pci_dev->devfn;
1041 qdev_unrealize(dev);
1042
1043 s390_pci_msix_free(pbdev);
1044 s390_pci_iommu_free(s, bus, devfn);
1045 pbdev->pdev = NULL;
1046 pbdev->state = ZPCI_FS_RESERVED;
1047 } else if (object_dynamic_cast(OBJECT(dev), TYPE_S390_PCI_DEVICE)) {
1048 pbdev = S390_PCI_DEVICE(dev);
1049 pbdev->fid = 0;
1050 QTAILQ_REMOVE(&s->zpci_devs, pbdev, link);
1051 g_hash_table_remove(s->zpci_table, &pbdev->idx);
1052 if (pbdev->iommu->dma_limit) {
1053 s390_pci_end_dma_count(s, pbdev->iommu->dma_limit);
1054 }
1055 qdev_unrealize(dev);
1056 }
1057 }
1058
1059 static void s390_pcihost_unplug_request(HotplugHandler *hotplug_dev,
1060 DeviceState *dev,
1061 Error **errp)
1062 {
1063 S390pciState *s = S390_PCI_HOST_BRIDGE(hotplug_dev);
1064 S390PCIBusDevice *pbdev;
1065
1066 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) {
1067 error_setg(errp, "PCI bridge hot unplug currently not supported");
1068 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
1069 /*
1070 * Redirect the unplug request to the zPCI device and remember that
1071 * we've checked the PCI device already (to prevent endless recursion).
1072 */
1073 pbdev = s390_pci_find_dev_by_pci(s, PCI_DEVICE(dev));
1074 g_assert(pbdev);
1075 pbdev->pci_unplug_request_processed = true;
1076 qdev_unplug(DEVICE(pbdev), errp);
1077 } else if (object_dynamic_cast(OBJECT(dev), TYPE_S390_PCI_DEVICE)) {
1078 pbdev = S390_PCI_DEVICE(dev);
1079
1080 /*
1081 * If unplug was initially requested for the zPCI device, we
1082 * first have to redirect to the PCI device, which will in return
1083 * redirect back to us after performing its checks (if the request
1084 * is not blocked, e.g. because it's a PCI bridge).
1085 */
1086 if (pbdev->pdev && !pbdev->pci_unplug_request_processed) {
1087 qdev_unplug(DEVICE(pbdev->pdev), errp);
1088 return;
1089 }
1090 pbdev->pci_unplug_request_processed = false;
1091
1092 switch (pbdev->state) {
1093 case ZPCI_FS_STANDBY:
1094 case ZPCI_FS_RESERVED:
1095 s390_pci_perform_unplug(pbdev);
1096 break;
1097 default:
1098 /*
1099 * Allow to send multiple requests, e.g. if the guest crashed
1100 * before releasing the device, we would not be able to send
1101 * another request to the same VM (e.g. fresh OS).
1102 */
1103 pbdev->unplug_requested = true;
1104 s390_pci_generate_plug_event(HP_EVENT_DECONFIGURE_REQUEST,
1105 pbdev->fh, pbdev->fid);
1106 }
1107 } else {
1108 g_assert_not_reached();
1109 }
1110 }
1111
1112 static void s390_pci_enumerate_bridge(PCIBus *bus, PCIDevice *pdev,
1113 void *opaque)
1114 {
1115 S390pciState *s = opaque;
1116 PCIBus *sec_bus = NULL;
1117
1118 if ((pci_default_read_config(pdev, PCI_HEADER_TYPE, 1) !=
1119 PCI_HEADER_TYPE_BRIDGE)) {
1120 return;
1121 }
1122
1123 (s->bus_no)++;
1124 pci_default_write_config(pdev, PCI_PRIMARY_BUS, pci_dev_bus_num(pdev), 1);
1125 pci_default_write_config(pdev, PCI_SECONDARY_BUS, s->bus_no, 1);
1126 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, s->bus_no, 1);
1127
1128 sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
1129 if (!sec_bus) {
1130 return;
1131 }
1132
1133 /* Assign numbers to all child bridges. The last is the highest number. */
1134 pci_for_each_device(sec_bus, pci_bus_num(sec_bus),
1135 s390_pci_enumerate_bridge, s);
1136 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, s->bus_no, 1);
1137 }
1138
1139 static void s390_pcihost_reset(DeviceState *dev)
1140 {
1141 S390pciState *s = S390_PCI_HOST_BRIDGE(dev);
1142 PCIBus *bus = s->parent_obj.bus;
1143 S390PCIBusDevice *pbdev, *next;
1144
1145 /* Process all pending unplug requests */
1146 QTAILQ_FOREACH_SAFE(pbdev, &s->zpci_devs, link, next) {
1147 if (pbdev->unplug_requested) {
1148 if (pbdev->summary_ind) {
1149 pci_dereg_irqs(pbdev);
1150 }
1151 if (pbdev->iommu->enabled) {
1152 pci_dereg_ioat(pbdev->iommu);
1153 }
1154 pbdev->state = ZPCI_FS_STANDBY;
1155 s390_pci_perform_unplug(pbdev);
1156 }
1157 }
1158
1159 /*
1160 * When resetting a PCI bridge, the assigned numbers are set to 0. So
1161 * on every system reset, we also have to reassign numbers.
1162 */
1163 s->bus_no = 0;
1164 pci_for_each_device(bus, pci_bus_num(bus), s390_pci_enumerate_bridge, s);
1165 }
1166
1167 static void s390_pcihost_class_init(ObjectClass *klass, void *data)
1168 {
1169 DeviceClass *dc = DEVICE_CLASS(klass);
1170 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
1171
1172 dc->reset = s390_pcihost_reset;
1173 dc->realize = s390_pcihost_realize;
1174 hc->pre_plug = s390_pcihost_pre_plug;
1175 hc->plug = s390_pcihost_plug;
1176 hc->unplug_request = s390_pcihost_unplug_request;
1177 hc->unplug = s390_pcihost_unplug;
1178 msi_nonbroken = true;
1179 }
1180
1181 static const TypeInfo s390_pcihost_info = {
1182 .name = TYPE_S390_PCI_HOST_BRIDGE,
1183 .parent = TYPE_PCI_HOST_BRIDGE,
1184 .instance_size = sizeof(S390pciState),
1185 .class_init = s390_pcihost_class_init,
1186 .interfaces = (InterfaceInfo[]) {
1187 { TYPE_HOTPLUG_HANDLER },
1188 { }
1189 }
1190 };
1191
1192 static const TypeInfo s390_pcibus_info = {
1193 .name = TYPE_S390_PCI_BUS,
1194 .parent = TYPE_BUS,
1195 .instance_size = sizeof(S390PCIBus),
1196 };
1197
1198 static uint16_t s390_pci_generate_uid(S390pciState *s)
1199 {
1200 uint16_t uid = 0;
1201
1202 do {
1203 uid++;
1204 if (!s390_pci_find_dev_by_uid(s, uid)) {
1205 return uid;
1206 }
1207 } while (uid < ZPCI_MAX_UID);
1208
1209 return UID_UNDEFINED;
1210 }
1211
1212 static uint32_t s390_pci_generate_fid(S390pciState *s, Error **errp)
1213 {
1214 uint32_t fid = 0;
1215
1216 do {
1217 if (!s390_pci_find_dev_by_fid(s, fid)) {
1218 return fid;
1219 }
1220 } while (fid++ != ZPCI_MAX_FID);
1221
1222 error_setg(errp, "no free fid could be found");
1223 return 0;
1224 }
1225
1226 static void s390_pci_device_realize(DeviceState *dev, Error **errp)
1227 {
1228 S390PCIBusDevice *zpci = S390_PCI_DEVICE(dev);
1229 S390pciState *s = s390_get_phb();
1230
1231 if (!zpci->target) {
1232 error_setg(errp, "target must be defined");
1233 return;
1234 }
1235
1236 if (s390_pci_find_dev_by_target(s, zpci->target)) {
1237 error_setg(errp, "target %s already has an associated zpci device",
1238 zpci->target);
1239 return;
1240 }
1241
1242 if (zpci->uid == UID_UNDEFINED) {
1243 zpci->uid = s390_pci_generate_uid(s);
1244 if (!zpci->uid) {
1245 error_setg(errp, "no free uid could be found");
1246 return;
1247 }
1248 } else if (s390_pci_find_dev_by_uid(s, zpci->uid)) {
1249 error_setg(errp, "uid %u already in use", zpci->uid);
1250 return;
1251 }
1252
1253 if (!zpci->fid_defined) {
1254 Error *local_error = NULL;
1255
1256 zpci->fid = s390_pci_generate_fid(s, &local_error);
1257 if (local_error) {
1258 error_propagate(errp, local_error);
1259 return;
1260 }
1261 } else if (s390_pci_find_dev_by_fid(s, zpci->fid)) {
1262 error_setg(errp, "fid %u already in use", zpci->fid);
1263 return;
1264 }
1265
1266 zpci->state = ZPCI_FS_RESERVED;
1267 zpci->fmb.format = ZPCI_FMB_FORMAT;
1268 }
1269
1270 static void s390_pci_device_reset(DeviceState *dev)
1271 {
1272 S390PCIBusDevice *pbdev = S390_PCI_DEVICE(dev);
1273
1274 switch (pbdev->state) {
1275 case ZPCI_FS_RESERVED:
1276 return;
1277 case ZPCI_FS_STANDBY:
1278 break;
1279 default:
1280 pbdev->fh &= ~FH_MASK_ENABLE;
1281 pbdev->state = ZPCI_FS_DISABLED;
1282 break;
1283 }
1284
1285 if (pbdev->summary_ind) {
1286 pci_dereg_irqs(pbdev);
1287 }
1288 if (pbdev->iommu->enabled) {
1289 pci_dereg_ioat(pbdev->iommu);
1290 }
1291
1292 fmb_timer_free(pbdev);
1293 }
1294
1295 static void s390_pci_get_fid(Object *obj, Visitor *v, const char *name,
1296 void *opaque, Error **errp)
1297 {
1298 Property *prop = opaque;
1299 uint32_t *ptr = qdev_get_prop_ptr(DEVICE(obj), prop);
1300
1301 visit_type_uint32(v, name, ptr, errp);
1302 }
1303
1304 static void s390_pci_set_fid(Object *obj, Visitor *v, const char *name,
1305 void *opaque, Error **errp)
1306 {
1307 DeviceState *dev = DEVICE(obj);
1308 S390PCIBusDevice *zpci = S390_PCI_DEVICE(obj);
1309 Property *prop = opaque;
1310 uint32_t *ptr = qdev_get_prop_ptr(dev, prop);
1311
1312 if (dev->realized) {
1313 qdev_prop_set_after_realize(dev, name, errp);
1314 return;
1315 }
1316
1317 if (!visit_type_uint32(v, name, ptr, errp)) {
1318 return;
1319 }
1320 zpci->fid_defined = true;
1321 }
1322
1323 static const PropertyInfo s390_pci_fid_propinfo = {
1324 .name = "zpci_fid",
1325 .get = s390_pci_get_fid,
1326 .set = s390_pci_set_fid,
1327 };
1328
1329 #define DEFINE_PROP_S390_PCI_FID(_n, _s, _f) \
1330 DEFINE_PROP(_n, _s, _f, s390_pci_fid_propinfo, uint32_t)
1331
1332 static Property s390_pci_device_properties[] = {
1333 DEFINE_PROP_UINT16("uid", S390PCIBusDevice, uid, UID_UNDEFINED),
1334 DEFINE_PROP_S390_PCI_FID("fid", S390PCIBusDevice, fid),
1335 DEFINE_PROP_STRING("target", S390PCIBusDevice, target),
1336 DEFINE_PROP_END_OF_LIST(),
1337 };
1338
1339 static const VMStateDescription s390_pci_device_vmstate = {
1340 .name = TYPE_S390_PCI_DEVICE,
1341 /*
1342 * TODO: add state handling here, so migration works at least with
1343 * emulated pci devices on s390x
1344 */
1345 .unmigratable = 1,
1346 };
1347
1348 static void s390_pci_device_class_init(ObjectClass *klass, void *data)
1349 {
1350 DeviceClass *dc = DEVICE_CLASS(klass);
1351
1352 dc->desc = "zpci device";
1353 set_bit(DEVICE_CATEGORY_MISC, dc->categories);
1354 dc->reset = s390_pci_device_reset;
1355 dc->bus_type = TYPE_S390_PCI_BUS;
1356 dc->realize = s390_pci_device_realize;
1357 device_class_set_props(dc, s390_pci_device_properties);
1358 dc->vmsd = &s390_pci_device_vmstate;
1359 }
1360
1361 static const TypeInfo s390_pci_device_info = {
1362 .name = TYPE_S390_PCI_DEVICE,
1363 .parent = TYPE_DEVICE,
1364 .instance_size = sizeof(S390PCIBusDevice),
1365 .class_init = s390_pci_device_class_init,
1366 };
1367
1368 static TypeInfo s390_pci_iommu_info = {
1369 .name = TYPE_S390_PCI_IOMMU,
1370 .parent = TYPE_OBJECT,
1371 .instance_size = sizeof(S390PCIIOMMU),
1372 };
1373
1374 static void s390_iommu_memory_region_class_init(ObjectClass *klass, void *data)
1375 {
1376 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass);
1377
1378 imrc->translate = s390_translate_iommu;
1379 imrc->replay = s390_pci_iommu_replay;
1380 }
1381
1382 static const TypeInfo s390_iommu_memory_region_info = {
1383 .parent = TYPE_IOMMU_MEMORY_REGION,
1384 .name = TYPE_S390_IOMMU_MEMORY_REGION,
1385 .class_init = s390_iommu_memory_region_class_init,
1386 };
1387
1388 static void s390_pci_register_types(void)
1389 {
1390 type_register_static(&s390_pcihost_info);
1391 type_register_static(&s390_pcibus_info);
1392 type_register_static(&s390_pci_device_info);
1393 type_register_static(&s390_pci_iommu_info);
1394 type_register_static(&s390_iommu_memory_region_info);
1395 }
1396
1397 type_init(s390_pci_register_types)