s390x/pci: fix endianness issues
[qemu.git] / hw / s390x / s390-pci-inst.c
1 /*
2 * s390 PCI instructions
3 *
4 * Copyright 2014 IBM Corp.
5 * Author(s): Frank Blaschka <frank.blaschka@de.ibm.com>
6 * Hong Bo Li <lihbbj@cn.ibm.com>
7 * Yi Min Zhao <zyimin@cn.ibm.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2 or (at
10 * your option) any later version. See the COPYING file in the top-level
11 * directory.
12 */
13
14 #include "qemu/osdep.h"
15 #include "cpu.h"
16 #include "exec/memop.h"
17 #include "exec/memory-internal.h"
18 #include "qemu/error-report.h"
19 #include "sysemu/hw_accel.h"
20 #include "hw/s390x/s390-pci-inst.h"
21 #include "hw/s390x/s390-pci-bus.h"
22 #include "hw/s390x/tod.h"
23
24 #ifndef DEBUG_S390PCI_INST
25 #define DEBUG_S390PCI_INST 0
26 #endif
27
28 #define DPRINTF(fmt, ...) \
29 do { \
30 if (DEBUG_S390PCI_INST) { \
31 fprintf(stderr, "s390pci-inst: " fmt, ## __VA_ARGS__); \
32 } \
33 } while (0)
34
35 static inline void inc_dma_avail(S390PCIIOMMU *iommu)
36 {
37 if (iommu->dma_limit) {
38 iommu->dma_limit->avail++;
39 }
40 }
41
42 static inline void dec_dma_avail(S390PCIIOMMU *iommu)
43 {
44 if (iommu->dma_limit) {
45 iommu->dma_limit->avail--;
46 }
47 }
48
49 static void s390_set_status_code(CPUS390XState *env,
50 uint8_t r, uint64_t status_code)
51 {
52 env->regs[r] &= ~0xff000000ULL;
53 env->regs[r] |= (status_code & 0xff) << 24;
54 }
55
56 static int list_pci(ClpReqRspListPci *rrb, uint8_t *cc)
57 {
58 S390PCIBusDevice *pbdev = NULL;
59 S390pciState *s = s390_get_phb();
60 uint32_t res_code, initial_l2, g_l2;
61 int rc, i;
62 uint64_t resume_token;
63
64 rc = 0;
65 if (lduw_p(&rrb->request.hdr.len) != 32) {
66 res_code = CLP_RC_LEN;
67 rc = -EINVAL;
68 goto out;
69 }
70
71 if ((ldl_p(&rrb->request.fmt) & CLP_MASK_FMT) != 0) {
72 res_code = CLP_RC_FMT;
73 rc = -EINVAL;
74 goto out;
75 }
76
77 if ((ldl_p(&rrb->request.fmt) & ~CLP_MASK_FMT) != 0 ||
78 ldq_p(&rrb->request.reserved1) != 0) {
79 res_code = CLP_RC_RESNOT0;
80 rc = -EINVAL;
81 goto out;
82 }
83
84 resume_token = ldq_p(&rrb->request.resume_token);
85
86 if (resume_token) {
87 pbdev = s390_pci_find_dev_by_idx(s, resume_token);
88 if (!pbdev) {
89 res_code = CLP_RC_LISTPCI_BADRT;
90 rc = -EINVAL;
91 goto out;
92 }
93 } else {
94 pbdev = s390_pci_find_next_avail_dev(s, NULL);
95 }
96
97 if (lduw_p(&rrb->response.hdr.len) < 48) {
98 res_code = CLP_RC_8K;
99 rc = -EINVAL;
100 goto out;
101 }
102
103 initial_l2 = lduw_p(&rrb->response.hdr.len);
104 if ((initial_l2 - LIST_PCI_HDR_LEN) % sizeof(ClpFhListEntry)
105 != 0) {
106 res_code = CLP_RC_LEN;
107 rc = -EINVAL;
108 *cc = 3;
109 goto out;
110 }
111
112 stl_p(&rrb->response.fmt, 0);
113 stq_p(&rrb->response.reserved1, 0);
114 stl_p(&rrb->response.mdd, FH_MASK_SHM);
115 stw_p(&rrb->response.max_fn, PCI_MAX_FUNCTIONS);
116 rrb->response.flags = UID_CHECKING_ENABLED;
117 rrb->response.entry_size = sizeof(ClpFhListEntry);
118
119 i = 0;
120 g_l2 = LIST_PCI_HDR_LEN;
121 while (g_l2 < initial_l2 && pbdev) {
122 stw_p(&rrb->response.fh_list[i].device_id,
123 pci_get_word(pbdev->pdev->config + PCI_DEVICE_ID));
124 stw_p(&rrb->response.fh_list[i].vendor_id,
125 pci_get_word(pbdev->pdev->config + PCI_VENDOR_ID));
126 /* Ignore RESERVED devices. */
127 stl_p(&rrb->response.fh_list[i].config,
128 pbdev->state == ZPCI_FS_STANDBY ? 0 : 1 << 31);
129 stl_p(&rrb->response.fh_list[i].fid, pbdev->fid);
130 stl_p(&rrb->response.fh_list[i].fh, pbdev->fh);
131
132 g_l2 += sizeof(ClpFhListEntry);
133 /* Add endian check for DPRINTF? */
134 DPRINTF("g_l2 %d vendor id 0x%x device id 0x%x fid 0x%x fh 0x%x\n",
135 g_l2,
136 lduw_p(&rrb->response.fh_list[i].vendor_id),
137 lduw_p(&rrb->response.fh_list[i].device_id),
138 ldl_p(&rrb->response.fh_list[i].fid),
139 ldl_p(&rrb->response.fh_list[i].fh));
140 pbdev = s390_pci_find_next_avail_dev(s, pbdev);
141 i++;
142 }
143
144 if (!pbdev) {
145 resume_token = 0;
146 } else {
147 resume_token = pbdev->fh & FH_MASK_INDEX;
148 }
149 stq_p(&rrb->response.resume_token, resume_token);
150 stw_p(&rrb->response.hdr.len, g_l2);
151 stw_p(&rrb->response.hdr.rsp, CLP_RC_OK);
152 out:
153 if (rc) {
154 DPRINTF("list pci failed rc 0x%x\n", rc);
155 stw_p(&rrb->response.hdr.rsp, res_code);
156 }
157 return rc;
158 }
159
160 int clp_service_call(S390CPU *cpu, uint8_t r2, uintptr_t ra)
161 {
162 ClpReqHdr *reqh;
163 ClpRspHdr *resh;
164 S390PCIBusDevice *pbdev;
165 uint32_t req_len;
166 uint32_t res_len;
167 uint8_t buffer[4096 * 2];
168 uint8_t cc = 0;
169 CPUS390XState *env = &cpu->env;
170 S390pciState *s = s390_get_phb();
171 int i;
172
173 if (env->psw.mask & PSW_MASK_PSTATE) {
174 s390_program_interrupt(env, PGM_PRIVILEGED, ra);
175 return 0;
176 }
177
178 if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer, sizeof(*reqh))) {
179 s390_cpu_virt_mem_handle_exc(cpu, ra);
180 return 0;
181 }
182 reqh = (ClpReqHdr *)buffer;
183 req_len = lduw_p(&reqh->len);
184 if (req_len < 16 || req_len > 8184 || (req_len % 8 != 0)) {
185 s390_program_interrupt(env, PGM_OPERAND, ra);
186 return 0;
187 }
188
189 if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer,
190 req_len + sizeof(*resh))) {
191 s390_cpu_virt_mem_handle_exc(cpu, ra);
192 return 0;
193 }
194 resh = (ClpRspHdr *)(buffer + req_len);
195 res_len = lduw_p(&resh->len);
196 if (res_len < 8 || res_len > 8176 || (res_len % 8 != 0)) {
197 s390_program_interrupt(env, PGM_OPERAND, ra);
198 return 0;
199 }
200 if ((req_len + res_len) > 8192) {
201 s390_program_interrupt(env, PGM_OPERAND, ra);
202 return 0;
203 }
204
205 if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer,
206 req_len + res_len)) {
207 s390_cpu_virt_mem_handle_exc(cpu, ra);
208 return 0;
209 }
210
211 if (req_len != 32) {
212 stw_p(&resh->rsp, CLP_RC_LEN);
213 goto out;
214 }
215
216 switch (lduw_p(&reqh->cmd)) {
217 case CLP_LIST_PCI: {
218 ClpReqRspListPci *rrb = (ClpReqRspListPci *)buffer;
219 list_pci(rrb, &cc);
220 break;
221 }
222 case CLP_SET_PCI_FN: {
223 ClpReqSetPci *reqsetpci = (ClpReqSetPci *)reqh;
224 ClpRspSetPci *ressetpci = (ClpRspSetPci *)resh;
225
226 pbdev = s390_pci_find_dev_by_fh(s, ldl_p(&reqsetpci->fh));
227 if (!pbdev) {
228 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FH);
229 goto out;
230 }
231
232 switch (reqsetpci->oc) {
233 case CLP_SET_ENABLE_PCI_FN:
234 switch (reqsetpci->ndas) {
235 case 0:
236 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_DMAAS);
237 goto out;
238 case 1:
239 break;
240 default:
241 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_RES);
242 goto out;
243 }
244
245 if (pbdev->fh & FH_MASK_ENABLE) {
246 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP);
247 goto out;
248 }
249
250 pbdev->fh |= FH_MASK_ENABLE;
251 pbdev->state = ZPCI_FS_ENABLED;
252 stl_p(&ressetpci->fh, pbdev->fh);
253 stw_p(&ressetpci->hdr.rsp, CLP_RC_OK);
254 break;
255 case CLP_SET_DISABLE_PCI_FN:
256 if (!(pbdev->fh & FH_MASK_ENABLE)) {
257 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP);
258 goto out;
259 }
260 device_legacy_reset(DEVICE(pbdev));
261 pbdev->fh &= ~FH_MASK_ENABLE;
262 pbdev->state = ZPCI_FS_DISABLED;
263 stl_p(&ressetpci->fh, pbdev->fh);
264 stw_p(&ressetpci->hdr.rsp, CLP_RC_OK);
265 break;
266 default:
267 DPRINTF("unknown set pci command\n");
268 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP);
269 break;
270 }
271 break;
272 }
273 case CLP_QUERY_PCI_FN: {
274 ClpReqQueryPci *reqquery = (ClpReqQueryPci *)reqh;
275 ClpRspQueryPci *resquery = (ClpRspQueryPci *)resh;
276
277 pbdev = s390_pci_find_dev_by_fh(s, ldl_p(&reqquery->fh));
278 if (!pbdev) {
279 DPRINTF("query pci no pci dev\n");
280 stw_p(&resquery->hdr.rsp, CLP_RC_SETPCIFN_FH);
281 goto out;
282 }
283
284 stq_p(&resquery->sdma, pbdev->zpci_fn.sdma);
285 stq_p(&resquery->edma, pbdev->zpci_fn.edma);
286 stw_p(&resquery->pchid, pbdev->zpci_fn.pchid);
287 resquery->flags = pbdev->zpci_fn.flags;
288 resquery->pfgid = pbdev->zpci_fn.pfgid;
289 stl_p(&resquery->fid, pbdev->zpci_fn.fid);
290 stl_p(&resquery->uid, pbdev->zpci_fn.uid);
291
292 for (i = 0; i < PCI_BAR_COUNT; i++) {
293 uint32_t data = pci_get_long(pbdev->pdev->config +
294 PCI_BASE_ADDRESS_0 + (i * 4));
295
296 stl_p(&resquery->bar[i], data);
297 resquery->bar_size[i] = pbdev->pdev->io_regions[i].size ?
298 ctz64(pbdev->pdev->io_regions[i].size) : 0;
299 DPRINTF("bar %d addr 0x%x size 0x%" PRIx64 "barsize 0x%x\n", i,
300 ldl_p(&resquery->bar[i]),
301 pbdev->pdev->io_regions[i].size,
302 resquery->bar_size[i]);
303 }
304
305 stw_p(&resquery->hdr.rsp, CLP_RC_OK);
306 break;
307 }
308 case CLP_QUERY_PCI_FNGRP: {
309 ClpRspQueryPciGrp *resgrp = (ClpRspQueryPciGrp *)resh;
310
311 ClpReqQueryPciGrp *reqgrp = (ClpReqQueryPciGrp *)reqh;
312 S390PCIGroup *group;
313
314 group = s390_group_find(reqgrp->g);
315 if (!group) {
316 /* We do not allow access to unknown groups */
317 /* The group must have been obtained with a vfio device */
318 stw_p(&resgrp->hdr.rsp, CLP_RC_QUERYPCIFG_PFGID);
319 goto out;
320 }
321 resgrp->fr = group->zpci_group.fr;
322 stq_p(&resgrp->dasm, group->zpci_group.dasm);
323 stq_p(&resgrp->msia, group->zpci_group.msia);
324 stw_p(&resgrp->mui, group->zpci_group.mui);
325 stw_p(&resgrp->i, group->zpci_group.i);
326 stw_p(&resgrp->maxstbl, group->zpci_group.maxstbl);
327 resgrp->version = group->zpci_group.version;
328 stw_p(&resgrp->hdr.rsp, CLP_RC_OK);
329 break;
330 }
331 default:
332 DPRINTF("unknown clp command\n");
333 stw_p(&resh->rsp, CLP_RC_CMD);
334 break;
335 }
336
337 out:
338 if (s390_cpu_virt_mem_write(cpu, env->regs[r2], r2, buffer,
339 req_len + res_len)) {
340 s390_cpu_virt_mem_handle_exc(cpu, ra);
341 return 0;
342 }
343 setcc(cpu, cc);
344 return 0;
345 }
346
347 /**
348 * Swap data contained in s390x big endian registers to little endian
349 * PCI bars.
350 *
351 * @ptr: a pointer to a uint64_t data field
352 * @len: the length of the valid data, must be 1,2,4 or 8
353 */
354 static int zpci_endian_swap(uint64_t *ptr, uint8_t len)
355 {
356 uint64_t data = *ptr;
357
358 switch (len) {
359 case 1:
360 break;
361 case 2:
362 data = bswap16(data);
363 break;
364 case 4:
365 data = bswap32(data);
366 break;
367 case 8:
368 data = bswap64(data);
369 break;
370 default:
371 return -EINVAL;
372 }
373 *ptr = data;
374 return 0;
375 }
376
377 static MemoryRegion *s390_get_subregion(MemoryRegion *mr, uint64_t offset,
378 uint8_t len)
379 {
380 MemoryRegion *subregion;
381 uint64_t subregion_size;
382
383 QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) {
384 subregion_size = int128_get64(subregion->size);
385 if ((offset >= subregion->addr) &&
386 (offset + len) <= (subregion->addr + subregion_size)) {
387 mr = subregion;
388 break;
389 }
390 }
391 return mr;
392 }
393
394 static MemTxResult zpci_read_bar(S390PCIBusDevice *pbdev, uint8_t pcias,
395 uint64_t offset, uint64_t *data, uint8_t len)
396 {
397 MemoryRegion *mr;
398
399 mr = pbdev->pdev->io_regions[pcias].memory;
400 mr = s390_get_subregion(mr, offset, len);
401 offset -= mr->addr;
402 return memory_region_dispatch_read(mr, offset, data,
403 size_memop(len) | MO_BE,
404 MEMTXATTRS_UNSPECIFIED);
405 }
406
407 int pcilg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2, uintptr_t ra)
408 {
409 CPUS390XState *env = &cpu->env;
410 S390PCIBusDevice *pbdev;
411 uint64_t offset;
412 uint64_t data;
413 MemTxResult result;
414 uint8_t len;
415 uint32_t fh;
416 uint8_t pcias;
417
418 if (env->psw.mask & PSW_MASK_PSTATE) {
419 s390_program_interrupt(env, PGM_PRIVILEGED, ra);
420 return 0;
421 }
422
423 if (r2 & 0x1) {
424 s390_program_interrupt(env, PGM_SPECIFICATION, ra);
425 return 0;
426 }
427
428 fh = env->regs[r2] >> 32;
429 pcias = (env->regs[r2] >> 16) & 0xf;
430 len = env->regs[r2] & 0xf;
431 offset = env->regs[r2 + 1];
432
433 if (!(fh & FH_MASK_ENABLE)) {
434 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
435 return 0;
436 }
437
438 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh);
439 if (!pbdev) {
440 DPRINTF("pcilg no pci dev\n");
441 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
442 return 0;
443 }
444
445 switch (pbdev->state) {
446 case ZPCI_FS_PERMANENT_ERROR:
447 case ZPCI_FS_ERROR:
448 setcc(cpu, ZPCI_PCI_LS_ERR);
449 s390_set_status_code(env, r2, ZPCI_PCI_ST_BLOCKED);
450 return 0;
451 default:
452 break;
453 }
454
455 switch (pcias) {
456 case ZPCI_IO_BAR_MIN...ZPCI_IO_BAR_MAX:
457 if (!len || (len > (8 - (offset & 0x7)))) {
458 s390_program_interrupt(env, PGM_OPERAND, ra);
459 return 0;
460 }
461 result = zpci_read_bar(pbdev, pcias, offset, &data, len);
462 if (result != MEMTX_OK) {
463 s390_program_interrupt(env, PGM_OPERAND, ra);
464 return 0;
465 }
466 break;
467 case ZPCI_CONFIG_BAR:
468 if (!len || (len > (4 - (offset & 0x3))) || len == 3) {
469 s390_program_interrupt(env, PGM_OPERAND, ra);
470 return 0;
471 }
472 data = pci_host_config_read_common(
473 pbdev->pdev, offset, pci_config_size(pbdev->pdev), len);
474
475 if (zpci_endian_swap(&data, len)) {
476 s390_program_interrupt(env, PGM_OPERAND, ra);
477 return 0;
478 }
479 break;
480 default:
481 DPRINTF("pcilg invalid space\n");
482 setcc(cpu, ZPCI_PCI_LS_ERR);
483 s390_set_status_code(env, r2, ZPCI_PCI_ST_INVAL_AS);
484 return 0;
485 }
486
487 pbdev->fmb.counter[ZPCI_FMB_CNT_LD]++;
488
489 env->regs[r1] = data;
490 setcc(cpu, ZPCI_PCI_LS_OK);
491 return 0;
492 }
493
494 static MemTxResult zpci_write_bar(S390PCIBusDevice *pbdev, uint8_t pcias,
495 uint64_t offset, uint64_t data, uint8_t len)
496 {
497 MemoryRegion *mr;
498
499 mr = pbdev->pdev->io_regions[pcias].memory;
500 mr = s390_get_subregion(mr, offset, len);
501 offset -= mr->addr;
502 return memory_region_dispatch_write(mr, offset, data,
503 size_memop(len) | MO_BE,
504 MEMTXATTRS_UNSPECIFIED);
505 }
506
507 int pcistg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2, uintptr_t ra)
508 {
509 CPUS390XState *env = &cpu->env;
510 uint64_t offset, data;
511 S390PCIBusDevice *pbdev;
512 MemTxResult result;
513 uint8_t len;
514 uint32_t fh;
515 uint8_t pcias;
516
517 if (env->psw.mask & PSW_MASK_PSTATE) {
518 s390_program_interrupt(env, PGM_PRIVILEGED, ra);
519 return 0;
520 }
521
522 if (r2 & 0x1) {
523 s390_program_interrupt(env, PGM_SPECIFICATION, ra);
524 return 0;
525 }
526
527 fh = env->regs[r2] >> 32;
528 pcias = (env->regs[r2] >> 16) & 0xf;
529 len = env->regs[r2] & 0xf;
530 offset = env->regs[r2 + 1];
531 data = env->regs[r1];
532
533 if (!(fh & FH_MASK_ENABLE)) {
534 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
535 return 0;
536 }
537
538 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh);
539 if (!pbdev) {
540 DPRINTF("pcistg no pci dev\n");
541 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
542 return 0;
543 }
544
545 switch (pbdev->state) {
546 /* ZPCI_FS_RESERVED, ZPCI_FS_STANDBY and ZPCI_FS_DISABLED
547 * are already covered by the FH_MASK_ENABLE check above
548 */
549 case ZPCI_FS_PERMANENT_ERROR:
550 case ZPCI_FS_ERROR:
551 setcc(cpu, ZPCI_PCI_LS_ERR);
552 s390_set_status_code(env, r2, ZPCI_PCI_ST_BLOCKED);
553 return 0;
554 default:
555 break;
556 }
557
558 switch (pcias) {
559 /* A ZPCI PCI card may use any BAR from BAR 0 to BAR 5 */
560 case ZPCI_IO_BAR_MIN...ZPCI_IO_BAR_MAX:
561 /* Check length:
562 * A length of 0 is invalid and length should not cross a double word
563 */
564 if (!len || (len > (8 - (offset & 0x7)))) {
565 s390_program_interrupt(env, PGM_OPERAND, ra);
566 return 0;
567 }
568
569 result = zpci_write_bar(pbdev, pcias, offset, data, len);
570 if (result != MEMTX_OK) {
571 s390_program_interrupt(env, PGM_OPERAND, ra);
572 return 0;
573 }
574 break;
575 case ZPCI_CONFIG_BAR:
576 /* ZPCI uses the pseudo BAR number 15 as configuration space */
577 /* possible access lengths are 1,2,4 and must not cross a word */
578 if (!len || (len > (4 - (offset & 0x3))) || len == 3) {
579 s390_program_interrupt(env, PGM_OPERAND, ra);
580 return 0;
581 }
582 /* len = 1,2,4 so we do not need to test */
583 zpci_endian_swap(&data, len);
584 pci_host_config_write_common(pbdev->pdev, offset,
585 pci_config_size(pbdev->pdev),
586 data, len);
587 break;
588 default:
589 DPRINTF("pcistg invalid space\n");
590 setcc(cpu, ZPCI_PCI_LS_ERR);
591 s390_set_status_code(env, r2, ZPCI_PCI_ST_INVAL_AS);
592 return 0;
593 }
594
595 pbdev->fmb.counter[ZPCI_FMB_CNT_ST]++;
596
597 setcc(cpu, ZPCI_PCI_LS_OK);
598 return 0;
599 }
600
601 static uint32_t s390_pci_update_iotlb(S390PCIIOMMU *iommu,
602 S390IOTLBEntry *entry)
603 {
604 S390IOTLBEntry *cache = g_hash_table_lookup(iommu->iotlb, &entry->iova);
605 IOMMUTLBEntry notify = {
606 .target_as = &address_space_memory,
607 .iova = entry->iova,
608 .translated_addr = entry->translated_addr,
609 .perm = entry->perm,
610 .addr_mask = ~PAGE_MASK,
611 };
612
613 if (entry->perm == IOMMU_NONE) {
614 if (!cache) {
615 goto out;
616 }
617 g_hash_table_remove(iommu->iotlb, &entry->iova);
618 inc_dma_avail(iommu);
619 } else {
620 if (cache) {
621 if (cache->perm == entry->perm &&
622 cache->translated_addr == entry->translated_addr) {
623 goto out;
624 }
625
626 notify.perm = IOMMU_NONE;
627 memory_region_notify_iommu(&iommu->iommu_mr, 0, notify);
628 notify.perm = entry->perm;
629 }
630
631 cache = g_new(S390IOTLBEntry, 1);
632 cache->iova = entry->iova;
633 cache->translated_addr = entry->translated_addr;
634 cache->len = PAGE_SIZE;
635 cache->perm = entry->perm;
636 g_hash_table_replace(iommu->iotlb, &cache->iova, cache);
637 dec_dma_avail(iommu);
638 }
639
640 memory_region_notify_iommu(&iommu->iommu_mr, 0, notify);
641
642 out:
643 return iommu->dma_limit ? iommu->dma_limit->avail : 1;
644 }
645
646 int rpcit_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2, uintptr_t ra)
647 {
648 CPUS390XState *env = &cpu->env;
649 uint32_t fh;
650 uint16_t error = 0;
651 S390PCIBusDevice *pbdev;
652 S390PCIIOMMU *iommu;
653 S390IOTLBEntry entry;
654 hwaddr start, end;
655 uint32_t dma_avail;
656
657 if (env->psw.mask & PSW_MASK_PSTATE) {
658 s390_program_interrupt(env, PGM_PRIVILEGED, ra);
659 return 0;
660 }
661
662 if (r2 & 0x1) {
663 s390_program_interrupt(env, PGM_SPECIFICATION, ra);
664 return 0;
665 }
666
667 fh = env->regs[r1] >> 32;
668 start = env->regs[r2];
669 end = start + env->regs[r2 + 1];
670
671 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh);
672 if (!pbdev) {
673 DPRINTF("rpcit no pci dev\n");
674 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
675 return 0;
676 }
677
678 switch (pbdev->state) {
679 case ZPCI_FS_RESERVED:
680 case ZPCI_FS_STANDBY:
681 case ZPCI_FS_DISABLED:
682 case ZPCI_FS_PERMANENT_ERROR:
683 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
684 return 0;
685 case ZPCI_FS_ERROR:
686 setcc(cpu, ZPCI_PCI_LS_ERR);
687 s390_set_status_code(env, r1, ZPCI_MOD_ST_ERROR_RECOVER);
688 return 0;
689 default:
690 break;
691 }
692
693 iommu = pbdev->iommu;
694 if (iommu->dma_limit) {
695 dma_avail = iommu->dma_limit->avail;
696 } else {
697 dma_avail = 1;
698 }
699 if (!iommu->g_iota) {
700 error = ERR_EVENT_INVALAS;
701 goto err;
702 }
703
704 if (end < iommu->pba || start > iommu->pal) {
705 error = ERR_EVENT_OORANGE;
706 goto err;
707 }
708
709 while (start < end) {
710 error = s390_guest_io_table_walk(iommu->g_iota, start, &entry);
711 if (error) {
712 break;
713 }
714
715 start += entry.len;
716 while (entry.iova < start && entry.iova < end &&
717 (dma_avail > 0 || entry.perm == IOMMU_NONE)) {
718 dma_avail = s390_pci_update_iotlb(iommu, &entry);
719 entry.iova += PAGE_SIZE;
720 entry.translated_addr += PAGE_SIZE;
721 }
722 }
723 err:
724 if (error) {
725 pbdev->state = ZPCI_FS_ERROR;
726 setcc(cpu, ZPCI_PCI_LS_ERR);
727 s390_set_status_code(env, r1, ZPCI_PCI_ST_FUNC_IN_ERR);
728 s390_pci_generate_error_event(error, pbdev->fh, pbdev->fid, start, 0);
729 } else {
730 pbdev->fmb.counter[ZPCI_FMB_CNT_RPCIT]++;
731 if (dma_avail > 0) {
732 setcc(cpu, ZPCI_PCI_LS_OK);
733 } else {
734 /* vfio DMA mappings are exhausted, trigger a RPCIT */
735 setcc(cpu, ZPCI_PCI_LS_ERR);
736 s390_set_status_code(env, r1, ZPCI_RPCIT_ST_INSUFF_RES);
737 }
738 }
739 return 0;
740 }
741
742 int pcistb_service_call(S390CPU *cpu, uint8_t r1, uint8_t r3, uint64_t gaddr,
743 uint8_t ar, uintptr_t ra)
744 {
745 CPUS390XState *env = &cpu->env;
746 S390PCIBusDevice *pbdev;
747 MemoryRegion *mr;
748 MemTxResult result;
749 uint64_t offset;
750 int i;
751 uint32_t fh;
752 uint8_t pcias;
753 uint8_t len;
754 uint8_t buffer[128];
755
756 if (env->psw.mask & PSW_MASK_PSTATE) {
757 s390_program_interrupt(env, PGM_PRIVILEGED, ra);
758 return 0;
759 }
760
761 fh = env->regs[r1] >> 32;
762 pcias = (env->regs[r1] >> 16) & 0xf;
763 len = env->regs[r1] & 0xff;
764 offset = env->regs[r3];
765
766 if (!(fh & FH_MASK_ENABLE)) {
767 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
768 return 0;
769 }
770
771 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh);
772 if (!pbdev) {
773 DPRINTF("pcistb no pci dev fh 0x%x\n", fh);
774 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
775 return 0;
776 }
777
778 switch (pbdev->state) {
779 case ZPCI_FS_PERMANENT_ERROR:
780 case ZPCI_FS_ERROR:
781 setcc(cpu, ZPCI_PCI_LS_ERR);
782 s390_set_status_code(env, r1, ZPCI_PCI_ST_BLOCKED);
783 return 0;
784 default:
785 break;
786 }
787
788 if (pcias > ZPCI_IO_BAR_MAX) {
789 DPRINTF("pcistb invalid space\n");
790 setcc(cpu, ZPCI_PCI_LS_ERR);
791 s390_set_status_code(env, r1, ZPCI_PCI_ST_INVAL_AS);
792 return 0;
793 }
794
795 /* Verify the address, offset and length */
796 /* offset must be a multiple of 8 */
797 if (offset % 8) {
798 goto specification_error;
799 }
800 /* Length must be greater than 8, a multiple of 8 */
801 /* and not greater than maxstbl */
802 if ((len <= 8) || (len % 8) ||
803 (len > pbdev->pci_group->zpci_group.maxstbl)) {
804 goto specification_error;
805 }
806 /* Do not cross a 4K-byte boundary */
807 if (((offset & 0xfff) + len) > 0x1000) {
808 goto specification_error;
809 }
810 /* Guest address must be double word aligned */
811 if (gaddr & 0x07UL) {
812 goto specification_error;
813 }
814
815 mr = pbdev->pdev->io_regions[pcias].memory;
816 mr = s390_get_subregion(mr, offset, len);
817 offset -= mr->addr;
818
819 if (!memory_region_access_valid(mr, offset, len, true,
820 MEMTXATTRS_UNSPECIFIED)) {
821 s390_program_interrupt(env, PGM_OPERAND, ra);
822 return 0;
823 }
824
825 if (s390_cpu_virt_mem_read(cpu, gaddr, ar, buffer, len)) {
826 s390_cpu_virt_mem_handle_exc(cpu, ra);
827 return 0;
828 }
829
830 for (i = 0; i < len / 8; i++) {
831 result = memory_region_dispatch_write(mr, offset + i * 8,
832 ldq_p(buffer + i * 8),
833 MO_64, MEMTXATTRS_UNSPECIFIED);
834 if (result != MEMTX_OK) {
835 s390_program_interrupt(env, PGM_OPERAND, ra);
836 return 0;
837 }
838 }
839
840 pbdev->fmb.counter[ZPCI_FMB_CNT_STB]++;
841
842 setcc(cpu, ZPCI_PCI_LS_OK);
843 return 0;
844
845 specification_error:
846 s390_program_interrupt(env, PGM_SPECIFICATION, ra);
847 return 0;
848 }
849
850 static int reg_irqs(CPUS390XState *env, S390PCIBusDevice *pbdev, ZpciFib fib)
851 {
852 int ret, len;
853 uint8_t isc = FIB_DATA_ISC(ldl_p(&fib.data));
854
855 pbdev->routes.adapter.adapter_id = css_get_adapter_id(
856 CSS_IO_ADAPTER_PCI, isc);
857 pbdev->summary_ind = get_indicator(ldq_p(&fib.aisb), sizeof(uint64_t));
858 len = BITS_TO_LONGS(FIB_DATA_NOI(ldl_p(&fib.data))) * sizeof(unsigned long);
859 pbdev->indicator = get_indicator(ldq_p(&fib.aibv), len);
860
861 ret = map_indicator(&pbdev->routes.adapter, pbdev->summary_ind);
862 if (ret) {
863 goto out;
864 }
865
866 ret = map_indicator(&pbdev->routes.adapter, pbdev->indicator);
867 if (ret) {
868 goto out;
869 }
870
871 pbdev->routes.adapter.summary_addr = ldq_p(&fib.aisb);
872 pbdev->routes.adapter.summary_offset = FIB_DATA_AISBO(ldl_p(&fib.data));
873 pbdev->routes.adapter.ind_addr = ldq_p(&fib.aibv);
874 pbdev->routes.adapter.ind_offset = FIB_DATA_AIBVO(ldl_p(&fib.data));
875 pbdev->isc = isc;
876 pbdev->noi = FIB_DATA_NOI(ldl_p(&fib.data));
877 pbdev->sum = FIB_DATA_SUM(ldl_p(&fib.data));
878
879 DPRINTF("reg_irqs adapter id %d\n", pbdev->routes.adapter.adapter_id);
880 return 0;
881 out:
882 release_indicator(&pbdev->routes.adapter, pbdev->summary_ind);
883 release_indicator(&pbdev->routes.adapter, pbdev->indicator);
884 pbdev->summary_ind = NULL;
885 pbdev->indicator = NULL;
886 return ret;
887 }
888
889 int pci_dereg_irqs(S390PCIBusDevice *pbdev)
890 {
891 release_indicator(&pbdev->routes.adapter, pbdev->summary_ind);
892 release_indicator(&pbdev->routes.adapter, pbdev->indicator);
893
894 pbdev->summary_ind = NULL;
895 pbdev->indicator = NULL;
896 pbdev->routes.adapter.summary_addr = 0;
897 pbdev->routes.adapter.summary_offset = 0;
898 pbdev->routes.adapter.ind_addr = 0;
899 pbdev->routes.adapter.ind_offset = 0;
900 pbdev->isc = 0;
901 pbdev->noi = 0;
902 pbdev->sum = 0;
903
904 DPRINTF("dereg_irqs adapter id %d\n", pbdev->routes.adapter.adapter_id);
905 return 0;
906 }
907
908 static int reg_ioat(CPUS390XState *env, S390PCIIOMMU *iommu, ZpciFib fib,
909 uintptr_t ra)
910 {
911 uint64_t pba = ldq_p(&fib.pba);
912 uint64_t pal = ldq_p(&fib.pal);
913 uint64_t g_iota = ldq_p(&fib.iota);
914 uint8_t dt = (g_iota >> 2) & 0x7;
915 uint8_t t = (g_iota >> 11) & 0x1;
916
917 pba &= ~0xfff;
918 pal |= 0xfff;
919 if (pba > pal || pba < ZPCI_SDMA_ADDR || pal > ZPCI_EDMA_ADDR) {
920 s390_program_interrupt(env, PGM_OPERAND, ra);
921 return -EINVAL;
922 }
923
924 /* currently we only support designation type 1 with translation */
925 if (!(dt == ZPCI_IOTA_RTTO && t)) {
926 error_report("unsupported ioat dt %d t %d", dt, t);
927 s390_program_interrupt(env, PGM_OPERAND, ra);
928 return -EINVAL;
929 }
930
931 iommu->pba = pba;
932 iommu->pal = pal;
933 iommu->g_iota = g_iota;
934
935 s390_pci_iommu_enable(iommu);
936
937 return 0;
938 }
939
940 void pci_dereg_ioat(S390PCIIOMMU *iommu)
941 {
942 s390_pci_iommu_disable(iommu);
943 iommu->pba = 0;
944 iommu->pal = 0;
945 iommu->g_iota = 0;
946 }
947
948 void fmb_timer_free(S390PCIBusDevice *pbdev)
949 {
950 if (pbdev->fmb_timer) {
951 timer_del(pbdev->fmb_timer);
952 timer_free(pbdev->fmb_timer);
953 pbdev->fmb_timer = NULL;
954 }
955 pbdev->fmb_addr = 0;
956 memset(&pbdev->fmb, 0, sizeof(ZpciFmb));
957 }
958
959 static int fmb_do_update(S390PCIBusDevice *pbdev, int offset, uint64_t val,
960 int len)
961 {
962 MemTxResult ret;
963 uint64_t dst = pbdev->fmb_addr + offset;
964
965 switch (len) {
966 case 8:
967 address_space_stq_be(&address_space_memory, dst, val,
968 MEMTXATTRS_UNSPECIFIED,
969 &ret);
970 break;
971 case 4:
972 address_space_stl_be(&address_space_memory, dst, val,
973 MEMTXATTRS_UNSPECIFIED,
974 &ret);
975 break;
976 case 2:
977 address_space_stw_be(&address_space_memory, dst, val,
978 MEMTXATTRS_UNSPECIFIED,
979 &ret);
980 break;
981 case 1:
982 address_space_stb(&address_space_memory, dst, val,
983 MEMTXATTRS_UNSPECIFIED,
984 &ret);
985 break;
986 default:
987 ret = MEMTX_ERROR;
988 break;
989 }
990 if (ret != MEMTX_OK) {
991 s390_pci_generate_error_event(ERR_EVENT_FMBA, pbdev->fh, pbdev->fid,
992 pbdev->fmb_addr, 0);
993 fmb_timer_free(pbdev);
994 }
995
996 return ret;
997 }
998
999 static void fmb_update(void *opaque)
1000 {
1001 S390PCIBusDevice *pbdev = opaque;
1002 int64_t t = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL);
1003 int i;
1004
1005 /* Update U bit */
1006 pbdev->fmb.last_update *= 2;
1007 pbdev->fmb.last_update |= UPDATE_U_BIT;
1008 if (fmb_do_update(pbdev, offsetof(ZpciFmb, last_update),
1009 pbdev->fmb.last_update,
1010 sizeof(pbdev->fmb.last_update))) {
1011 return;
1012 }
1013
1014 /* Update FMB sample count */
1015 if (fmb_do_update(pbdev, offsetof(ZpciFmb, sample),
1016 pbdev->fmb.sample++,
1017 sizeof(pbdev->fmb.sample))) {
1018 return;
1019 }
1020
1021 /* Update FMB counters */
1022 for (i = 0; i < ZPCI_FMB_CNT_MAX; i++) {
1023 if (fmb_do_update(pbdev, offsetof(ZpciFmb, counter[i]),
1024 pbdev->fmb.counter[i],
1025 sizeof(pbdev->fmb.counter[0]))) {
1026 return;
1027 }
1028 }
1029
1030 /* Clear U bit and update the time */
1031 pbdev->fmb.last_update = time2tod(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
1032 pbdev->fmb.last_update *= 2;
1033 if (fmb_do_update(pbdev, offsetof(ZpciFmb, last_update),
1034 pbdev->fmb.last_update,
1035 sizeof(pbdev->fmb.last_update))) {
1036 return;
1037 }
1038 timer_mod(pbdev->fmb_timer, t + DEFAULT_MUI);
1039 }
1040
1041 int mpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar,
1042 uintptr_t ra)
1043 {
1044 CPUS390XState *env = &cpu->env;
1045 uint8_t oc, dmaas;
1046 uint32_t fh;
1047 ZpciFib fib;
1048 S390PCIBusDevice *pbdev;
1049 uint64_t cc = ZPCI_PCI_LS_OK;
1050
1051 if (env->psw.mask & PSW_MASK_PSTATE) {
1052 s390_program_interrupt(env, PGM_PRIVILEGED, ra);
1053 return 0;
1054 }
1055
1056 oc = env->regs[r1] & 0xff;
1057 dmaas = (env->regs[r1] >> 16) & 0xff;
1058 fh = env->regs[r1] >> 32;
1059
1060 if (fiba & 0x7) {
1061 s390_program_interrupt(env, PGM_SPECIFICATION, ra);
1062 return 0;
1063 }
1064
1065 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh);
1066 if (!pbdev) {
1067 DPRINTF("mpcifc no pci dev fh 0x%x\n", fh);
1068 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
1069 return 0;
1070 }
1071
1072 switch (pbdev->state) {
1073 case ZPCI_FS_RESERVED:
1074 case ZPCI_FS_STANDBY:
1075 case ZPCI_FS_DISABLED:
1076 case ZPCI_FS_PERMANENT_ERROR:
1077 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
1078 return 0;
1079 default:
1080 break;
1081 }
1082
1083 if (s390_cpu_virt_mem_read(cpu, fiba, ar, (uint8_t *)&fib, sizeof(fib))) {
1084 s390_cpu_virt_mem_handle_exc(cpu, ra);
1085 return 0;
1086 }
1087
1088 if (fib.fmt != 0) {
1089 s390_program_interrupt(env, PGM_OPERAND, ra);
1090 return 0;
1091 }
1092
1093 switch (oc) {
1094 case ZPCI_MOD_FC_REG_INT:
1095 if (pbdev->summary_ind) {
1096 cc = ZPCI_PCI_LS_ERR;
1097 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
1098 } else if (reg_irqs(env, pbdev, fib)) {
1099 cc = ZPCI_PCI_LS_ERR;
1100 s390_set_status_code(env, r1, ZPCI_MOD_ST_RES_NOT_AVAIL);
1101 }
1102 break;
1103 case ZPCI_MOD_FC_DEREG_INT:
1104 if (!pbdev->summary_ind) {
1105 cc = ZPCI_PCI_LS_ERR;
1106 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
1107 } else {
1108 pci_dereg_irqs(pbdev);
1109 }
1110 break;
1111 case ZPCI_MOD_FC_REG_IOAT:
1112 if (dmaas != 0) {
1113 cc = ZPCI_PCI_LS_ERR;
1114 s390_set_status_code(env, r1, ZPCI_MOD_ST_DMAAS_INVAL);
1115 } else if (pbdev->iommu->enabled) {
1116 cc = ZPCI_PCI_LS_ERR;
1117 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
1118 } else if (reg_ioat(env, pbdev->iommu, fib, ra)) {
1119 cc = ZPCI_PCI_LS_ERR;
1120 s390_set_status_code(env, r1, ZPCI_MOD_ST_INSUF_RES);
1121 }
1122 break;
1123 case ZPCI_MOD_FC_DEREG_IOAT:
1124 if (dmaas != 0) {
1125 cc = ZPCI_PCI_LS_ERR;
1126 s390_set_status_code(env, r1, ZPCI_MOD_ST_DMAAS_INVAL);
1127 } else if (!pbdev->iommu->enabled) {
1128 cc = ZPCI_PCI_LS_ERR;
1129 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
1130 } else {
1131 pci_dereg_ioat(pbdev->iommu);
1132 }
1133 break;
1134 case ZPCI_MOD_FC_REREG_IOAT:
1135 if (dmaas != 0) {
1136 cc = ZPCI_PCI_LS_ERR;
1137 s390_set_status_code(env, r1, ZPCI_MOD_ST_DMAAS_INVAL);
1138 } else if (!pbdev->iommu->enabled) {
1139 cc = ZPCI_PCI_LS_ERR;
1140 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
1141 } else {
1142 pci_dereg_ioat(pbdev->iommu);
1143 if (reg_ioat(env, pbdev->iommu, fib, ra)) {
1144 cc = ZPCI_PCI_LS_ERR;
1145 s390_set_status_code(env, r1, ZPCI_MOD_ST_INSUF_RES);
1146 }
1147 }
1148 break;
1149 case ZPCI_MOD_FC_RESET_ERROR:
1150 switch (pbdev->state) {
1151 case ZPCI_FS_BLOCKED:
1152 case ZPCI_FS_ERROR:
1153 pbdev->state = ZPCI_FS_ENABLED;
1154 break;
1155 default:
1156 cc = ZPCI_PCI_LS_ERR;
1157 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
1158 }
1159 break;
1160 case ZPCI_MOD_FC_RESET_BLOCK:
1161 switch (pbdev->state) {
1162 case ZPCI_FS_ERROR:
1163 pbdev->state = ZPCI_FS_BLOCKED;
1164 break;
1165 default:
1166 cc = ZPCI_PCI_LS_ERR;
1167 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
1168 }
1169 break;
1170 case ZPCI_MOD_FC_SET_MEASURE: {
1171 uint64_t fmb_addr = ldq_p(&fib.fmb_addr);
1172
1173 if (fmb_addr & FMBK_MASK) {
1174 cc = ZPCI_PCI_LS_ERR;
1175 s390_pci_generate_error_event(ERR_EVENT_FMBPRO, pbdev->fh,
1176 pbdev->fid, fmb_addr, 0);
1177 fmb_timer_free(pbdev);
1178 break;
1179 }
1180
1181 if (!fmb_addr) {
1182 /* Stop updating FMB. */
1183 fmb_timer_free(pbdev);
1184 break;
1185 }
1186
1187 if (!pbdev->fmb_timer) {
1188 pbdev->fmb_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL,
1189 fmb_update, pbdev);
1190 } else if (timer_pending(pbdev->fmb_timer)) {
1191 /* Remove pending timer to update FMB address. */
1192 timer_del(pbdev->fmb_timer);
1193 }
1194 pbdev->fmb_addr = fmb_addr;
1195 timer_mod(pbdev->fmb_timer,
1196 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + DEFAULT_MUI);
1197 break;
1198 }
1199 default:
1200 s390_program_interrupt(&cpu->env, PGM_OPERAND, ra);
1201 cc = ZPCI_PCI_LS_ERR;
1202 }
1203
1204 setcc(cpu, cc);
1205 return 0;
1206 }
1207
1208 int stpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar,
1209 uintptr_t ra)
1210 {
1211 CPUS390XState *env = &cpu->env;
1212 uint8_t dmaas;
1213 uint32_t fh;
1214 ZpciFib fib;
1215 S390PCIBusDevice *pbdev;
1216 uint32_t data;
1217 uint64_t cc = ZPCI_PCI_LS_OK;
1218
1219 if (env->psw.mask & PSW_MASK_PSTATE) {
1220 s390_program_interrupt(env, PGM_PRIVILEGED, ra);
1221 return 0;
1222 }
1223
1224 fh = env->regs[r1] >> 32;
1225 dmaas = (env->regs[r1] >> 16) & 0xff;
1226
1227 if (dmaas) {
1228 setcc(cpu, ZPCI_PCI_LS_ERR);
1229 s390_set_status_code(env, r1, ZPCI_STPCIFC_ST_INVAL_DMAAS);
1230 return 0;
1231 }
1232
1233 if (fiba & 0x7) {
1234 s390_program_interrupt(env, PGM_SPECIFICATION, ra);
1235 return 0;
1236 }
1237
1238 pbdev = s390_pci_find_dev_by_idx(s390_get_phb(), fh & FH_MASK_INDEX);
1239 if (!pbdev) {
1240 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
1241 return 0;
1242 }
1243
1244 memset(&fib, 0, sizeof(fib));
1245
1246 switch (pbdev->state) {
1247 case ZPCI_FS_RESERVED:
1248 case ZPCI_FS_STANDBY:
1249 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
1250 return 0;
1251 case ZPCI_FS_DISABLED:
1252 if (fh & FH_MASK_ENABLE) {
1253 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
1254 return 0;
1255 }
1256 goto out;
1257 /* BLOCKED bit is set to one coincident with the setting of ERROR bit.
1258 * FH Enabled bit is set to one in states of ENABLED, BLOCKED or ERROR. */
1259 case ZPCI_FS_ERROR:
1260 fib.fc |= 0x20;
1261 /* fallthrough */
1262 case ZPCI_FS_BLOCKED:
1263 fib.fc |= 0x40;
1264 /* fallthrough */
1265 case ZPCI_FS_ENABLED:
1266 fib.fc |= 0x80;
1267 if (pbdev->iommu->enabled) {
1268 fib.fc |= 0x10;
1269 }
1270 if (!(fh & FH_MASK_ENABLE)) {
1271 env->regs[r1] |= 1ULL << 63;
1272 }
1273 break;
1274 case ZPCI_FS_PERMANENT_ERROR:
1275 setcc(cpu, ZPCI_PCI_LS_ERR);
1276 s390_set_status_code(env, r1, ZPCI_STPCIFC_ST_PERM_ERROR);
1277 return 0;
1278 }
1279
1280 stq_p(&fib.pba, pbdev->iommu->pba);
1281 stq_p(&fib.pal, pbdev->iommu->pal);
1282 stq_p(&fib.iota, pbdev->iommu->g_iota);
1283 stq_p(&fib.aibv, pbdev->routes.adapter.ind_addr);
1284 stq_p(&fib.aisb, pbdev->routes.adapter.summary_addr);
1285 stq_p(&fib.fmb_addr, pbdev->fmb_addr);
1286
1287 data = ((uint32_t)pbdev->isc << 28) | ((uint32_t)pbdev->noi << 16) |
1288 ((uint32_t)pbdev->routes.adapter.ind_offset << 8) |
1289 ((uint32_t)pbdev->sum << 7) | pbdev->routes.adapter.summary_offset;
1290 stl_p(&fib.data, data);
1291
1292 out:
1293 if (s390_cpu_virt_mem_write(cpu, fiba, ar, (uint8_t *)&fib, sizeof(fib))) {
1294 s390_cpu_virt_mem_handle_exc(cpu, ra);
1295 return 0;
1296 }
1297
1298 setcc(cpu, cc);
1299 return 0;
1300 }