esp-pci: fixup deadlock with linux
[qemu.git] / hw / scsi / esp-pci.c
1 /*
2 * QEMU ESP/NCR53C9x emulation
3 *
4 * Copyright (c) 2005-2006 Fabrice Bellard
5 * Copyright (c) 2012 Herve Poussineau
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25
26 #include "hw/pci/pci.h"
27 #include "hw/nvram/eeprom93xx.h"
28 #include "hw/scsi/esp.h"
29 #include "trace.h"
30 #include "qemu/log.h"
31
32 #define TYPE_AM53C974_DEVICE "am53c974"
33
34 #define PCI_ESP(obj) \
35 OBJECT_CHECK(PCIESPState, (obj), TYPE_AM53C974_DEVICE)
36
37 #define DMA_CMD 0x0
38 #define DMA_STC 0x1
39 #define DMA_SPA 0x2
40 #define DMA_WBC 0x3
41 #define DMA_WAC 0x4
42 #define DMA_STAT 0x5
43 #define DMA_SMDLA 0x6
44 #define DMA_WMAC 0x7
45
46 #define DMA_CMD_MASK 0x03
47 #define DMA_CMD_DIAG 0x04
48 #define DMA_CMD_MDL 0x10
49 #define DMA_CMD_INTE_P 0x20
50 #define DMA_CMD_INTE_D 0x40
51 #define DMA_CMD_DIR 0x80
52
53 #define DMA_STAT_PWDN 0x01
54 #define DMA_STAT_ERROR 0x02
55 #define DMA_STAT_ABORT 0x04
56 #define DMA_STAT_DONE 0x08
57 #define DMA_STAT_SCSIINT 0x10
58 #define DMA_STAT_BCMBLT 0x20
59
60 #define SBAC_STATUS 0x1000
61
62 typedef struct PCIESPState {
63 /*< private >*/
64 PCIDevice parent_obj;
65 /*< public >*/
66
67 MemoryRegion io;
68 uint32_t dma_regs[8];
69 uint32_t sbac;
70 ESPState esp;
71 } PCIESPState;
72
73 static void esp_pci_handle_idle(PCIESPState *pci, uint32_t val)
74 {
75 trace_esp_pci_dma_idle(val);
76 esp_dma_enable(&pci->esp, 0, 0);
77 }
78
79 static void esp_pci_handle_blast(PCIESPState *pci, uint32_t val)
80 {
81 trace_esp_pci_dma_blast(val);
82 qemu_log_mask(LOG_UNIMP, "am53c974: cmd BLAST not implemented\n");
83 }
84
85 static void esp_pci_handle_abort(PCIESPState *pci, uint32_t val)
86 {
87 trace_esp_pci_dma_abort(val);
88 if (pci->esp.current_req) {
89 scsi_req_cancel(pci->esp.current_req);
90 }
91 }
92
93 static void esp_pci_handle_start(PCIESPState *pci, uint32_t val)
94 {
95 trace_esp_pci_dma_start(val);
96
97 pci->dma_regs[DMA_WBC] = pci->dma_regs[DMA_STC];
98 pci->dma_regs[DMA_WAC] = pci->dma_regs[DMA_SPA];
99 pci->dma_regs[DMA_WMAC] = pci->dma_regs[DMA_SMDLA];
100
101 pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_BCMBLT | DMA_STAT_SCSIINT
102 | DMA_STAT_DONE | DMA_STAT_ABORT
103 | DMA_STAT_ERROR | DMA_STAT_PWDN);
104
105 esp_dma_enable(&pci->esp, 0, 1);
106 }
107
108 static void esp_pci_dma_write(PCIESPState *pci, uint32_t saddr, uint32_t val)
109 {
110 trace_esp_pci_dma_write(saddr, pci->dma_regs[saddr], val);
111 switch (saddr) {
112 case DMA_CMD:
113 pci->dma_regs[saddr] = val;
114 switch (val & DMA_CMD_MASK) {
115 case 0x0: /* IDLE */
116 esp_pci_handle_idle(pci, val);
117 break;
118 case 0x1: /* BLAST */
119 esp_pci_handle_blast(pci, val);
120 break;
121 case 0x2: /* ABORT */
122 esp_pci_handle_abort(pci, val);
123 break;
124 case 0x3: /* START */
125 esp_pci_handle_start(pci, val);
126 break;
127 default: /* can't happen */
128 abort();
129 }
130 break;
131 case DMA_STC:
132 case DMA_SPA:
133 case DMA_SMDLA:
134 pci->dma_regs[saddr] = val;
135 break;
136 case DMA_STAT:
137 if (!(pci->sbac & SBAC_STATUS)) {
138 /* clear some bits on write */
139 uint32_t mask = DMA_STAT_ERROR | DMA_STAT_ABORT | DMA_STAT_DONE;
140 pci->dma_regs[DMA_STAT] &= ~(val & mask);
141 }
142 break;
143 default:
144 trace_esp_pci_error_invalid_write_dma(val, saddr);
145 return;
146 }
147 }
148
149 static uint32_t esp_pci_dma_read(PCIESPState *pci, uint32_t saddr)
150 {
151 uint32_t val;
152
153 val = pci->dma_regs[saddr];
154 if (saddr == DMA_STAT) {
155 if (pci->esp.rregs[ESP_RSTAT] & STAT_INT) {
156 val |= DMA_STAT_SCSIINT;
157 }
158 if (pci->sbac & SBAC_STATUS) {
159 pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_ERROR | DMA_STAT_ABORT |
160 DMA_STAT_DONE);
161 }
162 }
163
164 trace_esp_pci_dma_read(saddr, val);
165 return val;
166 }
167
168 static void esp_pci_io_write(void *opaque, hwaddr addr,
169 uint64_t val, unsigned int size)
170 {
171 PCIESPState *pci = opaque;
172
173 if (size < 4 || addr & 3) {
174 /* need to upgrade request: we only support 4-bytes accesses */
175 uint32_t current = 0, mask;
176 int shift;
177
178 if (addr < 0x40) {
179 current = pci->esp.wregs[addr >> 2];
180 } else if (addr < 0x60) {
181 current = pci->dma_regs[(addr - 0x40) >> 2];
182 } else if (addr < 0x74) {
183 current = pci->sbac;
184 }
185
186 shift = (4 - size) * 8;
187 mask = (~(uint32_t)0 << shift) >> shift;
188
189 shift = ((4 - (addr & 3)) & 3) * 8;
190 val <<= shift;
191 val |= current & ~(mask << shift);
192 addr &= ~3;
193 size = 4;
194 }
195
196 if (addr < 0x40) {
197 /* SCSI core reg */
198 esp_reg_write(&pci->esp, addr >> 2, val);
199 } else if (addr < 0x60) {
200 /* PCI DMA CCB */
201 esp_pci_dma_write(pci, (addr - 0x40) >> 2, val);
202 } else if (addr == 0x70) {
203 /* DMA SCSI Bus and control */
204 trace_esp_pci_sbac_write(pci->sbac, val);
205 pci->sbac = val;
206 } else {
207 trace_esp_pci_error_invalid_write((int)addr);
208 }
209 }
210
211 static uint64_t esp_pci_io_read(void *opaque, hwaddr addr,
212 unsigned int size)
213 {
214 PCIESPState *pci = opaque;
215 uint32_t ret;
216
217 if (addr < 0x40) {
218 /* SCSI core reg */
219 ret = esp_reg_read(&pci->esp, addr >> 2);
220 } else if (addr < 0x60) {
221 /* PCI DMA CCB */
222 ret = esp_pci_dma_read(pci, (addr - 0x40) >> 2);
223 } else if (addr == 0x70) {
224 /* DMA SCSI Bus and control */
225 trace_esp_pci_sbac_read(pci->sbac);
226 ret = pci->sbac;
227 } else {
228 /* Invalid region */
229 trace_esp_pci_error_invalid_read((int)addr);
230 ret = 0;
231 }
232
233 /* give only requested data */
234 ret >>= (addr & 3) * 8;
235 ret &= ~(~(uint64_t)0 << (8 * size));
236
237 return ret;
238 }
239
240 static void esp_pci_dma_memory_rw(PCIESPState *pci, uint8_t *buf, int len,
241 DMADirection dir)
242 {
243 dma_addr_t addr;
244 DMADirection expected_dir;
245
246 if (pci->dma_regs[DMA_CMD] & DMA_CMD_DIR) {
247 expected_dir = DMA_DIRECTION_FROM_DEVICE;
248 } else {
249 expected_dir = DMA_DIRECTION_TO_DEVICE;
250 }
251
252 if (dir != expected_dir) {
253 trace_esp_pci_error_invalid_dma_direction();
254 return;
255 }
256
257 if (pci->dma_regs[DMA_STAT] & DMA_CMD_MDL) {
258 qemu_log_mask(LOG_UNIMP, "am53c974: MDL transfer not implemented\n");
259 }
260
261 addr = pci->dma_regs[DMA_SPA];
262 if (pci->dma_regs[DMA_WBC] < len) {
263 len = pci->dma_regs[DMA_WBC];
264 }
265
266 pci_dma_rw(PCI_DEVICE(pci), addr, buf, len, dir);
267
268 /* update status registers */
269 pci->dma_regs[DMA_WBC] -= len;
270 pci->dma_regs[DMA_WAC] += len;
271 if (pci->dma_regs[DMA_WBC] == 0)
272 pci->dma_regs[DMA_STAT] |= DMA_STAT_DONE;
273 }
274
275 static void esp_pci_dma_memory_read(void *opaque, uint8_t *buf, int len)
276 {
277 PCIESPState *pci = opaque;
278 esp_pci_dma_memory_rw(pci, buf, len, DMA_DIRECTION_TO_DEVICE);
279 }
280
281 static void esp_pci_dma_memory_write(void *opaque, uint8_t *buf, int len)
282 {
283 PCIESPState *pci = opaque;
284 esp_pci_dma_memory_rw(pci, buf, len, DMA_DIRECTION_FROM_DEVICE);
285 }
286
287 static const MemoryRegionOps esp_pci_io_ops = {
288 .read = esp_pci_io_read,
289 .write = esp_pci_io_write,
290 .endianness = DEVICE_LITTLE_ENDIAN,
291 .impl = {
292 .min_access_size = 1,
293 .max_access_size = 4,
294 },
295 };
296
297 static void esp_pci_hard_reset(DeviceState *dev)
298 {
299 PCIESPState *pci = PCI_ESP(dev);
300 esp_hard_reset(&pci->esp);
301 pci->dma_regs[DMA_CMD] &= ~(DMA_CMD_DIR | DMA_CMD_INTE_D | DMA_CMD_INTE_P
302 | DMA_CMD_MDL | DMA_CMD_DIAG | DMA_CMD_MASK);
303 pci->dma_regs[DMA_WBC] &= ~0xffff;
304 pci->dma_regs[DMA_WAC] = 0xffffffff;
305 pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_BCMBLT | DMA_STAT_SCSIINT
306 | DMA_STAT_DONE | DMA_STAT_ABORT
307 | DMA_STAT_ERROR);
308 pci->dma_regs[DMA_WMAC] = 0xfffffffd;
309 }
310
311 static const VMStateDescription vmstate_esp_pci_scsi = {
312 .name = "pciespscsi",
313 .version_id = 0,
314 .minimum_version_id = 0,
315 .fields = (VMStateField[]) {
316 VMSTATE_PCI_DEVICE(parent_obj, PCIESPState),
317 VMSTATE_BUFFER_UNSAFE(dma_regs, PCIESPState, 0, 8 * sizeof(uint32_t)),
318 VMSTATE_STRUCT(esp, PCIESPState, 0, vmstate_esp, ESPState),
319 VMSTATE_END_OF_LIST()
320 }
321 };
322
323 static void esp_pci_command_complete(SCSIRequest *req, uint32_t status,
324 size_t resid)
325 {
326 ESPState *s = req->hba_private;
327 PCIESPState *pci = container_of(s, PCIESPState, esp);
328
329 esp_command_complete(req, status, resid);
330 pci->dma_regs[DMA_WBC] = 0;
331 pci->dma_regs[DMA_STAT] |= DMA_STAT_DONE;
332 }
333
334 static const struct SCSIBusInfo esp_pci_scsi_info = {
335 .tcq = false,
336 .max_target = ESP_MAX_DEVS,
337 .max_lun = 7,
338
339 .transfer_data = esp_transfer_data,
340 .complete = esp_pci_command_complete,
341 .cancel = esp_request_cancelled,
342 };
343
344 static int esp_pci_scsi_init(PCIDevice *dev)
345 {
346 PCIESPState *pci = PCI_ESP(dev);
347 DeviceState *d = DEVICE(dev);
348 ESPState *s = &pci->esp;
349 uint8_t *pci_conf;
350 Error *err = NULL;
351
352 pci_conf = dev->config;
353
354 /* Interrupt pin A */
355 pci_conf[PCI_INTERRUPT_PIN] = 0x01;
356
357 s->dma_memory_read = esp_pci_dma_memory_read;
358 s->dma_memory_write = esp_pci_dma_memory_write;
359 s->dma_opaque = pci;
360 s->chip_id = TCHI_AM53C974;
361 memory_region_init_io(&pci->io, OBJECT(pci), &esp_pci_io_ops, pci,
362 "esp-io", 0x80);
363
364 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->io);
365 s->irq = pci_allocate_irq(dev);
366
367 scsi_bus_new(&s->bus, sizeof(s->bus), d, &esp_pci_scsi_info, NULL);
368 if (!d->hotplugged) {
369 scsi_bus_legacy_handle_cmdline(&s->bus, &err);
370 if (err != NULL) {
371 error_free(err);
372 return -1;
373 }
374 }
375 return 0;
376 }
377
378 static void esp_pci_scsi_uninit(PCIDevice *d)
379 {
380 PCIESPState *pci = PCI_ESP(d);
381
382 qemu_free_irq(pci->esp.irq);
383 }
384
385 static void esp_pci_class_init(ObjectClass *klass, void *data)
386 {
387 DeviceClass *dc = DEVICE_CLASS(klass);
388 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
389
390 k->init = esp_pci_scsi_init;
391 k->exit = esp_pci_scsi_uninit;
392 k->vendor_id = PCI_VENDOR_ID_AMD;
393 k->device_id = PCI_DEVICE_ID_AMD_SCSI;
394 k->revision = 0x10;
395 k->class_id = PCI_CLASS_STORAGE_SCSI;
396 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
397 dc->desc = "AMD Am53c974 PCscsi-PCI SCSI adapter";
398 dc->reset = esp_pci_hard_reset;
399 dc->vmsd = &vmstate_esp_pci_scsi;
400 }
401
402 static const TypeInfo esp_pci_info = {
403 .name = TYPE_AM53C974_DEVICE,
404 .parent = TYPE_PCI_DEVICE,
405 .instance_size = sizeof(PCIESPState),
406 .class_init = esp_pci_class_init,
407 };
408
409 typedef struct {
410 PCIESPState pci;
411 eeprom_t *eeprom;
412 } DC390State;
413
414 #define TYPE_DC390_DEVICE "dc390"
415 #define DC390(obj) \
416 OBJECT_CHECK(DC390State, obj, TYPE_DC390_DEVICE)
417
418 #define EE_ADAPT_SCSI_ID 64
419 #define EE_MODE2 65
420 #define EE_DELAY 66
421 #define EE_TAG_CMD_NUM 67
422 #define EE_ADAPT_OPTIONS 68
423 #define EE_BOOT_SCSI_ID 69
424 #define EE_BOOT_SCSI_LUN 70
425 #define EE_CHKSUM1 126
426 #define EE_CHKSUM2 127
427
428 #define EE_ADAPT_OPTION_F6_F8_AT_BOOT 0x01
429 #define EE_ADAPT_OPTION_BOOT_FROM_CDROM 0x02
430 #define EE_ADAPT_OPTION_INT13 0x04
431 #define EE_ADAPT_OPTION_SCAM_SUPPORT 0x08
432
433
434 static uint32_t dc390_read_config(PCIDevice *dev, uint32_t addr, int l)
435 {
436 DC390State *pci = DC390(dev);
437 uint32_t val;
438
439 val = pci_default_read_config(dev, addr, l);
440
441 if (addr == 0x00 && l == 1) {
442 /* First byte of address space is AND-ed with EEPROM DO line */
443 if (!eeprom93xx_read(pci->eeprom)) {
444 val &= ~0xff;
445 }
446 }
447
448 return val;
449 }
450
451 static void dc390_write_config(PCIDevice *dev,
452 uint32_t addr, uint32_t val, int l)
453 {
454 DC390State *pci = DC390(dev);
455 if (addr == 0x80) {
456 /* EEPROM write */
457 int eesk = val & 0x80 ? 1 : 0;
458 int eedi = val & 0x40 ? 1 : 0;
459 eeprom93xx_write(pci->eeprom, 1, eesk, eedi);
460 } else if (addr == 0xc0) {
461 /* EEPROM CS low */
462 eeprom93xx_write(pci->eeprom, 0, 0, 0);
463 } else {
464 pci_default_write_config(dev, addr, val, l);
465 }
466 }
467
468 static int dc390_scsi_init(PCIDevice *dev)
469 {
470 DC390State *pci = DC390(dev);
471 uint8_t *contents;
472 uint16_t chksum = 0;
473 int i, ret;
474
475 /* init base class */
476 ret = esp_pci_scsi_init(dev);
477 if (ret < 0) {
478 return ret;
479 }
480
481 /* EEPROM */
482 pci->eeprom = eeprom93xx_new(DEVICE(dev), 64);
483
484 /* set default eeprom values */
485 contents = (uint8_t *)eeprom93xx_data(pci->eeprom);
486
487 for (i = 0; i < 16; i++) {
488 contents[i * 2] = 0x57;
489 contents[i * 2 + 1] = 0x00;
490 }
491 contents[EE_ADAPT_SCSI_ID] = 7;
492 contents[EE_MODE2] = 0x0f;
493 contents[EE_TAG_CMD_NUM] = 0x04;
494 contents[EE_ADAPT_OPTIONS] = EE_ADAPT_OPTION_F6_F8_AT_BOOT
495 | EE_ADAPT_OPTION_BOOT_FROM_CDROM
496 | EE_ADAPT_OPTION_INT13;
497
498 /* update eeprom checksum */
499 for (i = 0; i < EE_CHKSUM1; i += 2) {
500 chksum += contents[i] + (((uint16_t)contents[i + 1]) << 8);
501 }
502 chksum = 0x1234 - chksum;
503 contents[EE_CHKSUM1] = chksum & 0xff;
504 contents[EE_CHKSUM2] = chksum >> 8;
505
506 return 0;
507 }
508
509 static void dc390_class_init(ObjectClass *klass, void *data)
510 {
511 DeviceClass *dc = DEVICE_CLASS(klass);
512 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
513
514 k->init = dc390_scsi_init;
515 k->config_read = dc390_read_config;
516 k->config_write = dc390_write_config;
517 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
518 dc->desc = "Tekram DC-390 SCSI adapter";
519 }
520
521 static const TypeInfo dc390_info = {
522 .name = "dc390",
523 .parent = TYPE_AM53C974_DEVICE,
524 .instance_size = sizeof(DC390State),
525 .class_init = dc390_class_init,
526 };
527
528 static void esp_pci_register_types(void)
529 {
530 type_register_static(&esp_pci_info);
531 type_register_static(&dc390_info);
532 }
533
534 type_init(esp_pci_register_types)