sm501: Add missing arbitration control register
[qemu.git] / hw / scsi / esp.c
1 /*
2 * QEMU ESP/NCR53C9x emulation
3 *
4 * Copyright (c) 2005-2006 Fabrice Bellard
5 * Copyright (c) 2012 Herve Poussineau
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25
26 #include "qemu/osdep.h"
27 #include "hw/sysbus.h"
28 #include "hw/scsi/esp.h"
29 #include "trace.h"
30 #include "qapi/error.h"
31 #include "qemu/log.h"
32
33 /*
34 * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O),
35 * also produced as NCR89C100. See
36 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
37 * and
38 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt
39 */
40
41 static void esp_raise_irq(ESPState *s)
42 {
43 if (!(s->rregs[ESP_RSTAT] & STAT_INT)) {
44 s->rregs[ESP_RSTAT] |= STAT_INT;
45 qemu_irq_raise(s->irq);
46 trace_esp_raise_irq();
47 }
48 }
49
50 static void esp_lower_irq(ESPState *s)
51 {
52 if (s->rregs[ESP_RSTAT] & STAT_INT) {
53 s->rregs[ESP_RSTAT] &= ~STAT_INT;
54 qemu_irq_lower(s->irq);
55 trace_esp_lower_irq();
56 }
57 }
58
59 void esp_dma_enable(ESPState *s, int irq, int level)
60 {
61 if (level) {
62 s->dma_enabled = 1;
63 trace_esp_dma_enable();
64 if (s->dma_cb) {
65 s->dma_cb(s);
66 s->dma_cb = NULL;
67 }
68 } else {
69 trace_esp_dma_disable();
70 s->dma_enabled = 0;
71 }
72 }
73
74 void esp_request_cancelled(SCSIRequest *req)
75 {
76 ESPState *s = req->hba_private;
77
78 if (req == s->current_req) {
79 scsi_req_unref(s->current_req);
80 s->current_req = NULL;
81 s->current_dev = NULL;
82 }
83 }
84
85 static uint32_t get_cmd(ESPState *s, uint8_t *buf, uint8_t buflen)
86 {
87 uint32_t dmalen;
88 int target;
89
90 target = s->wregs[ESP_WBUSID] & BUSID_DID;
91 if (s->dma) {
92 dmalen = s->rregs[ESP_TCLO];
93 dmalen |= s->rregs[ESP_TCMID] << 8;
94 dmalen |= s->rregs[ESP_TCHI] << 16;
95 if (dmalen > buflen) {
96 return 0;
97 }
98 s->dma_memory_read(s->dma_opaque, buf, dmalen);
99 } else {
100 dmalen = s->ti_size;
101 if (dmalen > TI_BUFSZ) {
102 return 0;
103 }
104 memcpy(buf, s->ti_buf, dmalen);
105 buf[0] = buf[2] >> 5;
106 }
107 trace_esp_get_cmd(dmalen, target);
108
109 s->ti_size = 0;
110 s->ti_rptr = 0;
111 s->ti_wptr = 0;
112
113 if (s->current_req) {
114 /* Started a new command before the old one finished. Cancel it. */
115 scsi_req_cancel(s->current_req);
116 s->async_len = 0;
117 }
118
119 s->current_dev = scsi_device_find(&s->bus, 0, target, 0);
120 if (!s->current_dev) {
121 // No such drive
122 s->rregs[ESP_RSTAT] = 0;
123 s->rregs[ESP_RINTR] = INTR_DC;
124 s->rregs[ESP_RSEQ] = SEQ_0;
125 esp_raise_irq(s);
126 return 0;
127 }
128 return dmalen;
129 }
130
131 static void do_busid_cmd(ESPState *s, uint8_t *buf, uint8_t busid)
132 {
133 int32_t datalen;
134 int lun;
135 SCSIDevice *current_lun;
136
137 trace_esp_do_busid_cmd(busid);
138 lun = busid & 7;
139 current_lun = scsi_device_find(&s->bus, 0, s->current_dev->id, lun);
140 s->current_req = scsi_req_new(current_lun, 0, lun, buf, s);
141 datalen = scsi_req_enqueue(s->current_req);
142 s->ti_size = datalen;
143 if (datalen != 0) {
144 s->rregs[ESP_RSTAT] = STAT_TC;
145 s->dma_left = 0;
146 s->dma_counter = 0;
147 if (datalen > 0) {
148 s->rregs[ESP_RSTAT] |= STAT_DI;
149 } else {
150 s->rregs[ESP_RSTAT] |= STAT_DO;
151 }
152 scsi_req_continue(s->current_req);
153 }
154 s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
155 s->rregs[ESP_RSEQ] = SEQ_CD;
156 esp_raise_irq(s);
157 }
158
159 static void do_cmd(ESPState *s, uint8_t *buf)
160 {
161 uint8_t busid = buf[0];
162
163 do_busid_cmd(s, &buf[1], busid);
164 }
165
166 static void handle_satn(ESPState *s)
167 {
168 uint8_t buf[32];
169 int len;
170
171 if (s->dma && !s->dma_enabled) {
172 s->dma_cb = handle_satn;
173 return;
174 }
175 len = get_cmd(s, buf, sizeof(buf));
176 if (len)
177 do_cmd(s, buf);
178 }
179
180 static void handle_s_without_atn(ESPState *s)
181 {
182 uint8_t buf[32];
183 int len;
184
185 if (s->dma && !s->dma_enabled) {
186 s->dma_cb = handle_s_without_atn;
187 return;
188 }
189 len = get_cmd(s, buf, sizeof(buf));
190 if (len) {
191 do_busid_cmd(s, buf, 0);
192 }
193 }
194
195 static void handle_satn_stop(ESPState *s)
196 {
197 if (s->dma && !s->dma_enabled) {
198 s->dma_cb = handle_satn_stop;
199 return;
200 }
201 s->cmdlen = get_cmd(s, s->cmdbuf, sizeof(s->cmdbuf));
202 if (s->cmdlen) {
203 trace_esp_handle_satn_stop(s->cmdlen);
204 s->do_cmd = 1;
205 s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD;
206 s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
207 s->rregs[ESP_RSEQ] = SEQ_CD;
208 esp_raise_irq(s);
209 }
210 }
211
212 static void write_response(ESPState *s)
213 {
214 trace_esp_write_response(s->status);
215 s->ti_buf[0] = s->status;
216 s->ti_buf[1] = 0;
217 if (s->dma) {
218 s->dma_memory_write(s->dma_opaque, s->ti_buf, 2);
219 s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST;
220 s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
221 s->rregs[ESP_RSEQ] = SEQ_CD;
222 } else {
223 s->ti_size = 2;
224 s->ti_rptr = 0;
225 s->ti_wptr = 2;
226 s->rregs[ESP_RFLAGS] = 2;
227 }
228 esp_raise_irq(s);
229 }
230
231 static void esp_dma_done(ESPState *s)
232 {
233 s->rregs[ESP_RSTAT] |= STAT_TC;
234 s->rregs[ESP_RINTR] = INTR_BS;
235 s->rregs[ESP_RSEQ] = 0;
236 s->rregs[ESP_RFLAGS] = 0;
237 s->rregs[ESP_TCLO] = 0;
238 s->rregs[ESP_TCMID] = 0;
239 s->rregs[ESP_TCHI] = 0;
240 esp_raise_irq(s);
241 }
242
243 static void esp_do_dma(ESPState *s)
244 {
245 uint32_t len;
246 int to_device;
247
248 len = s->dma_left;
249 if (s->do_cmd) {
250 trace_esp_do_dma(s->cmdlen, len);
251 assert (s->cmdlen <= sizeof(s->cmdbuf) &&
252 len <= sizeof(s->cmdbuf) - s->cmdlen);
253 s->dma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len);
254 return;
255 }
256 if (s->async_len == 0) {
257 /* Defer until data is available. */
258 return;
259 }
260 if (len > s->async_len) {
261 len = s->async_len;
262 }
263 to_device = (s->ti_size < 0);
264 if (to_device) {
265 s->dma_memory_read(s->dma_opaque, s->async_buf, len);
266 } else {
267 s->dma_memory_write(s->dma_opaque, s->async_buf, len);
268 }
269 s->dma_left -= len;
270 s->async_buf += len;
271 s->async_len -= len;
272 if (to_device)
273 s->ti_size += len;
274 else
275 s->ti_size -= len;
276 if (s->async_len == 0) {
277 scsi_req_continue(s->current_req);
278 /* If there is still data to be read from the device then
279 complete the DMA operation immediately. Otherwise defer
280 until the scsi layer has completed. */
281 if (to_device || s->dma_left != 0 || s->ti_size == 0) {
282 return;
283 }
284 }
285
286 /* Partially filled a scsi buffer. Complete immediately. */
287 esp_dma_done(s);
288 }
289
290 void esp_command_complete(SCSIRequest *req, uint32_t status,
291 size_t resid)
292 {
293 ESPState *s = req->hba_private;
294
295 trace_esp_command_complete();
296 if (s->ti_size != 0) {
297 trace_esp_command_complete_unexpected();
298 }
299 s->ti_size = 0;
300 s->dma_left = 0;
301 s->async_len = 0;
302 if (status) {
303 trace_esp_command_complete_fail();
304 }
305 s->status = status;
306 s->rregs[ESP_RSTAT] = STAT_ST;
307 esp_dma_done(s);
308 if (s->current_req) {
309 scsi_req_unref(s->current_req);
310 s->current_req = NULL;
311 s->current_dev = NULL;
312 }
313 }
314
315 void esp_transfer_data(SCSIRequest *req, uint32_t len)
316 {
317 ESPState *s = req->hba_private;
318
319 assert(!s->do_cmd);
320 trace_esp_transfer_data(s->dma_left, s->ti_size);
321 s->async_len = len;
322 s->async_buf = scsi_req_get_buf(req);
323 if (s->dma_left) {
324 esp_do_dma(s);
325 } else if (s->dma_counter != 0 && s->ti_size <= 0) {
326 /* If this was the last part of a DMA transfer then the
327 completion interrupt is deferred to here. */
328 esp_dma_done(s);
329 }
330 }
331
332 static void handle_ti(ESPState *s)
333 {
334 uint32_t dmalen, minlen;
335
336 if (s->dma && !s->dma_enabled) {
337 s->dma_cb = handle_ti;
338 return;
339 }
340
341 dmalen = s->rregs[ESP_TCLO];
342 dmalen |= s->rregs[ESP_TCMID] << 8;
343 dmalen |= s->rregs[ESP_TCHI] << 16;
344 if (dmalen==0) {
345 dmalen=0x10000;
346 }
347 s->dma_counter = dmalen;
348
349 if (s->do_cmd)
350 minlen = (dmalen < ESP_CMDBUF_SZ) ? dmalen : ESP_CMDBUF_SZ;
351 else if (s->ti_size < 0)
352 minlen = (dmalen < -s->ti_size) ? dmalen : -s->ti_size;
353 else
354 minlen = (dmalen < s->ti_size) ? dmalen : s->ti_size;
355 trace_esp_handle_ti(minlen);
356 if (s->dma) {
357 s->dma_left = minlen;
358 s->rregs[ESP_RSTAT] &= ~STAT_TC;
359 esp_do_dma(s);
360 }
361 if (s->do_cmd) {
362 trace_esp_handle_ti_cmd(s->cmdlen);
363 s->ti_size = 0;
364 s->cmdlen = 0;
365 s->do_cmd = 0;
366 do_cmd(s, s->cmdbuf);
367 }
368 }
369
370 void esp_hard_reset(ESPState *s)
371 {
372 memset(s->rregs, 0, ESP_REGS);
373 memset(s->wregs, 0, ESP_REGS);
374 s->tchi_written = 0;
375 s->ti_size = 0;
376 s->ti_rptr = 0;
377 s->ti_wptr = 0;
378 s->dma = 0;
379 s->do_cmd = 0;
380 s->dma_cb = NULL;
381
382 s->rregs[ESP_CFG1] = 7;
383 }
384
385 static void esp_soft_reset(ESPState *s)
386 {
387 qemu_irq_lower(s->irq);
388 esp_hard_reset(s);
389 }
390
391 static void parent_esp_reset(ESPState *s, int irq, int level)
392 {
393 if (level) {
394 esp_soft_reset(s);
395 }
396 }
397
398 uint64_t esp_reg_read(ESPState *s, uint32_t saddr)
399 {
400 uint32_t old_val;
401
402 trace_esp_mem_readb(saddr, s->rregs[saddr]);
403 switch (saddr) {
404 case ESP_FIFO:
405 if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) {
406 /* Data out. */
407 qemu_log_mask(LOG_UNIMP, "esp: PIO data read not implemented\n");
408 s->rregs[ESP_FIFO] = 0;
409 } else if (s->ti_rptr < s->ti_wptr) {
410 s->ti_size--;
411 s->rregs[ESP_FIFO] = s->ti_buf[s->ti_rptr++];
412 }
413 if (s->ti_rptr == s->ti_wptr) {
414 s->ti_rptr = 0;
415 s->ti_wptr = 0;
416 }
417 break;
418 case ESP_RINTR:
419 /* Clear sequence step, interrupt register and all status bits
420 except TC */
421 old_val = s->rregs[ESP_RINTR];
422 s->rregs[ESP_RINTR] = 0;
423 s->rregs[ESP_RSTAT] &= ~STAT_TC;
424 s->rregs[ESP_RSEQ] = SEQ_CD;
425 esp_lower_irq(s);
426
427 return old_val;
428 case ESP_TCHI:
429 /* Return the unique id if the value has never been written */
430 if (!s->tchi_written) {
431 return s->chip_id;
432 }
433 default:
434 break;
435 }
436 return s->rregs[saddr];
437 }
438
439 void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val)
440 {
441 trace_esp_mem_writeb(saddr, s->wregs[saddr], val);
442 switch (saddr) {
443 case ESP_TCHI:
444 s->tchi_written = true;
445 /* fall through */
446 case ESP_TCLO:
447 case ESP_TCMID:
448 s->rregs[ESP_RSTAT] &= ~STAT_TC;
449 break;
450 case ESP_FIFO:
451 if (s->do_cmd) {
452 if (s->cmdlen < ESP_CMDBUF_SZ) {
453 s->cmdbuf[s->cmdlen++] = val & 0xff;
454 } else {
455 trace_esp_error_fifo_overrun();
456 }
457 } else if (s->ti_wptr == TI_BUFSZ - 1) {
458 trace_esp_error_fifo_overrun();
459 } else {
460 s->ti_size++;
461 s->ti_buf[s->ti_wptr++] = val & 0xff;
462 }
463 break;
464 case ESP_CMD:
465 s->rregs[saddr] = val;
466 if (val & CMD_DMA) {
467 s->dma = 1;
468 /* Reload DMA counter. */
469 s->rregs[ESP_TCLO] = s->wregs[ESP_TCLO];
470 s->rregs[ESP_TCMID] = s->wregs[ESP_TCMID];
471 s->rregs[ESP_TCHI] = s->wregs[ESP_TCHI];
472 } else {
473 s->dma = 0;
474 }
475 switch(val & CMD_CMD) {
476 case CMD_NOP:
477 trace_esp_mem_writeb_cmd_nop(val);
478 break;
479 case CMD_FLUSH:
480 trace_esp_mem_writeb_cmd_flush(val);
481 //s->ti_size = 0;
482 s->rregs[ESP_RINTR] = INTR_FC;
483 s->rregs[ESP_RSEQ] = 0;
484 s->rregs[ESP_RFLAGS] = 0;
485 break;
486 case CMD_RESET:
487 trace_esp_mem_writeb_cmd_reset(val);
488 esp_soft_reset(s);
489 break;
490 case CMD_BUSRESET:
491 trace_esp_mem_writeb_cmd_bus_reset(val);
492 s->rregs[ESP_RINTR] = INTR_RST;
493 if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) {
494 esp_raise_irq(s);
495 }
496 break;
497 case CMD_TI:
498 handle_ti(s);
499 break;
500 case CMD_ICCS:
501 trace_esp_mem_writeb_cmd_iccs(val);
502 write_response(s);
503 s->rregs[ESP_RINTR] = INTR_FC;
504 s->rregs[ESP_RSTAT] |= STAT_MI;
505 break;
506 case CMD_MSGACC:
507 trace_esp_mem_writeb_cmd_msgacc(val);
508 s->rregs[ESP_RINTR] = INTR_DC;
509 s->rregs[ESP_RSEQ] = 0;
510 s->rregs[ESP_RFLAGS] = 0;
511 esp_raise_irq(s);
512 break;
513 case CMD_PAD:
514 trace_esp_mem_writeb_cmd_pad(val);
515 s->rregs[ESP_RSTAT] = STAT_TC;
516 s->rregs[ESP_RINTR] = INTR_FC;
517 s->rregs[ESP_RSEQ] = 0;
518 break;
519 case CMD_SATN:
520 trace_esp_mem_writeb_cmd_satn(val);
521 break;
522 case CMD_RSTATN:
523 trace_esp_mem_writeb_cmd_rstatn(val);
524 break;
525 case CMD_SEL:
526 trace_esp_mem_writeb_cmd_sel(val);
527 handle_s_without_atn(s);
528 break;
529 case CMD_SELATN:
530 trace_esp_mem_writeb_cmd_selatn(val);
531 handle_satn(s);
532 break;
533 case CMD_SELATNS:
534 trace_esp_mem_writeb_cmd_selatns(val);
535 handle_satn_stop(s);
536 break;
537 case CMD_ENSEL:
538 trace_esp_mem_writeb_cmd_ensel(val);
539 s->rregs[ESP_RINTR] = 0;
540 break;
541 case CMD_DISSEL:
542 trace_esp_mem_writeb_cmd_dissel(val);
543 s->rregs[ESP_RINTR] = 0;
544 esp_raise_irq(s);
545 break;
546 default:
547 trace_esp_error_unhandled_command(val);
548 break;
549 }
550 break;
551 case ESP_WBUSID ... ESP_WSYNO:
552 break;
553 case ESP_CFG1:
554 case ESP_CFG2: case ESP_CFG3:
555 case ESP_RES3: case ESP_RES4:
556 s->rregs[saddr] = val;
557 break;
558 case ESP_WCCF ... ESP_WTEST:
559 break;
560 default:
561 trace_esp_error_invalid_write(val, saddr);
562 return;
563 }
564 s->wregs[saddr] = val;
565 }
566
567 static bool esp_mem_accepts(void *opaque, hwaddr addr,
568 unsigned size, bool is_write)
569 {
570 return (size == 1) || (is_write && size == 4);
571 }
572
573 const VMStateDescription vmstate_esp = {
574 .name ="esp",
575 .version_id = 4,
576 .minimum_version_id = 3,
577 .fields = (VMStateField[]) {
578 VMSTATE_BUFFER(rregs, ESPState),
579 VMSTATE_BUFFER(wregs, ESPState),
580 VMSTATE_INT32(ti_size, ESPState),
581 VMSTATE_UINT32(ti_rptr, ESPState),
582 VMSTATE_UINT32(ti_wptr, ESPState),
583 VMSTATE_BUFFER(ti_buf, ESPState),
584 VMSTATE_UINT32(status, ESPState),
585 VMSTATE_UINT32(dma, ESPState),
586 VMSTATE_PARTIAL_BUFFER(cmdbuf, ESPState, 16),
587 VMSTATE_BUFFER_START_MIDDLE_V(cmdbuf, ESPState, 16, 4),
588 VMSTATE_UINT32(cmdlen, ESPState),
589 VMSTATE_UINT32(do_cmd, ESPState),
590 VMSTATE_UINT32(dma_left, ESPState),
591 VMSTATE_END_OF_LIST()
592 }
593 };
594
595 #define TYPE_ESP "esp"
596 #define ESP(obj) OBJECT_CHECK(SysBusESPState, (obj), TYPE_ESP)
597
598 typedef struct {
599 /*< private >*/
600 SysBusDevice parent_obj;
601 /*< public >*/
602
603 MemoryRegion iomem;
604 uint32_t it_shift;
605 ESPState esp;
606 } SysBusESPState;
607
608 static void sysbus_esp_mem_write(void *opaque, hwaddr addr,
609 uint64_t val, unsigned int size)
610 {
611 SysBusESPState *sysbus = opaque;
612 uint32_t saddr;
613
614 saddr = addr >> sysbus->it_shift;
615 esp_reg_write(&sysbus->esp, saddr, val);
616 }
617
618 static uint64_t sysbus_esp_mem_read(void *opaque, hwaddr addr,
619 unsigned int size)
620 {
621 SysBusESPState *sysbus = opaque;
622 uint32_t saddr;
623
624 saddr = addr >> sysbus->it_shift;
625 return esp_reg_read(&sysbus->esp, saddr);
626 }
627
628 static const MemoryRegionOps sysbus_esp_mem_ops = {
629 .read = sysbus_esp_mem_read,
630 .write = sysbus_esp_mem_write,
631 .endianness = DEVICE_NATIVE_ENDIAN,
632 .valid.accepts = esp_mem_accepts,
633 };
634
635 void esp_init(hwaddr espaddr, int it_shift,
636 ESPDMAMemoryReadWriteFunc dma_memory_read,
637 ESPDMAMemoryReadWriteFunc dma_memory_write,
638 void *dma_opaque, qemu_irq irq, qemu_irq *reset,
639 qemu_irq *dma_enable)
640 {
641 DeviceState *dev;
642 SysBusDevice *s;
643 SysBusESPState *sysbus;
644 ESPState *esp;
645
646 dev = qdev_create(NULL, TYPE_ESP);
647 sysbus = ESP(dev);
648 esp = &sysbus->esp;
649 esp->dma_memory_read = dma_memory_read;
650 esp->dma_memory_write = dma_memory_write;
651 esp->dma_opaque = dma_opaque;
652 sysbus->it_shift = it_shift;
653 /* XXX for now until rc4030 has been changed to use DMA enable signal */
654 esp->dma_enabled = 1;
655 qdev_init_nofail(dev);
656 s = SYS_BUS_DEVICE(dev);
657 sysbus_connect_irq(s, 0, irq);
658 sysbus_mmio_map(s, 0, espaddr);
659 *reset = qdev_get_gpio_in(dev, 0);
660 *dma_enable = qdev_get_gpio_in(dev, 1);
661 }
662
663 static const struct SCSIBusInfo esp_scsi_info = {
664 .tcq = false,
665 .max_target = ESP_MAX_DEVS,
666 .max_lun = 7,
667
668 .transfer_data = esp_transfer_data,
669 .complete = esp_command_complete,
670 .cancel = esp_request_cancelled
671 };
672
673 static void sysbus_esp_gpio_demux(void *opaque, int irq, int level)
674 {
675 SysBusESPState *sysbus = ESP(opaque);
676 ESPState *s = &sysbus->esp;
677
678 switch (irq) {
679 case 0:
680 parent_esp_reset(s, irq, level);
681 break;
682 case 1:
683 esp_dma_enable(opaque, irq, level);
684 break;
685 }
686 }
687
688 static void sysbus_esp_realize(DeviceState *dev, Error **errp)
689 {
690 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
691 SysBusESPState *sysbus = ESP(dev);
692 ESPState *s = &sysbus->esp;
693
694 sysbus_init_irq(sbd, &s->irq);
695 assert(sysbus->it_shift != -1);
696
697 s->chip_id = TCHI_FAS100A;
698 memory_region_init_io(&sysbus->iomem, OBJECT(sysbus), &sysbus_esp_mem_ops,
699 sysbus, "esp", ESP_REGS << sysbus->it_shift);
700 sysbus_init_mmio(sbd, &sysbus->iomem);
701
702 qdev_init_gpio_in(dev, sysbus_esp_gpio_demux, 2);
703
704 scsi_bus_new(&s->bus, sizeof(s->bus), dev, &esp_scsi_info, NULL);
705 }
706
707 static void sysbus_esp_hard_reset(DeviceState *dev)
708 {
709 SysBusESPState *sysbus = ESP(dev);
710 esp_hard_reset(&sysbus->esp);
711 }
712
713 static const VMStateDescription vmstate_sysbus_esp_scsi = {
714 .name = "sysbusespscsi",
715 .version_id = 0,
716 .minimum_version_id = 0,
717 .fields = (VMStateField[]) {
718 VMSTATE_STRUCT(esp, SysBusESPState, 0, vmstate_esp, ESPState),
719 VMSTATE_END_OF_LIST()
720 }
721 };
722
723 static void sysbus_esp_class_init(ObjectClass *klass, void *data)
724 {
725 DeviceClass *dc = DEVICE_CLASS(klass);
726
727 dc->realize = sysbus_esp_realize;
728 dc->reset = sysbus_esp_hard_reset;
729 dc->vmsd = &vmstate_sysbus_esp_scsi;
730 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
731 }
732
733 static const TypeInfo sysbus_esp_info = {
734 .name = TYPE_ESP,
735 .parent = TYPE_SYS_BUS_DEVICE,
736 .instance_size = sizeof(SysBusESPState),
737 .class_init = sysbus_esp_class_init,
738 };
739
740 static void esp_register_types(void)
741 {
742 type_register_static(&sysbus_esp_info);
743 }
744
745 type_init(esp_register_types)