vmw_pvscsi: check page count while initialising descriptor rings
[qemu.git] / hw / scsi / vmw_pvscsi.c
1 /*
2 * QEMU VMWARE PVSCSI paravirtual SCSI bus
3 *
4 * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com)
5 *
6 * Developed by Daynix Computing LTD (http://www.daynix.com)
7 *
8 * Based on implementation by Paolo Bonzini
9 * http://lists.gnu.org/archive/html/qemu-devel/2011-08/msg00729.html
10 *
11 * Authors:
12 * Paolo Bonzini <pbonzini@redhat.com>
13 * Dmitry Fleytman <dmitry@daynix.com>
14 * Yan Vugenfirer <yan@daynix.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2.
17 * See the COPYING file in the top-level directory.
18 *
19 * NOTE about MSI-X:
20 * MSI-X support has been removed for the moment because it leads Windows OS
21 * to crash on startup. The crash happens because Windows driver requires
22 * MSI-X shared memory to be part of the same BAR used for rings state
23 * registers, etc. This is not supported by QEMU infrastructure so separate
24 * BAR created from MSI-X purposes. Windows driver fails to deal with 2 BARs.
25 *
26 */
27
28 #include "qemu/osdep.h"
29 #include "qapi/error.h"
30 #include "hw/scsi/scsi.h"
31 #include "block/scsi.h"
32 #include "hw/pci/msi.h"
33 #include "vmw_pvscsi.h"
34 #include "trace.h"
35
36
37 #define PVSCSI_USE_64BIT (true)
38 #define PVSCSI_PER_VECTOR_MASK (false)
39
40 #define PVSCSI_MAX_DEVS (64)
41 #define PVSCSI_MSIX_NUM_VECTORS (1)
42
43 #define PVSCSI_MAX_CMD_DATA_WORDS \
44 (sizeof(PVSCSICmdDescSetupRings)/sizeof(uint32_t))
45
46 #define RS_GET_FIELD(m, field) \
47 (ldl_le_pci_dma(&container_of(m, PVSCSIState, rings)->parent_obj, \
48 (m)->rs_pa + offsetof(struct PVSCSIRingsState, field)))
49 #define RS_SET_FIELD(m, field, val) \
50 (stl_le_pci_dma(&container_of(m, PVSCSIState, rings)->parent_obj, \
51 (m)->rs_pa + offsetof(struct PVSCSIRingsState, field), val))
52
53 typedef struct PVSCSIClass {
54 PCIDeviceClass parent_class;
55 DeviceRealize parent_dc_realize;
56 } PVSCSIClass;
57
58 #define TYPE_PVSCSI "pvscsi"
59 #define PVSCSI(obj) OBJECT_CHECK(PVSCSIState, (obj), TYPE_PVSCSI)
60
61 #define PVSCSI_DEVICE_CLASS(klass) \
62 OBJECT_CLASS_CHECK(PVSCSIClass, (klass), TYPE_PVSCSI)
63 #define PVSCSI_DEVICE_GET_CLASS(obj) \
64 OBJECT_GET_CLASS(PVSCSIClass, (obj), TYPE_PVSCSI)
65
66 /* Compatibility flags for migration */
67 #define PVSCSI_COMPAT_OLD_PCI_CONFIGURATION_BIT 0
68 #define PVSCSI_COMPAT_OLD_PCI_CONFIGURATION \
69 (1 << PVSCSI_COMPAT_OLD_PCI_CONFIGURATION_BIT)
70 #define PVSCSI_COMPAT_DISABLE_PCIE_BIT 1
71 #define PVSCSI_COMPAT_DISABLE_PCIE \
72 (1 << PVSCSI_COMPAT_DISABLE_PCIE_BIT)
73
74 #define PVSCSI_USE_OLD_PCI_CONFIGURATION(s) \
75 ((s)->compat_flags & PVSCSI_COMPAT_OLD_PCI_CONFIGURATION)
76 #define PVSCSI_MSI_OFFSET(s) \
77 (PVSCSI_USE_OLD_PCI_CONFIGURATION(s) ? 0x50 : 0x7c)
78 #define PVSCSI_EXP_EP_OFFSET (0x40)
79
80 typedef struct PVSCSIRingInfo {
81 uint64_t rs_pa;
82 uint32_t txr_len_mask;
83 uint32_t rxr_len_mask;
84 uint32_t msg_len_mask;
85 uint64_t req_ring_pages_pa[PVSCSI_SETUP_RINGS_MAX_NUM_PAGES];
86 uint64_t cmp_ring_pages_pa[PVSCSI_SETUP_RINGS_MAX_NUM_PAGES];
87 uint64_t msg_ring_pages_pa[PVSCSI_SETUP_MSG_RING_MAX_NUM_PAGES];
88 uint64_t consumed_ptr;
89 uint64_t filled_cmp_ptr;
90 uint64_t filled_msg_ptr;
91 } PVSCSIRingInfo;
92
93 typedef struct PVSCSISGState {
94 hwaddr elemAddr;
95 hwaddr dataAddr;
96 uint32_t resid;
97 } PVSCSISGState;
98
99 typedef QTAILQ_HEAD(, PVSCSIRequest) PVSCSIRequestList;
100
101 typedef struct {
102 PCIDevice parent_obj;
103 MemoryRegion io_space;
104 SCSIBus bus;
105 QEMUBH *completion_worker;
106 PVSCSIRequestList pending_queue;
107 PVSCSIRequestList completion_queue;
108
109 uint64_t reg_interrupt_status; /* Interrupt status register value */
110 uint64_t reg_interrupt_enabled; /* Interrupt mask register value */
111 uint64_t reg_command_status; /* Command status register value */
112
113 /* Command data adoption mechanism */
114 uint64_t curr_cmd; /* Last command arrived */
115 uint32_t curr_cmd_data_cntr; /* Amount of data for last command */
116
117 /* Collector for current command data */
118 uint32_t curr_cmd_data[PVSCSI_MAX_CMD_DATA_WORDS];
119
120 uint8_t rings_info_valid; /* Whether data rings initialized */
121 uint8_t msg_ring_info_valid; /* Whether message ring initialized */
122 uint8_t use_msg; /* Whether to use message ring */
123
124 uint8_t msi_used; /* For migration compatibility */
125 PVSCSIRingInfo rings; /* Data transfer rings manager */
126 uint32_t resetting; /* Reset in progress */
127
128 uint32_t compat_flags;
129 } PVSCSIState;
130
131 typedef struct PVSCSIRequest {
132 SCSIRequest *sreq;
133 PVSCSIState *dev;
134 uint8_t sense_key;
135 uint8_t completed;
136 int lun;
137 QEMUSGList sgl;
138 PVSCSISGState sg;
139 struct PVSCSIRingReqDesc req;
140 struct PVSCSIRingCmpDesc cmp;
141 QTAILQ_ENTRY(PVSCSIRequest) next;
142 } PVSCSIRequest;
143
144 /* Integer binary logarithm */
145 static int
146 pvscsi_log2(uint32_t input)
147 {
148 int log = 0;
149 assert(input > 0);
150 while (input >> ++log) {
151 }
152 return log;
153 }
154
155 static void
156 pvscsi_ring_init_data(PVSCSIRingInfo *m, PVSCSICmdDescSetupRings *ri)
157 {
158 int i;
159 uint32_t txr_len_log2, rxr_len_log2;
160 uint32_t req_ring_size, cmp_ring_size;
161 m->rs_pa = ri->ringsStatePPN << VMW_PAGE_SHIFT;
162
163 req_ring_size = ri->reqRingNumPages * PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE;
164 cmp_ring_size = ri->cmpRingNumPages * PVSCSI_MAX_NUM_CMP_ENTRIES_PER_PAGE;
165 txr_len_log2 = pvscsi_log2(req_ring_size - 1);
166 rxr_len_log2 = pvscsi_log2(cmp_ring_size - 1);
167
168 m->txr_len_mask = MASK(txr_len_log2);
169 m->rxr_len_mask = MASK(rxr_len_log2);
170
171 m->consumed_ptr = 0;
172 m->filled_cmp_ptr = 0;
173
174 for (i = 0; i < ri->reqRingNumPages; i++) {
175 m->req_ring_pages_pa[i] = ri->reqRingPPNs[i] << VMW_PAGE_SHIFT;
176 }
177
178 for (i = 0; i < ri->cmpRingNumPages; i++) {
179 m->cmp_ring_pages_pa[i] = ri->cmpRingPPNs[i] << VMW_PAGE_SHIFT;
180 }
181
182 RS_SET_FIELD(m, reqProdIdx, 0);
183 RS_SET_FIELD(m, reqConsIdx, 0);
184 RS_SET_FIELD(m, reqNumEntriesLog2, txr_len_log2);
185
186 RS_SET_FIELD(m, cmpProdIdx, 0);
187 RS_SET_FIELD(m, cmpConsIdx, 0);
188 RS_SET_FIELD(m, cmpNumEntriesLog2, rxr_len_log2);
189
190 trace_pvscsi_ring_init_data(txr_len_log2, rxr_len_log2);
191
192 /* Flush ring state page changes */
193 smp_wmb();
194 }
195
196 static int
197 pvscsi_ring_init_msg(PVSCSIRingInfo *m, PVSCSICmdDescSetupMsgRing *ri)
198 {
199 int i;
200 uint32_t len_log2;
201 uint32_t ring_size;
202
203 if (ri->numPages > PVSCSI_SETUP_MSG_RING_MAX_NUM_PAGES) {
204 return -1;
205 }
206 ring_size = ri->numPages * PVSCSI_MAX_NUM_MSG_ENTRIES_PER_PAGE;
207 len_log2 = pvscsi_log2(ring_size - 1);
208
209 m->msg_len_mask = MASK(len_log2);
210
211 m->filled_msg_ptr = 0;
212
213 for (i = 0; i < ri->numPages; i++) {
214 m->msg_ring_pages_pa[i] = ri->ringPPNs[i] << VMW_PAGE_SHIFT;
215 }
216
217 RS_SET_FIELD(m, msgProdIdx, 0);
218 RS_SET_FIELD(m, msgConsIdx, 0);
219 RS_SET_FIELD(m, msgNumEntriesLog2, len_log2);
220
221 trace_pvscsi_ring_init_msg(len_log2);
222
223 /* Flush ring state page changes */
224 smp_wmb();
225
226 return 0;
227 }
228
229 static void
230 pvscsi_ring_cleanup(PVSCSIRingInfo *mgr)
231 {
232 mgr->rs_pa = 0;
233 mgr->txr_len_mask = 0;
234 mgr->rxr_len_mask = 0;
235 mgr->msg_len_mask = 0;
236 mgr->consumed_ptr = 0;
237 mgr->filled_cmp_ptr = 0;
238 mgr->filled_msg_ptr = 0;
239 memset(mgr->req_ring_pages_pa, 0, sizeof(mgr->req_ring_pages_pa));
240 memset(mgr->cmp_ring_pages_pa, 0, sizeof(mgr->cmp_ring_pages_pa));
241 memset(mgr->msg_ring_pages_pa, 0, sizeof(mgr->msg_ring_pages_pa));
242 }
243
244 static hwaddr
245 pvscsi_ring_pop_req_descr(PVSCSIRingInfo *mgr)
246 {
247 uint32_t ready_ptr = RS_GET_FIELD(mgr, reqProdIdx);
248
249 if (ready_ptr != mgr->consumed_ptr) {
250 uint32_t next_ready_ptr =
251 mgr->consumed_ptr++ & mgr->txr_len_mask;
252 uint32_t next_ready_page =
253 next_ready_ptr / PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE;
254 uint32_t inpage_idx =
255 next_ready_ptr % PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE;
256
257 return mgr->req_ring_pages_pa[next_ready_page] +
258 inpage_idx * sizeof(PVSCSIRingReqDesc);
259 } else {
260 return 0;
261 }
262 }
263
264 static void
265 pvscsi_ring_flush_req(PVSCSIRingInfo *mgr)
266 {
267 RS_SET_FIELD(mgr, reqConsIdx, mgr->consumed_ptr);
268 }
269
270 static hwaddr
271 pvscsi_ring_pop_cmp_descr(PVSCSIRingInfo *mgr)
272 {
273 /*
274 * According to Linux driver code it explicitly verifies that number
275 * of requests being processed by device is less then the size of
276 * completion queue, so device may omit completion queue overflow
277 * conditions check. We assume that this is true for other (Windows)
278 * drivers as well.
279 */
280
281 uint32_t free_cmp_ptr =
282 mgr->filled_cmp_ptr++ & mgr->rxr_len_mask;
283 uint32_t free_cmp_page =
284 free_cmp_ptr / PVSCSI_MAX_NUM_CMP_ENTRIES_PER_PAGE;
285 uint32_t inpage_idx =
286 free_cmp_ptr % PVSCSI_MAX_NUM_CMP_ENTRIES_PER_PAGE;
287 return mgr->cmp_ring_pages_pa[free_cmp_page] +
288 inpage_idx * sizeof(PVSCSIRingCmpDesc);
289 }
290
291 static hwaddr
292 pvscsi_ring_pop_msg_descr(PVSCSIRingInfo *mgr)
293 {
294 uint32_t free_msg_ptr =
295 mgr->filled_msg_ptr++ & mgr->msg_len_mask;
296 uint32_t free_msg_page =
297 free_msg_ptr / PVSCSI_MAX_NUM_MSG_ENTRIES_PER_PAGE;
298 uint32_t inpage_idx =
299 free_msg_ptr % PVSCSI_MAX_NUM_MSG_ENTRIES_PER_PAGE;
300 return mgr->msg_ring_pages_pa[free_msg_page] +
301 inpage_idx * sizeof(PVSCSIRingMsgDesc);
302 }
303
304 static void
305 pvscsi_ring_flush_cmp(PVSCSIRingInfo *mgr)
306 {
307 /* Flush descriptor changes */
308 smp_wmb();
309
310 trace_pvscsi_ring_flush_cmp(mgr->filled_cmp_ptr);
311
312 RS_SET_FIELD(mgr, cmpProdIdx, mgr->filled_cmp_ptr);
313 }
314
315 static bool
316 pvscsi_ring_msg_has_room(PVSCSIRingInfo *mgr)
317 {
318 uint32_t prodIdx = RS_GET_FIELD(mgr, msgProdIdx);
319 uint32_t consIdx = RS_GET_FIELD(mgr, msgConsIdx);
320
321 return (prodIdx - consIdx) < (mgr->msg_len_mask + 1);
322 }
323
324 static void
325 pvscsi_ring_flush_msg(PVSCSIRingInfo *mgr)
326 {
327 /* Flush descriptor changes */
328 smp_wmb();
329
330 trace_pvscsi_ring_flush_msg(mgr->filled_msg_ptr);
331
332 RS_SET_FIELD(mgr, msgProdIdx, mgr->filled_msg_ptr);
333 }
334
335 static void
336 pvscsi_reset_state(PVSCSIState *s)
337 {
338 s->curr_cmd = PVSCSI_CMD_FIRST;
339 s->curr_cmd_data_cntr = 0;
340 s->reg_command_status = PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
341 s->reg_interrupt_status = 0;
342 pvscsi_ring_cleanup(&s->rings);
343 s->rings_info_valid = FALSE;
344 s->msg_ring_info_valid = FALSE;
345 QTAILQ_INIT(&s->pending_queue);
346 QTAILQ_INIT(&s->completion_queue);
347 }
348
349 static void
350 pvscsi_update_irq_status(PVSCSIState *s)
351 {
352 PCIDevice *d = PCI_DEVICE(s);
353 bool should_raise = s->reg_interrupt_enabled & s->reg_interrupt_status;
354
355 trace_pvscsi_update_irq_level(should_raise, s->reg_interrupt_enabled,
356 s->reg_interrupt_status);
357
358 if (msi_enabled(d)) {
359 if (should_raise) {
360 trace_pvscsi_update_irq_msi();
361 msi_notify(d, PVSCSI_VECTOR_COMPLETION);
362 }
363 return;
364 }
365
366 pci_set_irq(d, !!should_raise);
367 }
368
369 static void
370 pvscsi_raise_completion_interrupt(PVSCSIState *s)
371 {
372 s->reg_interrupt_status |= PVSCSI_INTR_CMPL_0;
373
374 /* Memory barrier to flush interrupt status register changes*/
375 smp_wmb();
376
377 pvscsi_update_irq_status(s);
378 }
379
380 static void
381 pvscsi_raise_message_interrupt(PVSCSIState *s)
382 {
383 s->reg_interrupt_status |= PVSCSI_INTR_MSG_0;
384
385 /* Memory barrier to flush interrupt status register changes*/
386 smp_wmb();
387
388 pvscsi_update_irq_status(s);
389 }
390
391 static void
392 pvscsi_cmp_ring_put(PVSCSIState *s, struct PVSCSIRingCmpDesc *cmp_desc)
393 {
394 hwaddr cmp_descr_pa;
395
396 cmp_descr_pa = pvscsi_ring_pop_cmp_descr(&s->rings);
397 trace_pvscsi_cmp_ring_put(cmp_descr_pa);
398 cpu_physical_memory_write(cmp_descr_pa, (void *)cmp_desc,
399 sizeof(*cmp_desc));
400 }
401
402 static void
403 pvscsi_msg_ring_put(PVSCSIState *s, struct PVSCSIRingMsgDesc *msg_desc)
404 {
405 hwaddr msg_descr_pa;
406
407 msg_descr_pa = pvscsi_ring_pop_msg_descr(&s->rings);
408 trace_pvscsi_msg_ring_put(msg_descr_pa);
409 cpu_physical_memory_write(msg_descr_pa, (void *)msg_desc,
410 sizeof(*msg_desc));
411 }
412
413 static void
414 pvscsi_process_completion_queue(void *opaque)
415 {
416 PVSCSIState *s = opaque;
417 PVSCSIRequest *pvscsi_req;
418 bool has_completed = false;
419
420 while (!QTAILQ_EMPTY(&s->completion_queue)) {
421 pvscsi_req = QTAILQ_FIRST(&s->completion_queue);
422 QTAILQ_REMOVE(&s->completion_queue, pvscsi_req, next);
423 pvscsi_cmp_ring_put(s, &pvscsi_req->cmp);
424 g_free(pvscsi_req);
425 has_completed = true;
426 }
427
428 if (has_completed) {
429 pvscsi_ring_flush_cmp(&s->rings);
430 pvscsi_raise_completion_interrupt(s);
431 }
432 }
433
434 static void
435 pvscsi_reset_adapter(PVSCSIState *s)
436 {
437 s->resetting++;
438 qbus_reset_all_fn(&s->bus);
439 s->resetting--;
440 pvscsi_process_completion_queue(s);
441 assert(QTAILQ_EMPTY(&s->pending_queue));
442 pvscsi_reset_state(s);
443 }
444
445 static void
446 pvscsi_schedule_completion_processing(PVSCSIState *s)
447 {
448 /* Try putting more complete requests on the ring. */
449 if (!QTAILQ_EMPTY(&s->completion_queue)) {
450 qemu_bh_schedule(s->completion_worker);
451 }
452 }
453
454 static void
455 pvscsi_complete_request(PVSCSIState *s, PVSCSIRequest *r)
456 {
457 assert(!r->completed);
458
459 trace_pvscsi_complete_request(r->cmp.context, r->cmp.dataLen,
460 r->sense_key);
461 if (r->sreq != NULL) {
462 scsi_req_unref(r->sreq);
463 r->sreq = NULL;
464 }
465 r->completed = 1;
466 QTAILQ_REMOVE(&s->pending_queue, r, next);
467 QTAILQ_INSERT_TAIL(&s->completion_queue, r, next);
468 pvscsi_schedule_completion_processing(s);
469 }
470
471 static QEMUSGList *pvscsi_get_sg_list(SCSIRequest *r)
472 {
473 PVSCSIRequest *req = r->hba_private;
474
475 trace_pvscsi_get_sg_list(req->sgl.nsg, req->sgl.size);
476
477 return &req->sgl;
478 }
479
480 static void
481 pvscsi_get_next_sg_elem(PVSCSISGState *sg)
482 {
483 struct PVSCSISGElement elem;
484
485 cpu_physical_memory_read(sg->elemAddr, (void *)&elem, sizeof(elem));
486 if ((elem.flags & ~PVSCSI_KNOWN_FLAGS) != 0) {
487 /*
488 * There is PVSCSI_SGE_FLAG_CHAIN_ELEMENT flag described in
489 * header file but its value is unknown. This flag requires
490 * additional processing, so we put warning here to catch it
491 * some day and make proper implementation
492 */
493 trace_pvscsi_get_next_sg_elem(elem.flags);
494 }
495
496 sg->elemAddr += sizeof(elem);
497 sg->dataAddr = elem.addr;
498 sg->resid = elem.length;
499 }
500
501 static void
502 pvscsi_write_sense(PVSCSIRequest *r, uint8_t *sense, int len)
503 {
504 r->cmp.senseLen = MIN(r->req.senseLen, len);
505 r->sense_key = sense[(sense[0] & 2) ? 1 : 2];
506 cpu_physical_memory_write(r->req.senseAddr, sense, r->cmp.senseLen);
507 }
508
509 static void
510 pvscsi_command_complete(SCSIRequest *req, uint32_t status, size_t resid)
511 {
512 PVSCSIRequest *pvscsi_req = req->hba_private;
513 PVSCSIState *s;
514
515 if (!pvscsi_req) {
516 trace_pvscsi_command_complete_not_found(req->tag);
517 return;
518 }
519 s = pvscsi_req->dev;
520
521 if (resid) {
522 /* Short transfer. */
523 trace_pvscsi_command_complete_data_run();
524 pvscsi_req->cmp.hostStatus = BTSTAT_DATARUN;
525 }
526
527 pvscsi_req->cmp.scsiStatus = status;
528 if (pvscsi_req->cmp.scsiStatus == CHECK_CONDITION) {
529 uint8_t sense[SCSI_SENSE_BUF_SIZE];
530 int sense_len =
531 scsi_req_get_sense(pvscsi_req->sreq, sense, sizeof(sense));
532
533 trace_pvscsi_command_complete_sense_len(sense_len);
534 pvscsi_write_sense(pvscsi_req, sense, sense_len);
535 }
536 qemu_sglist_destroy(&pvscsi_req->sgl);
537 pvscsi_complete_request(s, pvscsi_req);
538 }
539
540 static void
541 pvscsi_send_msg(PVSCSIState *s, SCSIDevice *dev, uint32_t msg_type)
542 {
543 if (s->msg_ring_info_valid && pvscsi_ring_msg_has_room(&s->rings)) {
544 PVSCSIMsgDescDevStatusChanged msg = {0};
545
546 msg.type = msg_type;
547 msg.bus = dev->channel;
548 msg.target = dev->id;
549 msg.lun[1] = dev->lun;
550
551 pvscsi_msg_ring_put(s, (PVSCSIRingMsgDesc *)&msg);
552 pvscsi_ring_flush_msg(&s->rings);
553 pvscsi_raise_message_interrupt(s);
554 }
555 }
556
557 static void
558 pvscsi_hotplug(HotplugHandler *hotplug_dev, DeviceState *dev, Error **errp)
559 {
560 PVSCSIState *s = PVSCSI(hotplug_dev);
561
562 pvscsi_send_msg(s, SCSI_DEVICE(dev), PVSCSI_MSG_DEV_ADDED);
563 }
564
565 static void
566 pvscsi_hot_unplug(HotplugHandler *hotplug_dev, DeviceState *dev, Error **errp)
567 {
568 PVSCSIState *s = PVSCSI(hotplug_dev);
569
570 pvscsi_send_msg(s, SCSI_DEVICE(dev), PVSCSI_MSG_DEV_REMOVED);
571 qdev_simple_device_unplug_cb(hotplug_dev, dev, errp);
572 }
573
574 static void
575 pvscsi_request_cancelled(SCSIRequest *req)
576 {
577 PVSCSIRequest *pvscsi_req = req->hba_private;
578 PVSCSIState *s = pvscsi_req->dev;
579
580 if (pvscsi_req->completed) {
581 return;
582 }
583
584 if (pvscsi_req->dev->resetting) {
585 pvscsi_req->cmp.hostStatus = BTSTAT_BUSRESET;
586 } else {
587 pvscsi_req->cmp.hostStatus = BTSTAT_ABORTQUEUE;
588 }
589
590 pvscsi_complete_request(s, pvscsi_req);
591 }
592
593 static SCSIDevice*
594 pvscsi_device_find(PVSCSIState *s, int channel, int target,
595 uint8_t *requested_lun, uint8_t *target_lun)
596 {
597 if (requested_lun[0] || requested_lun[2] || requested_lun[3] ||
598 requested_lun[4] || requested_lun[5] || requested_lun[6] ||
599 requested_lun[7] || (target > PVSCSI_MAX_DEVS)) {
600 return NULL;
601 } else {
602 *target_lun = requested_lun[1];
603 return scsi_device_find(&s->bus, channel, target, *target_lun);
604 }
605 }
606
607 static PVSCSIRequest *
608 pvscsi_queue_pending_descriptor(PVSCSIState *s, SCSIDevice **d,
609 struct PVSCSIRingReqDesc *descr)
610 {
611 PVSCSIRequest *pvscsi_req;
612 uint8_t lun;
613
614 pvscsi_req = g_malloc0(sizeof(*pvscsi_req));
615 pvscsi_req->dev = s;
616 pvscsi_req->req = *descr;
617 pvscsi_req->cmp.context = pvscsi_req->req.context;
618 QTAILQ_INSERT_TAIL(&s->pending_queue, pvscsi_req, next);
619
620 *d = pvscsi_device_find(s, descr->bus, descr->target, descr->lun, &lun);
621 if (*d) {
622 pvscsi_req->lun = lun;
623 }
624
625 return pvscsi_req;
626 }
627
628 static void
629 pvscsi_convert_sglist(PVSCSIRequest *r)
630 {
631 int chunk_size;
632 uint64_t data_length = r->req.dataLen;
633 PVSCSISGState sg = r->sg;
634 while (data_length) {
635 while (!sg.resid) {
636 pvscsi_get_next_sg_elem(&sg);
637 trace_pvscsi_convert_sglist(r->req.context, r->sg.dataAddr,
638 r->sg.resid);
639 }
640 assert(data_length > 0);
641 chunk_size = MIN((unsigned) data_length, sg.resid);
642 if (chunk_size) {
643 qemu_sglist_add(&r->sgl, sg.dataAddr, chunk_size);
644 }
645
646 sg.dataAddr += chunk_size;
647 data_length -= chunk_size;
648 sg.resid -= chunk_size;
649 }
650 }
651
652 static void
653 pvscsi_build_sglist(PVSCSIState *s, PVSCSIRequest *r)
654 {
655 PCIDevice *d = PCI_DEVICE(s);
656
657 pci_dma_sglist_init(&r->sgl, d, 1);
658 if (r->req.flags & PVSCSI_FLAG_CMD_WITH_SG_LIST) {
659 pvscsi_convert_sglist(r);
660 } else {
661 qemu_sglist_add(&r->sgl, r->req.dataAddr, r->req.dataLen);
662 }
663 }
664
665 static void
666 pvscsi_process_request_descriptor(PVSCSIState *s,
667 struct PVSCSIRingReqDesc *descr)
668 {
669 SCSIDevice *d;
670 PVSCSIRequest *r = pvscsi_queue_pending_descriptor(s, &d, descr);
671 int64_t n;
672
673 trace_pvscsi_process_req_descr(descr->cdb[0], descr->context);
674
675 if (!d) {
676 r->cmp.hostStatus = BTSTAT_SELTIMEO;
677 trace_pvscsi_process_req_descr_unknown_device();
678 pvscsi_complete_request(s, r);
679 return;
680 }
681
682 if (descr->flags & PVSCSI_FLAG_CMD_WITH_SG_LIST) {
683 r->sg.elemAddr = descr->dataAddr;
684 }
685
686 r->sreq = scsi_req_new(d, descr->context, r->lun, descr->cdb, r);
687 if (r->sreq->cmd.mode == SCSI_XFER_FROM_DEV &&
688 (descr->flags & PVSCSI_FLAG_CMD_DIR_TODEVICE)) {
689 r->cmp.hostStatus = BTSTAT_BADMSG;
690 trace_pvscsi_process_req_descr_invalid_dir();
691 scsi_req_cancel(r->sreq);
692 return;
693 }
694 if (r->sreq->cmd.mode == SCSI_XFER_TO_DEV &&
695 (descr->flags & PVSCSI_FLAG_CMD_DIR_TOHOST)) {
696 r->cmp.hostStatus = BTSTAT_BADMSG;
697 trace_pvscsi_process_req_descr_invalid_dir();
698 scsi_req_cancel(r->sreq);
699 return;
700 }
701
702 pvscsi_build_sglist(s, r);
703 n = scsi_req_enqueue(r->sreq);
704
705 if (n) {
706 scsi_req_continue(r->sreq);
707 }
708 }
709
710 static void
711 pvscsi_process_io(PVSCSIState *s)
712 {
713 PVSCSIRingReqDesc descr;
714 hwaddr next_descr_pa;
715
716 assert(s->rings_info_valid);
717 while ((next_descr_pa = pvscsi_ring_pop_req_descr(&s->rings)) != 0) {
718
719 /* Only read after production index verification */
720 smp_rmb();
721
722 trace_pvscsi_process_io(next_descr_pa);
723 cpu_physical_memory_read(next_descr_pa, &descr, sizeof(descr));
724 pvscsi_process_request_descriptor(s, &descr);
725 }
726
727 pvscsi_ring_flush_req(&s->rings);
728 }
729
730 static void
731 pvscsi_dbg_dump_tx_rings_config(PVSCSICmdDescSetupRings *rc)
732 {
733 int i;
734 trace_pvscsi_tx_rings_ppn("Rings State", rc->ringsStatePPN);
735
736 trace_pvscsi_tx_rings_num_pages("Request Ring", rc->reqRingNumPages);
737 for (i = 0; i < rc->reqRingNumPages; i++) {
738 trace_pvscsi_tx_rings_ppn("Request Ring", rc->reqRingPPNs[i]);
739 }
740
741 trace_pvscsi_tx_rings_num_pages("Confirm Ring", rc->cmpRingNumPages);
742 for (i = 0; i < rc->cmpRingNumPages; i++) {
743 trace_pvscsi_tx_rings_ppn("Confirm Ring", rc->cmpRingPPNs[i]);
744 }
745 }
746
747 static uint64_t
748 pvscsi_on_cmd_config(PVSCSIState *s)
749 {
750 trace_pvscsi_on_cmd_noimpl("PVSCSI_CMD_CONFIG");
751 return PVSCSI_COMMAND_PROCESSING_FAILED;
752 }
753
754 static uint64_t
755 pvscsi_on_cmd_unplug(PVSCSIState *s)
756 {
757 trace_pvscsi_on_cmd_noimpl("PVSCSI_CMD_DEVICE_UNPLUG");
758 return PVSCSI_COMMAND_PROCESSING_FAILED;
759 }
760
761 static uint64_t
762 pvscsi_on_issue_scsi(PVSCSIState *s)
763 {
764 trace_pvscsi_on_cmd_noimpl("PVSCSI_CMD_ISSUE_SCSI");
765 return PVSCSI_COMMAND_PROCESSING_FAILED;
766 }
767
768 static uint64_t
769 pvscsi_on_cmd_setup_rings(PVSCSIState *s)
770 {
771 PVSCSICmdDescSetupRings *rc =
772 (PVSCSICmdDescSetupRings *) s->curr_cmd_data;
773
774 trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_SETUP_RINGS");
775
776 if (!rc->reqRingNumPages
777 || rc->reqRingNumPages > PVSCSI_SETUP_RINGS_MAX_NUM_PAGES
778 || !rc->cmpRingNumPages
779 || rc->cmpRingNumPages > PVSCSI_SETUP_RINGS_MAX_NUM_PAGES) {
780 return PVSCSI_COMMAND_PROCESSING_FAILED;
781 }
782
783 pvscsi_dbg_dump_tx_rings_config(rc);
784 pvscsi_ring_init_data(&s->rings, rc);
785
786 s->rings_info_valid = TRUE;
787 return PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
788 }
789
790 static uint64_t
791 pvscsi_on_cmd_abort(PVSCSIState *s)
792 {
793 PVSCSICmdDescAbortCmd *cmd = (PVSCSICmdDescAbortCmd *) s->curr_cmd_data;
794 PVSCSIRequest *r, *next;
795
796 trace_pvscsi_on_cmd_abort(cmd->context, cmd->target);
797
798 QTAILQ_FOREACH_SAFE(r, &s->pending_queue, next, next) {
799 if (r->req.context == cmd->context) {
800 break;
801 }
802 }
803 if (r) {
804 assert(!r->completed);
805 r->cmp.hostStatus = BTSTAT_ABORTQUEUE;
806 scsi_req_cancel(r->sreq);
807 }
808
809 return PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
810 }
811
812 static uint64_t
813 pvscsi_on_cmd_unknown(PVSCSIState *s)
814 {
815 trace_pvscsi_on_cmd_unknown_data(s->curr_cmd_data[0]);
816 return PVSCSI_COMMAND_PROCESSING_FAILED;
817 }
818
819 static uint64_t
820 pvscsi_on_cmd_reset_device(PVSCSIState *s)
821 {
822 uint8_t target_lun = 0;
823 struct PVSCSICmdDescResetDevice *cmd =
824 (struct PVSCSICmdDescResetDevice *) s->curr_cmd_data;
825 SCSIDevice *sdev;
826
827 sdev = pvscsi_device_find(s, 0, cmd->target, cmd->lun, &target_lun);
828
829 trace_pvscsi_on_cmd_reset_dev(cmd->target, (int) target_lun, sdev);
830
831 if (sdev != NULL) {
832 s->resetting++;
833 device_reset(&sdev->qdev);
834 s->resetting--;
835 return PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
836 }
837
838 return PVSCSI_COMMAND_PROCESSING_FAILED;
839 }
840
841 static uint64_t
842 pvscsi_on_cmd_reset_bus(PVSCSIState *s)
843 {
844 trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_RESET_BUS");
845
846 s->resetting++;
847 qbus_reset_all_fn(&s->bus);
848 s->resetting--;
849 return PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
850 }
851
852 static uint64_t
853 pvscsi_on_cmd_setup_msg_ring(PVSCSIState *s)
854 {
855 PVSCSICmdDescSetupMsgRing *rc =
856 (PVSCSICmdDescSetupMsgRing *) s->curr_cmd_data;
857
858 trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_SETUP_MSG_RING");
859
860 if (!s->use_msg) {
861 return PVSCSI_COMMAND_PROCESSING_FAILED;
862 }
863
864 if (s->rings_info_valid) {
865 if (pvscsi_ring_init_msg(&s->rings, rc) < 0) {
866 return PVSCSI_COMMAND_PROCESSING_FAILED;
867 }
868 s->msg_ring_info_valid = TRUE;
869 }
870 return sizeof(PVSCSICmdDescSetupMsgRing) / sizeof(uint32_t);
871 }
872
873 static uint64_t
874 pvscsi_on_cmd_adapter_reset(PVSCSIState *s)
875 {
876 trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_ADAPTER_RESET");
877
878 pvscsi_reset_adapter(s);
879 return PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
880 }
881
882 static const struct {
883 int data_size;
884 uint64_t (*handler_fn)(PVSCSIState *s);
885 } pvscsi_commands[] = {
886 [PVSCSI_CMD_FIRST] = {
887 .data_size = 0,
888 .handler_fn = pvscsi_on_cmd_unknown,
889 },
890
891 /* Not implemented, data size defined based on what arrives on windows */
892 [PVSCSI_CMD_CONFIG] = {
893 .data_size = 6 * sizeof(uint32_t),
894 .handler_fn = pvscsi_on_cmd_config,
895 },
896
897 /* Command not implemented, data size is unknown */
898 [PVSCSI_CMD_ISSUE_SCSI] = {
899 .data_size = 0,
900 .handler_fn = pvscsi_on_issue_scsi,
901 },
902
903 /* Command not implemented, data size is unknown */
904 [PVSCSI_CMD_DEVICE_UNPLUG] = {
905 .data_size = 0,
906 .handler_fn = pvscsi_on_cmd_unplug,
907 },
908
909 [PVSCSI_CMD_SETUP_RINGS] = {
910 .data_size = sizeof(PVSCSICmdDescSetupRings),
911 .handler_fn = pvscsi_on_cmd_setup_rings,
912 },
913
914 [PVSCSI_CMD_RESET_DEVICE] = {
915 .data_size = sizeof(struct PVSCSICmdDescResetDevice),
916 .handler_fn = pvscsi_on_cmd_reset_device,
917 },
918
919 [PVSCSI_CMD_RESET_BUS] = {
920 .data_size = 0,
921 .handler_fn = pvscsi_on_cmd_reset_bus,
922 },
923
924 [PVSCSI_CMD_SETUP_MSG_RING] = {
925 .data_size = sizeof(PVSCSICmdDescSetupMsgRing),
926 .handler_fn = pvscsi_on_cmd_setup_msg_ring,
927 },
928
929 [PVSCSI_CMD_ADAPTER_RESET] = {
930 .data_size = 0,
931 .handler_fn = pvscsi_on_cmd_adapter_reset,
932 },
933
934 [PVSCSI_CMD_ABORT_CMD] = {
935 .data_size = sizeof(struct PVSCSICmdDescAbortCmd),
936 .handler_fn = pvscsi_on_cmd_abort,
937 },
938 };
939
940 static void
941 pvscsi_do_command_processing(PVSCSIState *s)
942 {
943 size_t bytes_arrived = s->curr_cmd_data_cntr * sizeof(uint32_t);
944
945 assert(s->curr_cmd < PVSCSI_CMD_LAST);
946 if (bytes_arrived >= pvscsi_commands[s->curr_cmd].data_size) {
947 s->reg_command_status = pvscsi_commands[s->curr_cmd].handler_fn(s);
948 s->curr_cmd = PVSCSI_CMD_FIRST;
949 s->curr_cmd_data_cntr = 0;
950 }
951 }
952
953 static void
954 pvscsi_on_command_data(PVSCSIState *s, uint32_t value)
955 {
956 size_t bytes_arrived = s->curr_cmd_data_cntr * sizeof(uint32_t);
957
958 assert(bytes_arrived < sizeof(s->curr_cmd_data));
959 s->curr_cmd_data[s->curr_cmd_data_cntr++] = value;
960
961 pvscsi_do_command_processing(s);
962 }
963
964 static void
965 pvscsi_on_command(PVSCSIState *s, uint64_t cmd_id)
966 {
967 if ((cmd_id > PVSCSI_CMD_FIRST) && (cmd_id < PVSCSI_CMD_LAST)) {
968 s->curr_cmd = cmd_id;
969 } else {
970 s->curr_cmd = PVSCSI_CMD_FIRST;
971 trace_pvscsi_on_cmd_unknown(cmd_id);
972 }
973
974 s->curr_cmd_data_cntr = 0;
975 s->reg_command_status = PVSCSI_COMMAND_NOT_ENOUGH_DATA;
976
977 pvscsi_do_command_processing(s);
978 }
979
980 static void
981 pvscsi_io_write(void *opaque, hwaddr addr,
982 uint64_t val, unsigned size)
983 {
984 PVSCSIState *s = opaque;
985
986 switch (addr) {
987 case PVSCSI_REG_OFFSET_COMMAND:
988 pvscsi_on_command(s, val);
989 break;
990
991 case PVSCSI_REG_OFFSET_COMMAND_DATA:
992 pvscsi_on_command_data(s, (uint32_t) val);
993 break;
994
995 case PVSCSI_REG_OFFSET_INTR_STATUS:
996 trace_pvscsi_io_write("PVSCSI_REG_OFFSET_INTR_STATUS", val);
997 s->reg_interrupt_status &= ~val;
998 pvscsi_update_irq_status(s);
999 pvscsi_schedule_completion_processing(s);
1000 break;
1001
1002 case PVSCSI_REG_OFFSET_INTR_MASK:
1003 trace_pvscsi_io_write("PVSCSI_REG_OFFSET_INTR_MASK", val);
1004 s->reg_interrupt_enabled = val;
1005 pvscsi_update_irq_status(s);
1006 break;
1007
1008 case PVSCSI_REG_OFFSET_KICK_NON_RW_IO:
1009 trace_pvscsi_io_write("PVSCSI_REG_OFFSET_KICK_NON_RW_IO", val);
1010 pvscsi_process_io(s);
1011 break;
1012
1013 case PVSCSI_REG_OFFSET_KICK_RW_IO:
1014 trace_pvscsi_io_write("PVSCSI_REG_OFFSET_KICK_RW_IO", val);
1015 pvscsi_process_io(s);
1016 break;
1017
1018 case PVSCSI_REG_OFFSET_DEBUG:
1019 trace_pvscsi_io_write("PVSCSI_REG_OFFSET_DEBUG", val);
1020 break;
1021
1022 default:
1023 trace_pvscsi_io_write_unknown(addr, size, val);
1024 break;
1025 }
1026
1027 }
1028
1029 static uint64_t
1030 pvscsi_io_read(void *opaque, hwaddr addr, unsigned size)
1031 {
1032 PVSCSIState *s = opaque;
1033
1034 switch (addr) {
1035 case PVSCSI_REG_OFFSET_INTR_STATUS:
1036 trace_pvscsi_io_read("PVSCSI_REG_OFFSET_INTR_STATUS",
1037 s->reg_interrupt_status);
1038 return s->reg_interrupt_status;
1039
1040 case PVSCSI_REG_OFFSET_INTR_MASK:
1041 trace_pvscsi_io_read("PVSCSI_REG_OFFSET_INTR_MASK",
1042 s->reg_interrupt_status);
1043 return s->reg_interrupt_enabled;
1044
1045 case PVSCSI_REG_OFFSET_COMMAND_STATUS:
1046 trace_pvscsi_io_read("PVSCSI_REG_OFFSET_COMMAND_STATUS",
1047 s->reg_interrupt_status);
1048 return s->reg_command_status;
1049
1050 default:
1051 trace_pvscsi_io_read_unknown(addr, size);
1052 return 0;
1053 }
1054 }
1055
1056
1057 static void
1058 pvscsi_init_msi(PVSCSIState *s)
1059 {
1060 int res;
1061 PCIDevice *d = PCI_DEVICE(s);
1062
1063 res = msi_init(d, PVSCSI_MSI_OFFSET(s), PVSCSI_MSIX_NUM_VECTORS,
1064 PVSCSI_USE_64BIT, PVSCSI_PER_VECTOR_MASK, NULL);
1065 if (res < 0) {
1066 trace_pvscsi_init_msi_fail(res);
1067 s->msi_used = false;
1068 } else {
1069 s->msi_used = true;
1070 }
1071 }
1072
1073 static void
1074 pvscsi_cleanup_msi(PVSCSIState *s)
1075 {
1076 PCIDevice *d = PCI_DEVICE(s);
1077
1078 msi_uninit(d);
1079 }
1080
1081 static const MemoryRegionOps pvscsi_ops = {
1082 .read = pvscsi_io_read,
1083 .write = pvscsi_io_write,
1084 .endianness = DEVICE_LITTLE_ENDIAN,
1085 .impl = {
1086 .min_access_size = 4,
1087 .max_access_size = 4,
1088 },
1089 };
1090
1091 static const struct SCSIBusInfo pvscsi_scsi_info = {
1092 .tcq = true,
1093 .max_target = PVSCSI_MAX_DEVS,
1094 .max_channel = 0,
1095 .max_lun = 0,
1096
1097 .get_sg_list = pvscsi_get_sg_list,
1098 .complete = pvscsi_command_complete,
1099 .cancel = pvscsi_request_cancelled,
1100 };
1101
1102 static int
1103 pvscsi_init(PCIDevice *pci_dev)
1104 {
1105 PVSCSIState *s = PVSCSI(pci_dev);
1106
1107 trace_pvscsi_state("init");
1108
1109 /* PCI subsystem ID, subsystem vendor ID, revision */
1110 if (PVSCSI_USE_OLD_PCI_CONFIGURATION(s)) {
1111 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 0x1000);
1112 } else {
1113 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
1114 PCI_VENDOR_ID_VMWARE);
1115 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
1116 PCI_DEVICE_ID_VMWARE_PVSCSI);
1117 pci_config_set_revision(pci_dev->config, 0x2);
1118 }
1119
1120 /* PCI latency timer = 255 */
1121 pci_dev->config[PCI_LATENCY_TIMER] = 0xff;
1122
1123 /* Interrupt pin A */
1124 pci_config_set_interrupt_pin(pci_dev->config, 1);
1125
1126 memory_region_init_io(&s->io_space, OBJECT(s), &pvscsi_ops, s,
1127 "pvscsi-io", PVSCSI_MEM_SPACE_SIZE);
1128 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->io_space);
1129
1130 pvscsi_init_msi(s);
1131
1132 if (pci_is_express(pci_dev) && pci_bus_is_express(pci_dev->bus)) {
1133 pcie_endpoint_cap_init(pci_dev, PVSCSI_EXP_EP_OFFSET);
1134 }
1135
1136 s->completion_worker = qemu_bh_new(pvscsi_process_completion_queue, s);
1137 if (!s->completion_worker) {
1138 pvscsi_cleanup_msi(s);
1139 return -ENOMEM;
1140 }
1141
1142 scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(pci_dev),
1143 &pvscsi_scsi_info, NULL);
1144 /* override default SCSI bus hotplug-handler, with pvscsi's one */
1145 qbus_set_hotplug_handler(BUS(&s->bus), DEVICE(s), &error_abort);
1146 pvscsi_reset_state(s);
1147
1148 return 0;
1149 }
1150
1151 static void
1152 pvscsi_uninit(PCIDevice *pci_dev)
1153 {
1154 PVSCSIState *s = PVSCSI(pci_dev);
1155
1156 trace_pvscsi_state("uninit");
1157 qemu_bh_delete(s->completion_worker);
1158
1159 pvscsi_cleanup_msi(s);
1160 }
1161
1162 static void
1163 pvscsi_reset(DeviceState *dev)
1164 {
1165 PCIDevice *d = PCI_DEVICE(dev);
1166 PVSCSIState *s = PVSCSI(d);
1167
1168 trace_pvscsi_state("reset");
1169 pvscsi_reset_adapter(s);
1170 }
1171
1172 static void
1173 pvscsi_pre_save(void *opaque)
1174 {
1175 PVSCSIState *s = (PVSCSIState *) opaque;
1176
1177 trace_pvscsi_state("presave");
1178
1179 assert(QTAILQ_EMPTY(&s->pending_queue));
1180 assert(QTAILQ_EMPTY(&s->completion_queue));
1181 }
1182
1183 static int
1184 pvscsi_post_load(void *opaque, int version_id)
1185 {
1186 trace_pvscsi_state("postload");
1187 return 0;
1188 }
1189
1190 static bool pvscsi_vmstate_need_pcie_device(void *opaque)
1191 {
1192 PVSCSIState *s = PVSCSI(opaque);
1193
1194 return !(s->compat_flags & PVSCSI_COMPAT_DISABLE_PCIE);
1195 }
1196
1197 static bool pvscsi_vmstate_test_pci_device(void *opaque, int version_id)
1198 {
1199 return !pvscsi_vmstate_need_pcie_device(opaque);
1200 }
1201
1202 static const VMStateDescription vmstate_pvscsi_pcie_device = {
1203 .name = "pvscsi/pcie",
1204 .needed = pvscsi_vmstate_need_pcie_device,
1205 .fields = (VMStateField[]) {
1206 VMSTATE_PCIE_DEVICE(parent_obj, PVSCSIState),
1207 VMSTATE_END_OF_LIST()
1208 }
1209 };
1210
1211 static const VMStateDescription vmstate_pvscsi = {
1212 .name = "pvscsi",
1213 .version_id = 0,
1214 .minimum_version_id = 0,
1215 .pre_save = pvscsi_pre_save,
1216 .post_load = pvscsi_post_load,
1217 .fields = (VMStateField[]) {
1218 VMSTATE_STRUCT_TEST(parent_obj, PVSCSIState,
1219 pvscsi_vmstate_test_pci_device, 0,
1220 vmstate_pci_device, PCIDevice),
1221 VMSTATE_UINT8(msi_used, PVSCSIState),
1222 VMSTATE_UINT32(resetting, PVSCSIState),
1223 VMSTATE_UINT64(reg_interrupt_status, PVSCSIState),
1224 VMSTATE_UINT64(reg_interrupt_enabled, PVSCSIState),
1225 VMSTATE_UINT64(reg_command_status, PVSCSIState),
1226 VMSTATE_UINT64(curr_cmd, PVSCSIState),
1227 VMSTATE_UINT32(curr_cmd_data_cntr, PVSCSIState),
1228 VMSTATE_UINT32_ARRAY(curr_cmd_data, PVSCSIState,
1229 ARRAY_SIZE(((PVSCSIState *)NULL)->curr_cmd_data)),
1230 VMSTATE_UINT8(rings_info_valid, PVSCSIState),
1231 VMSTATE_UINT8(msg_ring_info_valid, PVSCSIState),
1232 VMSTATE_UINT8(use_msg, PVSCSIState),
1233
1234 VMSTATE_UINT64(rings.rs_pa, PVSCSIState),
1235 VMSTATE_UINT32(rings.txr_len_mask, PVSCSIState),
1236 VMSTATE_UINT32(rings.rxr_len_mask, PVSCSIState),
1237 VMSTATE_UINT64_ARRAY(rings.req_ring_pages_pa, PVSCSIState,
1238 PVSCSI_SETUP_RINGS_MAX_NUM_PAGES),
1239 VMSTATE_UINT64_ARRAY(rings.cmp_ring_pages_pa, PVSCSIState,
1240 PVSCSI_SETUP_RINGS_MAX_NUM_PAGES),
1241 VMSTATE_UINT64(rings.consumed_ptr, PVSCSIState),
1242 VMSTATE_UINT64(rings.filled_cmp_ptr, PVSCSIState),
1243
1244 VMSTATE_END_OF_LIST()
1245 },
1246 .subsections = (const VMStateDescription*[]) {
1247 &vmstate_pvscsi_pcie_device,
1248 NULL
1249 }
1250 };
1251
1252 static Property pvscsi_properties[] = {
1253 DEFINE_PROP_UINT8("use_msg", PVSCSIState, use_msg, 1),
1254 DEFINE_PROP_BIT("x-old-pci-configuration", PVSCSIState, compat_flags,
1255 PVSCSI_COMPAT_OLD_PCI_CONFIGURATION_BIT, false),
1256 DEFINE_PROP_BIT("x-disable-pcie", PVSCSIState, compat_flags,
1257 PVSCSI_COMPAT_DISABLE_PCIE_BIT, false),
1258 DEFINE_PROP_END_OF_LIST(),
1259 };
1260
1261 static void pvscsi_realize(DeviceState *qdev, Error **errp)
1262 {
1263 PVSCSIClass *pvs_c = PVSCSI_DEVICE_GET_CLASS(qdev);
1264 PCIDevice *pci_dev = PCI_DEVICE(qdev);
1265 PVSCSIState *s = PVSCSI(qdev);
1266
1267 if (!(s->compat_flags & PVSCSI_COMPAT_DISABLE_PCIE)) {
1268 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1269 }
1270
1271 pvs_c->parent_dc_realize(qdev, errp);
1272 }
1273
1274 static void pvscsi_class_init(ObjectClass *klass, void *data)
1275 {
1276 DeviceClass *dc = DEVICE_CLASS(klass);
1277 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1278 PVSCSIClass *pvs_k = PVSCSI_DEVICE_CLASS(klass);
1279 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
1280
1281 k->init = pvscsi_init;
1282 k->exit = pvscsi_uninit;
1283 k->vendor_id = PCI_VENDOR_ID_VMWARE;
1284 k->device_id = PCI_DEVICE_ID_VMWARE_PVSCSI;
1285 k->class_id = PCI_CLASS_STORAGE_SCSI;
1286 k->subsystem_id = 0x1000;
1287 pvs_k->parent_dc_realize = dc->realize;
1288 dc->realize = pvscsi_realize;
1289 dc->reset = pvscsi_reset;
1290 dc->vmsd = &vmstate_pvscsi;
1291 dc->props = pvscsi_properties;
1292 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
1293 hc->unplug = pvscsi_hot_unplug;
1294 hc->plug = pvscsi_hotplug;
1295 }
1296
1297 static const TypeInfo pvscsi_info = {
1298 .name = TYPE_PVSCSI,
1299 .parent = TYPE_PCI_DEVICE,
1300 .class_size = sizeof(PVSCSIClass),
1301 .instance_size = sizeof(PVSCSIState),
1302 .class_init = pvscsi_class_init,
1303 .interfaces = (InterfaceInfo[]) {
1304 { TYPE_HOTPLUG_HANDLER },
1305 { }
1306 }
1307 };
1308
1309 static void
1310 pvscsi_register_types(void)
1311 {
1312 type_register_static(&pvscsi_info);
1313 }
1314
1315 type_init(pvscsi_register_types);