sm501: Add missing arbitration control register
[qemu.git] / hw / scsi / vmw_pvscsi.c
1 /*
2 * QEMU VMWARE PVSCSI paravirtual SCSI bus
3 *
4 * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com)
5 *
6 * Developed by Daynix Computing LTD (http://www.daynix.com)
7 *
8 * Based on implementation by Paolo Bonzini
9 * http://lists.gnu.org/archive/html/qemu-devel/2011-08/msg00729.html
10 *
11 * Authors:
12 * Paolo Bonzini <pbonzini@redhat.com>
13 * Dmitry Fleytman <dmitry@daynix.com>
14 * Yan Vugenfirer <yan@daynix.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2.
17 * See the COPYING file in the top-level directory.
18 *
19 * NOTE about MSI-X:
20 * MSI-X support has been removed for the moment because it leads Windows OS
21 * to crash on startup. The crash happens because Windows driver requires
22 * MSI-X shared memory to be part of the same BAR used for rings state
23 * registers, etc. This is not supported by QEMU infrastructure so separate
24 * BAR created from MSI-X purposes. Windows driver fails to deal with 2 BARs.
25 *
26 */
27
28 #include "qemu/osdep.h"
29 #include "qapi/error.h"
30 #include "hw/scsi/scsi.h"
31 #include "block/scsi.h"
32 #include "hw/pci/msi.h"
33 #include "vmw_pvscsi.h"
34 #include "trace.h"
35
36
37 #define PVSCSI_USE_64BIT (true)
38 #define PVSCSI_PER_VECTOR_MASK (false)
39
40 #define PVSCSI_MAX_DEVS (64)
41 #define PVSCSI_MSIX_NUM_VECTORS (1)
42
43 #define PVSCSI_MAX_SG_ELEM 2048
44
45 #define PVSCSI_MAX_CMD_DATA_WORDS \
46 (sizeof(PVSCSICmdDescSetupRings)/sizeof(uint32_t))
47
48 #define RS_GET_FIELD(m, field) \
49 (ldl_le_pci_dma(&container_of(m, PVSCSIState, rings)->parent_obj, \
50 (m)->rs_pa + offsetof(struct PVSCSIRingsState, field)))
51 #define RS_SET_FIELD(m, field, val) \
52 (stl_le_pci_dma(&container_of(m, PVSCSIState, rings)->parent_obj, \
53 (m)->rs_pa + offsetof(struct PVSCSIRingsState, field), val))
54
55 typedef struct PVSCSIClass {
56 PCIDeviceClass parent_class;
57 DeviceRealize parent_dc_realize;
58 } PVSCSIClass;
59
60 #define TYPE_PVSCSI "pvscsi"
61 #define PVSCSI(obj) OBJECT_CHECK(PVSCSIState, (obj), TYPE_PVSCSI)
62
63 #define PVSCSI_DEVICE_CLASS(klass) \
64 OBJECT_CLASS_CHECK(PVSCSIClass, (klass), TYPE_PVSCSI)
65 #define PVSCSI_DEVICE_GET_CLASS(obj) \
66 OBJECT_GET_CLASS(PVSCSIClass, (obj), TYPE_PVSCSI)
67
68 /* Compatibility flags for migration */
69 #define PVSCSI_COMPAT_OLD_PCI_CONFIGURATION_BIT 0
70 #define PVSCSI_COMPAT_OLD_PCI_CONFIGURATION \
71 (1 << PVSCSI_COMPAT_OLD_PCI_CONFIGURATION_BIT)
72 #define PVSCSI_COMPAT_DISABLE_PCIE_BIT 1
73 #define PVSCSI_COMPAT_DISABLE_PCIE \
74 (1 << PVSCSI_COMPAT_DISABLE_PCIE_BIT)
75
76 #define PVSCSI_USE_OLD_PCI_CONFIGURATION(s) \
77 ((s)->compat_flags & PVSCSI_COMPAT_OLD_PCI_CONFIGURATION)
78 #define PVSCSI_MSI_OFFSET(s) \
79 (PVSCSI_USE_OLD_PCI_CONFIGURATION(s) ? 0x50 : 0x7c)
80 #define PVSCSI_EXP_EP_OFFSET (0x40)
81
82 typedef struct PVSCSIRingInfo {
83 uint64_t rs_pa;
84 uint32_t txr_len_mask;
85 uint32_t rxr_len_mask;
86 uint32_t msg_len_mask;
87 uint64_t req_ring_pages_pa[PVSCSI_SETUP_RINGS_MAX_NUM_PAGES];
88 uint64_t cmp_ring_pages_pa[PVSCSI_SETUP_RINGS_MAX_NUM_PAGES];
89 uint64_t msg_ring_pages_pa[PVSCSI_SETUP_MSG_RING_MAX_NUM_PAGES];
90 uint64_t consumed_ptr;
91 uint64_t filled_cmp_ptr;
92 uint64_t filled_msg_ptr;
93 } PVSCSIRingInfo;
94
95 typedef struct PVSCSISGState {
96 hwaddr elemAddr;
97 hwaddr dataAddr;
98 uint32_t resid;
99 } PVSCSISGState;
100
101 typedef QTAILQ_HEAD(, PVSCSIRequest) PVSCSIRequestList;
102
103 typedef struct {
104 PCIDevice parent_obj;
105 MemoryRegion io_space;
106 SCSIBus bus;
107 QEMUBH *completion_worker;
108 PVSCSIRequestList pending_queue;
109 PVSCSIRequestList completion_queue;
110
111 uint64_t reg_interrupt_status; /* Interrupt status register value */
112 uint64_t reg_interrupt_enabled; /* Interrupt mask register value */
113 uint64_t reg_command_status; /* Command status register value */
114
115 /* Command data adoption mechanism */
116 uint64_t curr_cmd; /* Last command arrived */
117 uint32_t curr_cmd_data_cntr; /* Amount of data for last command */
118
119 /* Collector for current command data */
120 uint32_t curr_cmd_data[PVSCSI_MAX_CMD_DATA_WORDS];
121
122 uint8_t rings_info_valid; /* Whether data rings initialized */
123 uint8_t msg_ring_info_valid; /* Whether message ring initialized */
124 uint8_t use_msg; /* Whether to use message ring */
125
126 uint8_t msi_used; /* For migration compatibility */
127 PVSCSIRingInfo rings; /* Data transfer rings manager */
128 uint32_t resetting; /* Reset in progress */
129
130 uint32_t compat_flags;
131 } PVSCSIState;
132
133 typedef struct PVSCSIRequest {
134 SCSIRequest *sreq;
135 PVSCSIState *dev;
136 uint8_t sense_key;
137 uint8_t completed;
138 int lun;
139 QEMUSGList sgl;
140 PVSCSISGState sg;
141 struct PVSCSIRingReqDesc req;
142 struct PVSCSIRingCmpDesc cmp;
143 QTAILQ_ENTRY(PVSCSIRequest) next;
144 } PVSCSIRequest;
145
146 /* Integer binary logarithm */
147 static int
148 pvscsi_log2(uint32_t input)
149 {
150 int log = 0;
151 assert(input > 0);
152 while (input >> ++log) {
153 }
154 return log;
155 }
156
157 static void
158 pvscsi_ring_init_data(PVSCSIRingInfo *m, PVSCSICmdDescSetupRings *ri)
159 {
160 int i;
161 uint32_t txr_len_log2, rxr_len_log2;
162 uint32_t req_ring_size, cmp_ring_size;
163 m->rs_pa = ri->ringsStatePPN << VMW_PAGE_SHIFT;
164
165 req_ring_size = ri->reqRingNumPages * PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE;
166 cmp_ring_size = ri->cmpRingNumPages * PVSCSI_MAX_NUM_CMP_ENTRIES_PER_PAGE;
167 txr_len_log2 = pvscsi_log2(req_ring_size - 1);
168 rxr_len_log2 = pvscsi_log2(cmp_ring_size - 1);
169
170 m->txr_len_mask = MASK(txr_len_log2);
171 m->rxr_len_mask = MASK(rxr_len_log2);
172
173 m->consumed_ptr = 0;
174 m->filled_cmp_ptr = 0;
175
176 for (i = 0; i < ri->reqRingNumPages; i++) {
177 m->req_ring_pages_pa[i] = ri->reqRingPPNs[i] << VMW_PAGE_SHIFT;
178 }
179
180 for (i = 0; i < ri->cmpRingNumPages; i++) {
181 m->cmp_ring_pages_pa[i] = ri->cmpRingPPNs[i] << VMW_PAGE_SHIFT;
182 }
183
184 RS_SET_FIELD(m, reqProdIdx, 0);
185 RS_SET_FIELD(m, reqConsIdx, 0);
186 RS_SET_FIELD(m, reqNumEntriesLog2, txr_len_log2);
187
188 RS_SET_FIELD(m, cmpProdIdx, 0);
189 RS_SET_FIELD(m, cmpConsIdx, 0);
190 RS_SET_FIELD(m, cmpNumEntriesLog2, rxr_len_log2);
191
192 trace_pvscsi_ring_init_data(txr_len_log2, rxr_len_log2);
193
194 /* Flush ring state page changes */
195 smp_wmb();
196 }
197
198 static int
199 pvscsi_ring_init_msg(PVSCSIRingInfo *m, PVSCSICmdDescSetupMsgRing *ri)
200 {
201 int i;
202 uint32_t len_log2;
203 uint32_t ring_size;
204
205 if (ri->numPages > PVSCSI_SETUP_MSG_RING_MAX_NUM_PAGES) {
206 return -1;
207 }
208 ring_size = ri->numPages * PVSCSI_MAX_NUM_MSG_ENTRIES_PER_PAGE;
209 len_log2 = pvscsi_log2(ring_size - 1);
210
211 m->msg_len_mask = MASK(len_log2);
212
213 m->filled_msg_ptr = 0;
214
215 for (i = 0; i < ri->numPages; i++) {
216 m->msg_ring_pages_pa[i] = ri->ringPPNs[i] << VMW_PAGE_SHIFT;
217 }
218
219 RS_SET_FIELD(m, msgProdIdx, 0);
220 RS_SET_FIELD(m, msgConsIdx, 0);
221 RS_SET_FIELD(m, msgNumEntriesLog2, len_log2);
222
223 trace_pvscsi_ring_init_msg(len_log2);
224
225 /* Flush ring state page changes */
226 smp_wmb();
227
228 return 0;
229 }
230
231 static void
232 pvscsi_ring_cleanup(PVSCSIRingInfo *mgr)
233 {
234 mgr->rs_pa = 0;
235 mgr->txr_len_mask = 0;
236 mgr->rxr_len_mask = 0;
237 mgr->msg_len_mask = 0;
238 mgr->consumed_ptr = 0;
239 mgr->filled_cmp_ptr = 0;
240 mgr->filled_msg_ptr = 0;
241 memset(mgr->req_ring_pages_pa, 0, sizeof(mgr->req_ring_pages_pa));
242 memset(mgr->cmp_ring_pages_pa, 0, sizeof(mgr->cmp_ring_pages_pa));
243 memset(mgr->msg_ring_pages_pa, 0, sizeof(mgr->msg_ring_pages_pa));
244 }
245
246 static hwaddr
247 pvscsi_ring_pop_req_descr(PVSCSIRingInfo *mgr)
248 {
249 uint32_t ready_ptr = RS_GET_FIELD(mgr, reqProdIdx);
250 uint32_t ring_size = PVSCSI_MAX_NUM_PAGES_REQ_RING
251 * PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE;
252
253 if (ready_ptr != mgr->consumed_ptr
254 && ready_ptr - mgr->consumed_ptr < ring_size) {
255 uint32_t next_ready_ptr =
256 mgr->consumed_ptr++ & mgr->txr_len_mask;
257 uint32_t next_ready_page =
258 next_ready_ptr / PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE;
259 uint32_t inpage_idx =
260 next_ready_ptr % PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE;
261
262 return mgr->req_ring_pages_pa[next_ready_page] +
263 inpage_idx * sizeof(PVSCSIRingReqDesc);
264 } else {
265 return 0;
266 }
267 }
268
269 static void
270 pvscsi_ring_flush_req(PVSCSIRingInfo *mgr)
271 {
272 RS_SET_FIELD(mgr, reqConsIdx, mgr->consumed_ptr);
273 }
274
275 static hwaddr
276 pvscsi_ring_pop_cmp_descr(PVSCSIRingInfo *mgr)
277 {
278 /*
279 * According to Linux driver code it explicitly verifies that number
280 * of requests being processed by device is less then the size of
281 * completion queue, so device may omit completion queue overflow
282 * conditions check. We assume that this is true for other (Windows)
283 * drivers as well.
284 */
285
286 uint32_t free_cmp_ptr =
287 mgr->filled_cmp_ptr++ & mgr->rxr_len_mask;
288 uint32_t free_cmp_page =
289 free_cmp_ptr / PVSCSI_MAX_NUM_CMP_ENTRIES_PER_PAGE;
290 uint32_t inpage_idx =
291 free_cmp_ptr % PVSCSI_MAX_NUM_CMP_ENTRIES_PER_PAGE;
292 return mgr->cmp_ring_pages_pa[free_cmp_page] +
293 inpage_idx * sizeof(PVSCSIRingCmpDesc);
294 }
295
296 static hwaddr
297 pvscsi_ring_pop_msg_descr(PVSCSIRingInfo *mgr)
298 {
299 uint32_t free_msg_ptr =
300 mgr->filled_msg_ptr++ & mgr->msg_len_mask;
301 uint32_t free_msg_page =
302 free_msg_ptr / PVSCSI_MAX_NUM_MSG_ENTRIES_PER_PAGE;
303 uint32_t inpage_idx =
304 free_msg_ptr % PVSCSI_MAX_NUM_MSG_ENTRIES_PER_PAGE;
305 return mgr->msg_ring_pages_pa[free_msg_page] +
306 inpage_idx * sizeof(PVSCSIRingMsgDesc);
307 }
308
309 static void
310 pvscsi_ring_flush_cmp(PVSCSIRingInfo *mgr)
311 {
312 /* Flush descriptor changes */
313 smp_wmb();
314
315 trace_pvscsi_ring_flush_cmp(mgr->filled_cmp_ptr);
316
317 RS_SET_FIELD(mgr, cmpProdIdx, mgr->filled_cmp_ptr);
318 }
319
320 static bool
321 pvscsi_ring_msg_has_room(PVSCSIRingInfo *mgr)
322 {
323 uint32_t prodIdx = RS_GET_FIELD(mgr, msgProdIdx);
324 uint32_t consIdx = RS_GET_FIELD(mgr, msgConsIdx);
325
326 return (prodIdx - consIdx) < (mgr->msg_len_mask + 1);
327 }
328
329 static void
330 pvscsi_ring_flush_msg(PVSCSIRingInfo *mgr)
331 {
332 /* Flush descriptor changes */
333 smp_wmb();
334
335 trace_pvscsi_ring_flush_msg(mgr->filled_msg_ptr);
336
337 RS_SET_FIELD(mgr, msgProdIdx, mgr->filled_msg_ptr);
338 }
339
340 static void
341 pvscsi_reset_state(PVSCSIState *s)
342 {
343 s->curr_cmd = PVSCSI_CMD_FIRST;
344 s->curr_cmd_data_cntr = 0;
345 s->reg_command_status = PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
346 s->reg_interrupt_status = 0;
347 pvscsi_ring_cleanup(&s->rings);
348 s->rings_info_valid = FALSE;
349 s->msg_ring_info_valid = FALSE;
350 QTAILQ_INIT(&s->pending_queue);
351 QTAILQ_INIT(&s->completion_queue);
352 }
353
354 static void
355 pvscsi_update_irq_status(PVSCSIState *s)
356 {
357 PCIDevice *d = PCI_DEVICE(s);
358 bool should_raise = s->reg_interrupt_enabled & s->reg_interrupt_status;
359
360 trace_pvscsi_update_irq_level(should_raise, s->reg_interrupt_enabled,
361 s->reg_interrupt_status);
362
363 if (msi_enabled(d)) {
364 if (should_raise) {
365 trace_pvscsi_update_irq_msi();
366 msi_notify(d, PVSCSI_VECTOR_COMPLETION);
367 }
368 return;
369 }
370
371 pci_set_irq(d, !!should_raise);
372 }
373
374 static void
375 pvscsi_raise_completion_interrupt(PVSCSIState *s)
376 {
377 s->reg_interrupt_status |= PVSCSI_INTR_CMPL_0;
378
379 /* Memory barrier to flush interrupt status register changes*/
380 smp_wmb();
381
382 pvscsi_update_irq_status(s);
383 }
384
385 static void
386 pvscsi_raise_message_interrupt(PVSCSIState *s)
387 {
388 s->reg_interrupt_status |= PVSCSI_INTR_MSG_0;
389
390 /* Memory barrier to flush interrupt status register changes*/
391 smp_wmb();
392
393 pvscsi_update_irq_status(s);
394 }
395
396 static void
397 pvscsi_cmp_ring_put(PVSCSIState *s, struct PVSCSIRingCmpDesc *cmp_desc)
398 {
399 hwaddr cmp_descr_pa;
400
401 cmp_descr_pa = pvscsi_ring_pop_cmp_descr(&s->rings);
402 trace_pvscsi_cmp_ring_put(cmp_descr_pa);
403 cpu_physical_memory_write(cmp_descr_pa, (void *)cmp_desc,
404 sizeof(*cmp_desc));
405 }
406
407 static void
408 pvscsi_msg_ring_put(PVSCSIState *s, struct PVSCSIRingMsgDesc *msg_desc)
409 {
410 hwaddr msg_descr_pa;
411
412 msg_descr_pa = pvscsi_ring_pop_msg_descr(&s->rings);
413 trace_pvscsi_msg_ring_put(msg_descr_pa);
414 cpu_physical_memory_write(msg_descr_pa, (void *)msg_desc,
415 sizeof(*msg_desc));
416 }
417
418 static void
419 pvscsi_process_completion_queue(void *opaque)
420 {
421 PVSCSIState *s = opaque;
422 PVSCSIRequest *pvscsi_req;
423 bool has_completed = false;
424
425 while (!QTAILQ_EMPTY(&s->completion_queue)) {
426 pvscsi_req = QTAILQ_FIRST(&s->completion_queue);
427 QTAILQ_REMOVE(&s->completion_queue, pvscsi_req, next);
428 pvscsi_cmp_ring_put(s, &pvscsi_req->cmp);
429 g_free(pvscsi_req);
430 has_completed = true;
431 }
432
433 if (has_completed) {
434 pvscsi_ring_flush_cmp(&s->rings);
435 pvscsi_raise_completion_interrupt(s);
436 }
437 }
438
439 static void
440 pvscsi_reset_adapter(PVSCSIState *s)
441 {
442 s->resetting++;
443 qbus_reset_all_fn(&s->bus);
444 s->resetting--;
445 pvscsi_process_completion_queue(s);
446 assert(QTAILQ_EMPTY(&s->pending_queue));
447 pvscsi_reset_state(s);
448 }
449
450 static void
451 pvscsi_schedule_completion_processing(PVSCSIState *s)
452 {
453 /* Try putting more complete requests on the ring. */
454 if (!QTAILQ_EMPTY(&s->completion_queue)) {
455 qemu_bh_schedule(s->completion_worker);
456 }
457 }
458
459 static void
460 pvscsi_complete_request(PVSCSIState *s, PVSCSIRequest *r)
461 {
462 assert(!r->completed);
463
464 trace_pvscsi_complete_request(r->cmp.context, r->cmp.dataLen,
465 r->sense_key);
466 if (r->sreq != NULL) {
467 scsi_req_unref(r->sreq);
468 r->sreq = NULL;
469 }
470 r->completed = 1;
471 QTAILQ_REMOVE(&s->pending_queue, r, next);
472 QTAILQ_INSERT_TAIL(&s->completion_queue, r, next);
473 pvscsi_schedule_completion_processing(s);
474 }
475
476 static QEMUSGList *pvscsi_get_sg_list(SCSIRequest *r)
477 {
478 PVSCSIRequest *req = r->hba_private;
479
480 trace_pvscsi_get_sg_list(req->sgl.nsg, req->sgl.size);
481
482 return &req->sgl;
483 }
484
485 static void
486 pvscsi_get_next_sg_elem(PVSCSISGState *sg)
487 {
488 struct PVSCSISGElement elem;
489
490 cpu_physical_memory_read(sg->elemAddr, (void *)&elem, sizeof(elem));
491 if ((elem.flags & ~PVSCSI_KNOWN_FLAGS) != 0) {
492 /*
493 * There is PVSCSI_SGE_FLAG_CHAIN_ELEMENT flag described in
494 * header file but its value is unknown. This flag requires
495 * additional processing, so we put warning here to catch it
496 * some day and make proper implementation
497 */
498 trace_pvscsi_get_next_sg_elem(elem.flags);
499 }
500
501 sg->elemAddr += sizeof(elem);
502 sg->dataAddr = elem.addr;
503 sg->resid = elem.length;
504 }
505
506 static void
507 pvscsi_write_sense(PVSCSIRequest *r, uint8_t *sense, int len)
508 {
509 r->cmp.senseLen = MIN(r->req.senseLen, len);
510 r->sense_key = sense[(sense[0] & 2) ? 1 : 2];
511 cpu_physical_memory_write(r->req.senseAddr, sense, r->cmp.senseLen);
512 }
513
514 static void
515 pvscsi_command_complete(SCSIRequest *req, uint32_t status, size_t resid)
516 {
517 PVSCSIRequest *pvscsi_req = req->hba_private;
518 PVSCSIState *s;
519
520 if (!pvscsi_req) {
521 trace_pvscsi_command_complete_not_found(req->tag);
522 return;
523 }
524 s = pvscsi_req->dev;
525
526 if (resid) {
527 /* Short transfer. */
528 trace_pvscsi_command_complete_data_run();
529 pvscsi_req->cmp.hostStatus = BTSTAT_DATARUN;
530 }
531
532 pvscsi_req->cmp.scsiStatus = status;
533 if (pvscsi_req->cmp.scsiStatus == CHECK_CONDITION) {
534 uint8_t sense[SCSI_SENSE_BUF_SIZE];
535 int sense_len =
536 scsi_req_get_sense(pvscsi_req->sreq, sense, sizeof(sense));
537
538 trace_pvscsi_command_complete_sense_len(sense_len);
539 pvscsi_write_sense(pvscsi_req, sense, sense_len);
540 }
541 qemu_sglist_destroy(&pvscsi_req->sgl);
542 pvscsi_complete_request(s, pvscsi_req);
543 }
544
545 static void
546 pvscsi_send_msg(PVSCSIState *s, SCSIDevice *dev, uint32_t msg_type)
547 {
548 if (s->msg_ring_info_valid && pvscsi_ring_msg_has_room(&s->rings)) {
549 PVSCSIMsgDescDevStatusChanged msg = {0};
550
551 msg.type = msg_type;
552 msg.bus = dev->channel;
553 msg.target = dev->id;
554 msg.lun[1] = dev->lun;
555
556 pvscsi_msg_ring_put(s, (PVSCSIRingMsgDesc *)&msg);
557 pvscsi_ring_flush_msg(&s->rings);
558 pvscsi_raise_message_interrupt(s);
559 }
560 }
561
562 static void
563 pvscsi_hotplug(HotplugHandler *hotplug_dev, DeviceState *dev, Error **errp)
564 {
565 PVSCSIState *s = PVSCSI(hotplug_dev);
566
567 pvscsi_send_msg(s, SCSI_DEVICE(dev), PVSCSI_MSG_DEV_ADDED);
568 }
569
570 static void
571 pvscsi_hot_unplug(HotplugHandler *hotplug_dev, DeviceState *dev, Error **errp)
572 {
573 PVSCSIState *s = PVSCSI(hotplug_dev);
574
575 pvscsi_send_msg(s, SCSI_DEVICE(dev), PVSCSI_MSG_DEV_REMOVED);
576 qdev_simple_device_unplug_cb(hotplug_dev, dev, errp);
577 }
578
579 static void
580 pvscsi_request_cancelled(SCSIRequest *req)
581 {
582 PVSCSIRequest *pvscsi_req = req->hba_private;
583 PVSCSIState *s = pvscsi_req->dev;
584
585 if (pvscsi_req->completed) {
586 return;
587 }
588
589 if (pvscsi_req->dev->resetting) {
590 pvscsi_req->cmp.hostStatus = BTSTAT_BUSRESET;
591 } else {
592 pvscsi_req->cmp.hostStatus = BTSTAT_ABORTQUEUE;
593 }
594
595 pvscsi_complete_request(s, pvscsi_req);
596 }
597
598 static SCSIDevice*
599 pvscsi_device_find(PVSCSIState *s, int channel, int target,
600 uint8_t *requested_lun, uint8_t *target_lun)
601 {
602 if (requested_lun[0] || requested_lun[2] || requested_lun[3] ||
603 requested_lun[4] || requested_lun[5] || requested_lun[6] ||
604 requested_lun[7] || (target > PVSCSI_MAX_DEVS)) {
605 return NULL;
606 } else {
607 *target_lun = requested_lun[1];
608 return scsi_device_find(&s->bus, channel, target, *target_lun);
609 }
610 }
611
612 static PVSCSIRequest *
613 pvscsi_queue_pending_descriptor(PVSCSIState *s, SCSIDevice **d,
614 struct PVSCSIRingReqDesc *descr)
615 {
616 PVSCSIRequest *pvscsi_req;
617 uint8_t lun;
618
619 pvscsi_req = g_malloc0(sizeof(*pvscsi_req));
620 pvscsi_req->dev = s;
621 pvscsi_req->req = *descr;
622 pvscsi_req->cmp.context = pvscsi_req->req.context;
623 QTAILQ_INSERT_TAIL(&s->pending_queue, pvscsi_req, next);
624
625 *d = pvscsi_device_find(s, descr->bus, descr->target, descr->lun, &lun);
626 if (*d) {
627 pvscsi_req->lun = lun;
628 }
629
630 return pvscsi_req;
631 }
632
633 static void
634 pvscsi_convert_sglist(PVSCSIRequest *r)
635 {
636 uint32_t chunk_size, elmcnt = 0;
637 uint64_t data_length = r->req.dataLen;
638 PVSCSISGState sg = r->sg;
639 while (data_length && elmcnt < PVSCSI_MAX_SG_ELEM) {
640 while (!sg.resid && elmcnt++ < PVSCSI_MAX_SG_ELEM) {
641 pvscsi_get_next_sg_elem(&sg);
642 trace_pvscsi_convert_sglist(r->req.context, r->sg.dataAddr,
643 r->sg.resid);
644 }
645 chunk_size = MIN(data_length, sg.resid);
646 if (chunk_size) {
647 qemu_sglist_add(&r->sgl, sg.dataAddr, chunk_size);
648 }
649
650 sg.dataAddr += chunk_size;
651 data_length -= chunk_size;
652 sg.resid -= chunk_size;
653 }
654 }
655
656 static void
657 pvscsi_build_sglist(PVSCSIState *s, PVSCSIRequest *r)
658 {
659 PCIDevice *d = PCI_DEVICE(s);
660
661 pci_dma_sglist_init(&r->sgl, d, 1);
662 if (r->req.flags & PVSCSI_FLAG_CMD_WITH_SG_LIST) {
663 pvscsi_convert_sglist(r);
664 } else {
665 qemu_sglist_add(&r->sgl, r->req.dataAddr, r->req.dataLen);
666 }
667 }
668
669 static void
670 pvscsi_process_request_descriptor(PVSCSIState *s,
671 struct PVSCSIRingReqDesc *descr)
672 {
673 SCSIDevice *d;
674 PVSCSIRequest *r = pvscsi_queue_pending_descriptor(s, &d, descr);
675 int64_t n;
676
677 trace_pvscsi_process_req_descr(descr->cdb[0], descr->context);
678
679 if (!d) {
680 r->cmp.hostStatus = BTSTAT_SELTIMEO;
681 trace_pvscsi_process_req_descr_unknown_device();
682 pvscsi_complete_request(s, r);
683 return;
684 }
685
686 if (descr->flags & PVSCSI_FLAG_CMD_WITH_SG_LIST) {
687 r->sg.elemAddr = descr->dataAddr;
688 }
689
690 r->sreq = scsi_req_new(d, descr->context, r->lun, descr->cdb, r);
691 if (r->sreq->cmd.mode == SCSI_XFER_FROM_DEV &&
692 (descr->flags & PVSCSI_FLAG_CMD_DIR_TODEVICE)) {
693 r->cmp.hostStatus = BTSTAT_BADMSG;
694 trace_pvscsi_process_req_descr_invalid_dir();
695 scsi_req_cancel(r->sreq);
696 return;
697 }
698 if (r->sreq->cmd.mode == SCSI_XFER_TO_DEV &&
699 (descr->flags & PVSCSI_FLAG_CMD_DIR_TOHOST)) {
700 r->cmp.hostStatus = BTSTAT_BADMSG;
701 trace_pvscsi_process_req_descr_invalid_dir();
702 scsi_req_cancel(r->sreq);
703 return;
704 }
705
706 pvscsi_build_sglist(s, r);
707 n = scsi_req_enqueue(r->sreq);
708
709 if (n) {
710 scsi_req_continue(r->sreq);
711 }
712 }
713
714 static void
715 pvscsi_process_io(PVSCSIState *s)
716 {
717 PVSCSIRingReqDesc descr;
718 hwaddr next_descr_pa;
719
720 assert(s->rings_info_valid);
721 while ((next_descr_pa = pvscsi_ring_pop_req_descr(&s->rings)) != 0) {
722
723 /* Only read after production index verification */
724 smp_rmb();
725
726 trace_pvscsi_process_io(next_descr_pa);
727 cpu_physical_memory_read(next_descr_pa, &descr, sizeof(descr));
728 pvscsi_process_request_descriptor(s, &descr);
729 }
730
731 pvscsi_ring_flush_req(&s->rings);
732 }
733
734 static void
735 pvscsi_dbg_dump_tx_rings_config(PVSCSICmdDescSetupRings *rc)
736 {
737 int i;
738 trace_pvscsi_tx_rings_ppn("Rings State", rc->ringsStatePPN);
739
740 trace_pvscsi_tx_rings_num_pages("Request Ring", rc->reqRingNumPages);
741 for (i = 0; i < rc->reqRingNumPages; i++) {
742 trace_pvscsi_tx_rings_ppn("Request Ring", rc->reqRingPPNs[i]);
743 }
744
745 trace_pvscsi_tx_rings_num_pages("Confirm Ring", rc->cmpRingNumPages);
746 for (i = 0; i < rc->cmpRingNumPages; i++) {
747 trace_pvscsi_tx_rings_ppn("Confirm Ring", rc->cmpRingPPNs[i]);
748 }
749 }
750
751 static uint64_t
752 pvscsi_on_cmd_config(PVSCSIState *s)
753 {
754 trace_pvscsi_on_cmd_noimpl("PVSCSI_CMD_CONFIG");
755 return PVSCSI_COMMAND_PROCESSING_FAILED;
756 }
757
758 static uint64_t
759 pvscsi_on_cmd_unplug(PVSCSIState *s)
760 {
761 trace_pvscsi_on_cmd_noimpl("PVSCSI_CMD_DEVICE_UNPLUG");
762 return PVSCSI_COMMAND_PROCESSING_FAILED;
763 }
764
765 static uint64_t
766 pvscsi_on_issue_scsi(PVSCSIState *s)
767 {
768 trace_pvscsi_on_cmd_noimpl("PVSCSI_CMD_ISSUE_SCSI");
769 return PVSCSI_COMMAND_PROCESSING_FAILED;
770 }
771
772 static uint64_t
773 pvscsi_on_cmd_setup_rings(PVSCSIState *s)
774 {
775 PVSCSICmdDescSetupRings *rc =
776 (PVSCSICmdDescSetupRings *) s->curr_cmd_data;
777
778 trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_SETUP_RINGS");
779
780 if (!rc->reqRingNumPages
781 || rc->reqRingNumPages > PVSCSI_SETUP_RINGS_MAX_NUM_PAGES
782 || !rc->cmpRingNumPages
783 || rc->cmpRingNumPages > PVSCSI_SETUP_RINGS_MAX_NUM_PAGES) {
784 return PVSCSI_COMMAND_PROCESSING_FAILED;
785 }
786
787 pvscsi_dbg_dump_tx_rings_config(rc);
788 pvscsi_ring_init_data(&s->rings, rc);
789
790 s->rings_info_valid = TRUE;
791 return PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
792 }
793
794 static uint64_t
795 pvscsi_on_cmd_abort(PVSCSIState *s)
796 {
797 PVSCSICmdDescAbortCmd *cmd = (PVSCSICmdDescAbortCmd *) s->curr_cmd_data;
798 PVSCSIRequest *r, *next;
799
800 trace_pvscsi_on_cmd_abort(cmd->context, cmd->target);
801
802 QTAILQ_FOREACH_SAFE(r, &s->pending_queue, next, next) {
803 if (r->req.context == cmd->context) {
804 break;
805 }
806 }
807 if (r) {
808 assert(!r->completed);
809 r->cmp.hostStatus = BTSTAT_ABORTQUEUE;
810 scsi_req_cancel(r->sreq);
811 }
812
813 return PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
814 }
815
816 static uint64_t
817 pvscsi_on_cmd_unknown(PVSCSIState *s)
818 {
819 trace_pvscsi_on_cmd_unknown_data(s->curr_cmd_data[0]);
820 return PVSCSI_COMMAND_PROCESSING_FAILED;
821 }
822
823 static uint64_t
824 pvscsi_on_cmd_reset_device(PVSCSIState *s)
825 {
826 uint8_t target_lun = 0;
827 struct PVSCSICmdDescResetDevice *cmd =
828 (struct PVSCSICmdDescResetDevice *) s->curr_cmd_data;
829 SCSIDevice *sdev;
830
831 sdev = pvscsi_device_find(s, 0, cmd->target, cmd->lun, &target_lun);
832
833 trace_pvscsi_on_cmd_reset_dev(cmd->target, (int) target_lun, sdev);
834
835 if (sdev != NULL) {
836 s->resetting++;
837 device_reset(&sdev->qdev);
838 s->resetting--;
839 return PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
840 }
841
842 return PVSCSI_COMMAND_PROCESSING_FAILED;
843 }
844
845 static uint64_t
846 pvscsi_on_cmd_reset_bus(PVSCSIState *s)
847 {
848 trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_RESET_BUS");
849
850 s->resetting++;
851 qbus_reset_all_fn(&s->bus);
852 s->resetting--;
853 return PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
854 }
855
856 static uint64_t
857 pvscsi_on_cmd_setup_msg_ring(PVSCSIState *s)
858 {
859 PVSCSICmdDescSetupMsgRing *rc =
860 (PVSCSICmdDescSetupMsgRing *) s->curr_cmd_data;
861
862 trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_SETUP_MSG_RING");
863
864 if (!s->use_msg) {
865 return PVSCSI_COMMAND_PROCESSING_FAILED;
866 }
867
868 if (s->rings_info_valid) {
869 if (pvscsi_ring_init_msg(&s->rings, rc) < 0) {
870 return PVSCSI_COMMAND_PROCESSING_FAILED;
871 }
872 s->msg_ring_info_valid = TRUE;
873 }
874 return sizeof(PVSCSICmdDescSetupMsgRing) / sizeof(uint32_t);
875 }
876
877 static uint64_t
878 pvscsi_on_cmd_adapter_reset(PVSCSIState *s)
879 {
880 trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_ADAPTER_RESET");
881
882 pvscsi_reset_adapter(s);
883 return PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
884 }
885
886 static const struct {
887 int data_size;
888 uint64_t (*handler_fn)(PVSCSIState *s);
889 } pvscsi_commands[] = {
890 [PVSCSI_CMD_FIRST] = {
891 .data_size = 0,
892 .handler_fn = pvscsi_on_cmd_unknown,
893 },
894
895 /* Not implemented, data size defined based on what arrives on windows */
896 [PVSCSI_CMD_CONFIG] = {
897 .data_size = 6 * sizeof(uint32_t),
898 .handler_fn = pvscsi_on_cmd_config,
899 },
900
901 /* Command not implemented, data size is unknown */
902 [PVSCSI_CMD_ISSUE_SCSI] = {
903 .data_size = 0,
904 .handler_fn = pvscsi_on_issue_scsi,
905 },
906
907 /* Command not implemented, data size is unknown */
908 [PVSCSI_CMD_DEVICE_UNPLUG] = {
909 .data_size = 0,
910 .handler_fn = pvscsi_on_cmd_unplug,
911 },
912
913 [PVSCSI_CMD_SETUP_RINGS] = {
914 .data_size = sizeof(PVSCSICmdDescSetupRings),
915 .handler_fn = pvscsi_on_cmd_setup_rings,
916 },
917
918 [PVSCSI_CMD_RESET_DEVICE] = {
919 .data_size = sizeof(struct PVSCSICmdDescResetDevice),
920 .handler_fn = pvscsi_on_cmd_reset_device,
921 },
922
923 [PVSCSI_CMD_RESET_BUS] = {
924 .data_size = 0,
925 .handler_fn = pvscsi_on_cmd_reset_bus,
926 },
927
928 [PVSCSI_CMD_SETUP_MSG_RING] = {
929 .data_size = sizeof(PVSCSICmdDescSetupMsgRing),
930 .handler_fn = pvscsi_on_cmd_setup_msg_ring,
931 },
932
933 [PVSCSI_CMD_ADAPTER_RESET] = {
934 .data_size = 0,
935 .handler_fn = pvscsi_on_cmd_adapter_reset,
936 },
937
938 [PVSCSI_CMD_ABORT_CMD] = {
939 .data_size = sizeof(struct PVSCSICmdDescAbortCmd),
940 .handler_fn = pvscsi_on_cmd_abort,
941 },
942 };
943
944 static void
945 pvscsi_do_command_processing(PVSCSIState *s)
946 {
947 size_t bytes_arrived = s->curr_cmd_data_cntr * sizeof(uint32_t);
948
949 assert(s->curr_cmd < PVSCSI_CMD_LAST);
950 if (bytes_arrived >= pvscsi_commands[s->curr_cmd].data_size) {
951 s->reg_command_status = pvscsi_commands[s->curr_cmd].handler_fn(s);
952 s->curr_cmd = PVSCSI_CMD_FIRST;
953 s->curr_cmd_data_cntr = 0;
954 }
955 }
956
957 static void
958 pvscsi_on_command_data(PVSCSIState *s, uint32_t value)
959 {
960 size_t bytes_arrived = s->curr_cmd_data_cntr * sizeof(uint32_t);
961
962 assert(bytes_arrived < sizeof(s->curr_cmd_data));
963 s->curr_cmd_data[s->curr_cmd_data_cntr++] = value;
964
965 pvscsi_do_command_processing(s);
966 }
967
968 static void
969 pvscsi_on_command(PVSCSIState *s, uint64_t cmd_id)
970 {
971 if ((cmd_id > PVSCSI_CMD_FIRST) && (cmd_id < PVSCSI_CMD_LAST)) {
972 s->curr_cmd = cmd_id;
973 } else {
974 s->curr_cmd = PVSCSI_CMD_FIRST;
975 trace_pvscsi_on_cmd_unknown(cmd_id);
976 }
977
978 s->curr_cmd_data_cntr = 0;
979 s->reg_command_status = PVSCSI_COMMAND_NOT_ENOUGH_DATA;
980
981 pvscsi_do_command_processing(s);
982 }
983
984 static void
985 pvscsi_io_write(void *opaque, hwaddr addr,
986 uint64_t val, unsigned size)
987 {
988 PVSCSIState *s = opaque;
989
990 switch (addr) {
991 case PVSCSI_REG_OFFSET_COMMAND:
992 pvscsi_on_command(s, val);
993 break;
994
995 case PVSCSI_REG_OFFSET_COMMAND_DATA:
996 pvscsi_on_command_data(s, (uint32_t) val);
997 break;
998
999 case PVSCSI_REG_OFFSET_INTR_STATUS:
1000 trace_pvscsi_io_write("PVSCSI_REG_OFFSET_INTR_STATUS", val);
1001 s->reg_interrupt_status &= ~val;
1002 pvscsi_update_irq_status(s);
1003 pvscsi_schedule_completion_processing(s);
1004 break;
1005
1006 case PVSCSI_REG_OFFSET_INTR_MASK:
1007 trace_pvscsi_io_write("PVSCSI_REG_OFFSET_INTR_MASK", val);
1008 s->reg_interrupt_enabled = val;
1009 pvscsi_update_irq_status(s);
1010 break;
1011
1012 case PVSCSI_REG_OFFSET_KICK_NON_RW_IO:
1013 trace_pvscsi_io_write("PVSCSI_REG_OFFSET_KICK_NON_RW_IO", val);
1014 pvscsi_process_io(s);
1015 break;
1016
1017 case PVSCSI_REG_OFFSET_KICK_RW_IO:
1018 trace_pvscsi_io_write("PVSCSI_REG_OFFSET_KICK_RW_IO", val);
1019 pvscsi_process_io(s);
1020 break;
1021
1022 case PVSCSI_REG_OFFSET_DEBUG:
1023 trace_pvscsi_io_write("PVSCSI_REG_OFFSET_DEBUG", val);
1024 break;
1025
1026 default:
1027 trace_pvscsi_io_write_unknown(addr, size, val);
1028 break;
1029 }
1030
1031 }
1032
1033 static uint64_t
1034 pvscsi_io_read(void *opaque, hwaddr addr, unsigned size)
1035 {
1036 PVSCSIState *s = opaque;
1037
1038 switch (addr) {
1039 case PVSCSI_REG_OFFSET_INTR_STATUS:
1040 trace_pvscsi_io_read("PVSCSI_REG_OFFSET_INTR_STATUS",
1041 s->reg_interrupt_status);
1042 return s->reg_interrupt_status;
1043
1044 case PVSCSI_REG_OFFSET_INTR_MASK:
1045 trace_pvscsi_io_read("PVSCSI_REG_OFFSET_INTR_MASK",
1046 s->reg_interrupt_status);
1047 return s->reg_interrupt_enabled;
1048
1049 case PVSCSI_REG_OFFSET_COMMAND_STATUS:
1050 trace_pvscsi_io_read("PVSCSI_REG_OFFSET_COMMAND_STATUS",
1051 s->reg_interrupt_status);
1052 return s->reg_command_status;
1053
1054 default:
1055 trace_pvscsi_io_read_unknown(addr, size);
1056 return 0;
1057 }
1058 }
1059
1060
1061 static void
1062 pvscsi_init_msi(PVSCSIState *s)
1063 {
1064 int res;
1065 PCIDevice *d = PCI_DEVICE(s);
1066
1067 res = msi_init(d, PVSCSI_MSI_OFFSET(s), PVSCSI_MSIX_NUM_VECTORS,
1068 PVSCSI_USE_64BIT, PVSCSI_PER_VECTOR_MASK, NULL);
1069 if (res < 0) {
1070 trace_pvscsi_init_msi_fail(res);
1071 s->msi_used = false;
1072 } else {
1073 s->msi_used = true;
1074 }
1075 }
1076
1077 static void
1078 pvscsi_cleanup_msi(PVSCSIState *s)
1079 {
1080 PCIDevice *d = PCI_DEVICE(s);
1081
1082 msi_uninit(d);
1083 }
1084
1085 static const MemoryRegionOps pvscsi_ops = {
1086 .read = pvscsi_io_read,
1087 .write = pvscsi_io_write,
1088 .endianness = DEVICE_LITTLE_ENDIAN,
1089 .impl = {
1090 .min_access_size = 4,
1091 .max_access_size = 4,
1092 },
1093 };
1094
1095 static const struct SCSIBusInfo pvscsi_scsi_info = {
1096 .tcq = true,
1097 .max_target = PVSCSI_MAX_DEVS,
1098 .max_channel = 0,
1099 .max_lun = 0,
1100
1101 .get_sg_list = pvscsi_get_sg_list,
1102 .complete = pvscsi_command_complete,
1103 .cancel = pvscsi_request_cancelled,
1104 };
1105
1106 static int
1107 pvscsi_init(PCIDevice *pci_dev)
1108 {
1109 PVSCSIState *s = PVSCSI(pci_dev);
1110
1111 trace_pvscsi_state("init");
1112
1113 /* PCI subsystem ID, subsystem vendor ID, revision */
1114 if (PVSCSI_USE_OLD_PCI_CONFIGURATION(s)) {
1115 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 0x1000);
1116 } else {
1117 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
1118 PCI_VENDOR_ID_VMWARE);
1119 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
1120 PCI_DEVICE_ID_VMWARE_PVSCSI);
1121 pci_config_set_revision(pci_dev->config, 0x2);
1122 }
1123
1124 /* PCI latency timer = 255 */
1125 pci_dev->config[PCI_LATENCY_TIMER] = 0xff;
1126
1127 /* Interrupt pin A */
1128 pci_config_set_interrupt_pin(pci_dev->config, 1);
1129
1130 memory_region_init_io(&s->io_space, OBJECT(s), &pvscsi_ops, s,
1131 "pvscsi-io", PVSCSI_MEM_SPACE_SIZE);
1132 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->io_space);
1133
1134 pvscsi_init_msi(s);
1135
1136 if (pci_is_express(pci_dev) && pci_bus_is_express(pci_dev->bus)) {
1137 pcie_endpoint_cap_init(pci_dev, PVSCSI_EXP_EP_OFFSET);
1138 }
1139
1140 s->completion_worker = qemu_bh_new(pvscsi_process_completion_queue, s);
1141 if (!s->completion_worker) {
1142 pvscsi_cleanup_msi(s);
1143 return -ENOMEM;
1144 }
1145
1146 scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(pci_dev),
1147 &pvscsi_scsi_info, NULL);
1148 /* override default SCSI bus hotplug-handler, with pvscsi's one */
1149 qbus_set_hotplug_handler(BUS(&s->bus), DEVICE(s), &error_abort);
1150 pvscsi_reset_state(s);
1151
1152 return 0;
1153 }
1154
1155 static void
1156 pvscsi_uninit(PCIDevice *pci_dev)
1157 {
1158 PVSCSIState *s = PVSCSI(pci_dev);
1159
1160 trace_pvscsi_state("uninit");
1161 qemu_bh_delete(s->completion_worker);
1162
1163 pvscsi_cleanup_msi(s);
1164 }
1165
1166 static void
1167 pvscsi_reset(DeviceState *dev)
1168 {
1169 PCIDevice *d = PCI_DEVICE(dev);
1170 PVSCSIState *s = PVSCSI(d);
1171
1172 trace_pvscsi_state("reset");
1173 pvscsi_reset_adapter(s);
1174 }
1175
1176 static void
1177 pvscsi_pre_save(void *opaque)
1178 {
1179 PVSCSIState *s = (PVSCSIState *) opaque;
1180
1181 trace_pvscsi_state("presave");
1182
1183 assert(QTAILQ_EMPTY(&s->pending_queue));
1184 assert(QTAILQ_EMPTY(&s->completion_queue));
1185 }
1186
1187 static int
1188 pvscsi_post_load(void *opaque, int version_id)
1189 {
1190 trace_pvscsi_state("postload");
1191 return 0;
1192 }
1193
1194 static bool pvscsi_vmstate_need_pcie_device(void *opaque)
1195 {
1196 PVSCSIState *s = PVSCSI(opaque);
1197
1198 return !(s->compat_flags & PVSCSI_COMPAT_DISABLE_PCIE);
1199 }
1200
1201 static bool pvscsi_vmstate_test_pci_device(void *opaque, int version_id)
1202 {
1203 return !pvscsi_vmstate_need_pcie_device(opaque);
1204 }
1205
1206 static const VMStateDescription vmstate_pvscsi_pcie_device = {
1207 .name = "pvscsi/pcie",
1208 .needed = pvscsi_vmstate_need_pcie_device,
1209 .fields = (VMStateField[]) {
1210 VMSTATE_PCI_DEVICE(parent_obj, PVSCSIState),
1211 VMSTATE_END_OF_LIST()
1212 }
1213 };
1214
1215 static const VMStateDescription vmstate_pvscsi = {
1216 .name = "pvscsi",
1217 .version_id = 0,
1218 .minimum_version_id = 0,
1219 .pre_save = pvscsi_pre_save,
1220 .post_load = pvscsi_post_load,
1221 .fields = (VMStateField[]) {
1222 VMSTATE_STRUCT_TEST(parent_obj, PVSCSIState,
1223 pvscsi_vmstate_test_pci_device, 0,
1224 vmstate_pci_device, PCIDevice),
1225 VMSTATE_UINT8(msi_used, PVSCSIState),
1226 VMSTATE_UINT32(resetting, PVSCSIState),
1227 VMSTATE_UINT64(reg_interrupt_status, PVSCSIState),
1228 VMSTATE_UINT64(reg_interrupt_enabled, PVSCSIState),
1229 VMSTATE_UINT64(reg_command_status, PVSCSIState),
1230 VMSTATE_UINT64(curr_cmd, PVSCSIState),
1231 VMSTATE_UINT32(curr_cmd_data_cntr, PVSCSIState),
1232 VMSTATE_UINT32_ARRAY(curr_cmd_data, PVSCSIState,
1233 ARRAY_SIZE(((PVSCSIState *)NULL)->curr_cmd_data)),
1234 VMSTATE_UINT8(rings_info_valid, PVSCSIState),
1235 VMSTATE_UINT8(msg_ring_info_valid, PVSCSIState),
1236 VMSTATE_UINT8(use_msg, PVSCSIState),
1237
1238 VMSTATE_UINT64(rings.rs_pa, PVSCSIState),
1239 VMSTATE_UINT32(rings.txr_len_mask, PVSCSIState),
1240 VMSTATE_UINT32(rings.rxr_len_mask, PVSCSIState),
1241 VMSTATE_UINT64_ARRAY(rings.req_ring_pages_pa, PVSCSIState,
1242 PVSCSI_SETUP_RINGS_MAX_NUM_PAGES),
1243 VMSTATE_UINT64_ARRAY(rings.cmp_ring_pages_pa, PVSCSIState,
1244 PVSCSI_SETUP_RINGS_MAX_NUM_PAGES),
1245 VMSTATE_UINT64(rings.consumed_ptr, PVSCSIState),
1246 VMSTATE_UINT64(rings.filled_cmp_ptr, PVSCSIState),
1247
1248 VMSTATE_END_OF_LIST()
1249 },
1250 .subsections = (const VMStateDescription*[]) {
1251 &vmstate_pvscsi_pcie_device,
1252 NULL
1253 }
1254 };
1255
1256 static Property pvscsi_properties[] = {
1257 DEFINE_PROP_UINT8("use_msg", PVSCSIState, use_msg, 1),
1258 DEFINE_PROP_BIT("x-old-pci-configuration", PVSCSIState, compat_flags,
1259 PVSCSI_COMPAT_OLD_PCI_CONFIGURATION_BIT, false),
1260 DEFINE_PROP_BIT("x-disable-pcie", PVSCSIState, compat_flags,
1261 PVSCSI_COMPAT_DISABLE_PCIE_BIT, false),
1262 DEFINE_PROP_END_OF_LIST(),
1263 };
1264
1265 static void pvscsi_realize(DeviceState *qdev, Error **errp)
1266 {
1267 PVSCSIClass *pvs_c = PVSCSI_DEVICE_GET_CLASS(qdev);
1268 PCIDevice *pci_dev = PCI_DEVICE(qdev);
1269 PVSCSIState *s = PVSCSI(qdev);
1270
1271 if (!(s->compat_flags & PVSCSI_COMPAT_DISABLE_PCIE)) {
1272 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1273 }
1274
1275 pvs_c->parent_dc_realize(qdev, errp);
1276 }
1277
1278 static void pvscsi_class_init(ObjectClass *klass, void *data)
1279 {
1280 DeviceClass *dc = DEVICE_CLASS(klass);
1281 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1282 PVSCSIClass *pvs_k = PVSCSI_DEVICE_CLASS(klass);
1283 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
1284
1285 k->init = pvscsi_init;
1286 k->exit = pvscsi_uninit;
1287 k->vendor_id = PCI_VENDOR_ID_VMWARE;
1288 k->device_id = PCI_DEVICE_ID_VMWARE_PVSCSI;
1289 k->class_id = PCI_CLASS_STORAGE_SCSI;
1290 k->subsystem_id = 0x1000;
1291 pvs_k->parent_dc_realize = dc->realize;
1292 dc->realize = pvscsi_realize;
1293 dc->reset = pvscsi_reset;
1294 dc->vmsd = &vmstate_pvscsi;
1295 dc->props = pvscsi_properties;
1296 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
1297 hc->unplug = pvscsi_hot_unplug;
1298 hc->plug = pvscsi_hotplug;
1299 }
1300
1301 static const TypeInfo pvscsi_info = {
1302 .name = TYPE_PVSCSI,
1303 .parent = TYPE_PCI_DEVICE,
1304 .class_size = sizeof(PVSCSIClass),
1305 .instance_size = sizeof(PVSCSIState),
1306 .class_init = pvscsi_class_init,
1307 .interfaces = (InterfaceInfo[]) {
1308 { TYPE_HOTPLUG_HANDLER },
1309 { }
1310 }
1311 };
1312
1313 static void
1314 pvscsi_register_types(void)
1315 {
1316 type_register_static(&pvscsi_info);
1317 }
1318
1319 type_init(pvscsi_register_types);