meson: convert hw/vfio
[qemu.git] / hw / scsi / vmw_pvscsi.c
1 /*
2 * QEMU VMWARE PVSCSI paravirtual SCSI bus
3 *
4 * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com)
5 *
6 * Developed by Daynix Computing LTD (http://www.daynix.com)
7 *
8 * Based on implementation by Paolo Bonzini
9 * http://lists.gnu.org/archive/html/qemu-devel/2011-08/msg00729.html
10 *
11 * Authors:
12 * Paolo Bonzini <pbonzini@redhat.com>
13 * Dmitry Fleytman <dmitry@daynix.com>
14 * Yan Vugenfirer <yan@daynix.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2.
17 * See the COPYING file in the top-level directory.
18 *
19 * NOTE about MSI-X:
20 * MSI-X support has been removed for the moment because it leads Windows OS
21 * to crash on startup. The crash happens because Windows driver requires
22 * MSI-X shared memory to be part of the same BAR used for rings state
23 * registers, etc. This is not supported by QEMU infrastructure so separate
24 * BAR created from MSI-X purposes. Windows driver fails to deal with 2 BARs.
25 *
26 */
27
28 #include "qemu/osdep.h"
29 #include "qapi/error.h"
30 #include "qemu/main-loop.h"
31 #include "qemu/module.h"
32 #include "hw/scsi/scsi.h"
33 #include "migration/vmstate.h"
34 #include "scsi/constants.h"
35 #include "hw/pci/msi.h"
36 #include "hw/qdev-properties.h"
37 #include "vmw_pvscsi.h"
38 #include "trace.h"
39
40
41 #define PVSCSI_USE_64BIT (true)
42 #define PVSCSI_PER_VECTOR_MASK (false)
43
44 #define PVSCSI_MAX_DEVS (64)
45 #define PVSCSI_MSIX_NUM_VECTORS (1)
46
47 #define PVSCSI_MAX_SG_ELEM 2048
48
49 #define PVSCSI_MAX_CMD_DATA_WORDS \
50 (sizeof(PVSCSICmdDescSetupRings)/sizeof(uint32_t))
51
52 #define RS_GET_FIELD(m, field) \
53 (ldl_le_pci_dma(&container_of(m, PVSCSIState, rings)->parent_obj, \
54 (m)->rs_pa + offsetof(struct PVSCSIRingsState, field)))
55 #define RS_SET_FIELD(m, field, val) \
56 (stl_le_pci_dma(&container_of(m, PVSCSIState, rings)->parent_obj, \
57 (m)->rs_pa + offsetof(struct PVSCSIRingsState, field), val))
58
59 typedef struct PVSCSIClass {
60 PCIDeviceClass parent_class;
61 DeviceRealize parent_dc_realize;
62 } PVSCSIClass;
63
64 #define TYPE_PVSCSI "pvscsi"
65 #define PVSCSI(obj) OBJECT_CHECK(PVSCSIState, (obj), TYPE_PVSCSI)
66
67 #define PVSCSI_DEVICE_CLASS(klass) \
68 OBJECT_CLASS_CHECK(PVSCSIClass, (klass), TYPE_PVSCSI)
69 #define PVSCSI_DEVICE_GET_CLASS(obj) \
70 OBJECT_GET_CLASS(PVSCSIClass, (obj), TYPE_PVSCSI)
71
72 /* Compatibility flags for migration */
73 #define PVSCSI_COMPAT_OLD_PCI_CONFIGURATION_BIT 0
74 #define PVSCSI_COMPAT_OLD_PCI_CONFIGURATION \
75 (1 << PVSCSI_COMPAT_OLD_PCI_CONFIGURATION_BIT)
76 #define PVSCSI_COMPAT_DISABLE_PCIE_BIT 1
77 #define PVSCSI_COMPAT_DISABLE_PCIE \
78 (1 << PVSCSI_COMPAT_DISABLE_PCIE_BIT)
79
80 #define PVSCSI_USE_OLD_PCI_CONFIGURATION(s) \
81 ((s)->compat_flags & PVSCSI_COMPAT_OLD_PCI_CONFIGURATION)
82 #define PVSCSI_MSI_OFFSET(s) \
83 (PVSCSI_USE_OLD_PCI_CONFIGURATION(s) ? 0x50 : 0x7c)
84 #define PVSCSI_EXP_EP_OFFSET (0x40)
85
86 typedef struct PVSCSIRingInfo {
87 uint64_t rs_pa;
88 uint32_t txr_len_mask;
89 uint32_t rxr_len_mask;
90 uint32_t msg_len_mask;
91 uint64_t req_ring_pages_pa[PVSCSI_SETUP_RINGS_MAX_NUM_PAGES];
92 uint64_t cmp_ring_pages_pa[PVSCSI_SETUP_RINGS_MAX_NUM_PAGES];
93 uint64_t msg_ring_pages_pa[PVSCSI_SETUP_MSG_RING_MAX_NUM_PAGES];
94 uint64_t consumed_ptr;
95 uint64_t filled_cmp_ptr;
96 uint64_t filled_msg_ptr;
97 } PVSCSIRingInfo;
98
99 typedef struct PVSCSISGState {
100 hwaddr elemAddr;
101 hwaddr dataAddr;
102 uint32_t resid;
103 } PVSCSISGState;
104
105 typedef QTAILQ_HEAD(, PVSCSIRequest) PVSCSIRequestList;
106
107 typedef struct {
108 PCIDevice parent_obj;
109 MemoryRegion io_space;
110 SCSIBus bus;
111 QEMUBH *completion_worker;
112 PVSCSIRequestList pending_queue;
113 PVSCSIRequestList completion_queue;
114
115 uint64_t reg_interrupt_status; /* Interrupt status register value */
116 uint64_t reg_interrupt_enabled; /* Interrupt mask register value */
117 uint64_t reg_command_status; /* Command status register value */
118
119 /* Command data adoption mechanism */
120 uint64_t curr_cmd; /* Last command arrived */
121 uint32_t curr_cmd_data_cntr; /* Amount of data for last command */
122
123 /* Collector for current command data */
124 uint32_t curr_cmd_data[PVSCSI_MAX_CMD_DATA_WORDS];
125
126 uint8_t rings_info_valid; /* Whether data rings initialized */
127 uint8_t msg_ring_info_valid; /* Whether message ring initialized */
128 uint8_t use_msg; /* Whether to use message ring */
129
130 uint8_t msi_used; /* For migration compatibility */
131 PVSCSIRingInfo rings; /* Data transfer rings manager */
132 uint32_t resetting; /* Reset in progress */
133
134 uint32_t compat_flags;
135 } PVSCSIState;
136
137 typedef struct PVSCSIRequest {
138 SCSIRequest *sreq;
139 PVSCSIState *dev;
140 uint8_t sense_key;
141 uint8_t completed;
142 int lun;
143 QEMUSGList sgl;
144 PVSCSISGState sg;
145 struct PVSCSIRingReqDesc req;
146 struct PVSCSIRingCmpDesc cmp;
147 QTAILQ_ENTRY(PVSCSIRequest) next;
148 } PVSCSIRequest;
149
150 /* Integer binary logarithm */
151 static int
152 pvscsi_log2(uint32_t input)
153 {
154 int log = 0;
155 assert(input > 0);
156 while (input >> ++log) {
157 }
158 return log;
159 }
160
161 static void
162 pvscsi_ring_init_data(PVSCSIRingInfo *m, PVSCSICmdDescSetupRings *ri)
163 {
164 int i;
165 uint32_t txr_len_log2, rxr_len_log2;
166 uint32_t req_ring_size, cmp_ring_size;
167 m->rs_pa = ri->ringsStatePPN << VMW_PAGE_SHIFT;
168
169 req_ring_size = ri->reqRingNumPages * PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE;
170 cmp_ring_size = ri->cmpRingNumPages * PVSCSI_MAX_NUM_CMP_ENTRIES_PER_PAGE;
171 txr_len_log2 = pvscsi_log2(req_ring_size - 1);
172 rxr_len_log2 = pvscsi_log2(cmp_ring_size - 1);
173
174 m->txr_len_mask = MASK(txr_len_log2);
175 m->rxr_len_mask = MASK(rxr_len_log2);
176
177 m->consumed_ptr = 0;
178 m->filled_cmp_ptr = 0;
179
180 for (i = 0; i < ri->reqRingNumPages; i++) {
181 m->req_ring_pages_pa[i] = ri->reqRingPPNs[i] << VMW_PAGE_SHIFT;
182 }
183
184 for (i = 0; i < ri->cmpRingNumPages; i++) {
185 m->cmp_ring_pages_pa[i] = ri->cmpRingPPNs[i] << VMW_PAGE_SHIFT;
186 }
187
188 RS_SET_FIELD(m, reqProdIdx, 0);
189 RS_SET_FIELD(m, reqConsIdx, 0);
190 RS_SET_FIELD(m, reqNumEntriesLog2, txr_len_log2);
191
192 RS_SET_FIELD(m, cmpProdIdx, 0);
193 RS_SET_FIELD(m, cmpConsIdx, 0);
194 RS_SET_FIELD(m, cmpNumEntriesLog2, rxr_len_log2);
195
196 trace_pvscsi_ring_init_data(txr_len_log2, rxr_len_log2);
197
198 /* Flush ring state page changes */
199 smp_wmb();
200 }
201
202 static int
203 pvscsi_ring_init_msg(PVSCSIRingInfo *m, PVSCSICmdDescSetupMsgRing *ri)
204 {
205 int i;
206 uint32_t len_log2;
207 uint32_t ring_size;
208
209 if (!ri->numPages || ri->numPages > PVSCSI_SETUP_MSG_RING_MAX_NUM_PAGES) {
210 return -1;
211 }
212 ring_size = ri->numPages * PVSCSI_MAX_NUM_MSG_ENTRIES_PER_PAGE;
213 len_log2 = pvscsi_log2(ring_size - 1);
214
215 m->msg_len_mask = MASK(len_log2);
216
217 m->filled_msg_ptr = 0;
218
219 for (i = 0; i < ri->numPages; i++) {
220 m->msg_ring_pages_pa[i] = ri->ringPPNs[i] << VMW_PAGE_SHIFT;
221 }
222
223 RS_SET_FIELD(m, msgProdIdx, 0);
224 RS_SET_FIELD(m, msgConsIdx, 0);
225 RS_SET_FIELD(m, msgNumEntriesLog2, len_log2);
226
227 trace_pvscsi_ring_init_msg(len_log2);
228
229 /* Flush ring state page changes */
230 smp_wmb();
231
232 return 0;
233 }
234
235 static void
236 pvscsi_ring_cleanup(PVSCSIRingInfo *mgr)
237 {
238 mgr->rs_pa = 0;
239 mgr->txr_len_mask = 0;
240 mgr->rxr_len_mask = 0;
241 mgr->msg_len_mask = 0;
242 mgr->consumed_ptr = 0;
243 mgr->filled_cmp_ptr = 0;
244 mgr->filled_msg_ptr = 0;
245 memset(mgr->req_ring_pages_pa, 0, sizeof(mgr->req_ring_pages_pa));
246 memset(mgr->cmp_ring_pages_pa, 0, sizeof(mgr->cmp_ring_pages_pa));
247 memset(mgr->msg_ring_pages_pa, 0, sizeof(mgr->msg_ring_pages_pa));
248 }
249
250 static hwaddr
251 pvscsi_ring_pop_req_descr(PVSCSIRingInfo *mgr)
252 {
253 uint32_t ready_ptr = RS_GET_FIELD(mgr, reqProdIdx);
254 uint32_t ring_size = PVSCSI_MAX_NUM_PAGES_REQ_RING
255 * PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE;
256
257 if (ready_ptr != mgr->consumed_ptr
258 && ready_ptr - mgr->consumed_ptr < ring_size) {
259 uint32_t next_ready_ptr =
260 mgr->consumed_ptr++ & mgr->txr_len_mask;
261 uint32_t next_ready_page =
262 next_ready_ptr / PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE;
263 uint32_t inpage_idx =
264 next_ready_ptr % PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE;
265
266 return mgr->req_ring_pages_pa[next_ready_page] +
267 inpage_idx * sizeof(PVSCSIRingReqDesc);
268 } else {
269 return 0;
270 }
271 }
272
273 static void
274 pvscsi_ring_flush_req(PVSCSIRingInfo *mgr)
275 {
276 RS_SET_FIELD(mgr, reqConsIdx, mgr->consumed_ptr);
277 }
278
279 static hwaddr
280 pvscsi_ring_pop_cmp_descr(PVSCSIRingInfo *mgr)
281 {
282 /*
283 * According to Linux driver code it explicitly verifies that number
284 * of requests being processed by device is less then the size of
285 * completion queue, so device may omit completion queue overflow
286 * conditions check. We assume that this is true for other (Windows)
287 * drivers as well.
288 */
289
290 uint32_t free_cmp_ptr =
291 mgr->filled_cmp_ptr++ & mgr->rxr_len_mask;
292 uint32_t free_cmp_page =
293 free_cmp_ptr / PVSCSI_MAX_NUM_CMP_ENTRIES_PER_PAGE;
294 uint32_t inpage_idx =
295 free_cmp_ptr % PVSCSI_MAX_NUM_CMP_ENTRIES_PER_PAGE;
296 return mgr->cmp_ring_pages_pa[free_cmp_page] +
297 inpage_idx * sizeof(PVSCSIRingCmpDesc);
298 }
299
300 static hwaddr
301 pvscsi_ring_pop_msg_descr(PVSCSIRingInfo *mgr)
302 {
303 uint32_t free_msg_ptr =
304 mgr->filled_msg_ptr++ & mgr->msg_len_mask;
305 uint32_t free_msg_page =
306 free_msg_ptr / PVSCSI_MAX_NUM_MSG_ENTRIES_PER_PAGE;
307 uint32_t inpage_idx =
308 free_msg_ptr % PVSCSI_MAX_NUM_MSG_ENTRIES_PER_PAGE;
309 return mgr->msg_ring_pages_pa[free_msg_page] +
310 inpage_idx * sizeof(PVSCSIRingMsgDesc);
311 }
312
313 static void
314 pvscsi_ring_flush_cmp(PVSCSIRingInfo *mgr)
315 {
316 /* Flush descriptor changes */
317 smp_wmb();
318
319 trace_pvscsi_ring_flush_cmp(mgr->filled_cmp_ptr);
320
321 RS_SET_FIELD(mgr, cmpProdIdx, mgr->filled_cmp_ptr);
322 }
323
324 static bool
325 pvscsi_ring_msg_has_room(PVSCSIRingInfo *mgr)
326 {
327 uint32_t prodIdx = RS_GET_FIELD(mgr, msgProdIdx);
328 uint32_t consIdx = RS_GET_FIELD(mgr, msgConsIdx);
329
330 return (prodIdx - consIdx) < (mgr->msg_len_mask + 1);
331 }
332
333 static void
334 pvscsi_ring_flush_msg(PVSCSIRingInfo *mgr)
335 {
336 /* Flush descriptor changes */
337 smp_wmb();
338
339 trace_pvscsi_ring_flush_msg(mgr->filled_msg_ptr);
340
341 RS_SET_FIELD(mgr, msgProdIdx, mgr->filled_msg_ptr);
342 }
343
344 static void
345 pvscsi_reset_state(PVSCSIState *s)
346 {
347 s->curr_cmd = PVSCSI_CMD_FIRST;
348 s->curr_cmd_data_cntr = 0;
349 s->reg_command_status = PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
350 s->reg_interrupt_status = 0;
351 pvscsi_ring_cleanup(&s->rings);
352 s->rings_info_valid = FALSE;
353 s->msg_ring_info_valid = FALSE;
354 QTAILQ_INIT(&s->pending_queue);
355 QTAILQ_INIT(&s->completion_queue);
356 }
357
358 static void
359 pvscsi_update_irq_status(PVSCSIState *s)
360 {
361 PCIDevice *d = PCI_DEVICE(s);
362 bool should_raise = s->reg_interrupt_enabled & s->reg_interrupt_status;
363
364 trace_pvscsi_update_irq_level(should_raise, s->reg_interrupt_enabled,
365 s->reg_interrupt_status);
366
367 if (msi_enabled(d)) {
368 if (should_raise) {
369 trace_pvscsi_update_irq_msi();
370 msi_notify(d, PVSCSI_VECTOR_COMPLETION);
371 }
372 return;
373 }
374
375 pci_set_irq(d, !!should_raise);
376 }
377
378 static void
379 pvscsi_raise_completion_interrupt(PVSCSIState *s)
380 {
381 s->reg_interrupt_status |= PVSCSI_INTR_CMPL_0;
382
383 /* Memory barrier to flush interrupt status register changes*/
384 smp_wmb();
385
386 pvscsi_update_irq_status(s);
387 }
388
389 static void
390 pvscsi_raise_message_interrupt(PVSCSIState *s)
391 {
392 s->reg_interrupt_status |= PVSCSI_INTR_MSG_0;
393
394 /* Memory barrier to flush interrupt status register changes*/
395 smp_wmb();
396
397 pvscsi_update_irq_status(s);
398 }
399
400 static void
401 pvscsi_cmp_ring_put(PVSCSIState *s, struct PVSCSIRingCmpDesc *cmp_desc)
402 {
403 hwaddr cmp_descr_pa;
404
405 cmp_descr_pa = pvscsi_ring_pop_cmp_descr(&s->rings);
406 trace_pvscsi_cmp_ring_put(cmp_descr_pa);
407 cpu_physical_memory_write(cmp_descr_pa, cmp_desc, sizeof(*cmp_desc));
408 }
409
410 static void
411 pvscsi_msg_ring_put(PVSCSIState *s, struct PVSCSIRingMsgDesc *msg_desc)
412 {
413 hwaddr msg_descr_pa;
414
415 msg_descr_pa = pvscsi_ring_pop_msg_descr(&s->rings);
416 trace_pvscsi_msg_ring_put(msg_descr_pa);
417 cpu_physical_memory_write(msg_descr_pa, msg_desc, sizeof(*msg_desc));
418 }
419
420 static void
421 pvscsi_process_completion_queue(void *opaque)
422 {
423 PVSCSIState *s = opaque;
424 PVSCSIRequest *pvscsi_req;
425 bool has_completed = false;
426
427 while (!QTAILQ_EMPTY(&s->completion_queue)) {
428 pvscsi_req = QTAILQ_FIRST(&s->completion_queue);
429 QTAILQ_REMOVE(&s->completion_queue, pvscsi_req, next);
430 pvscsi_cmp_ring_put(s, &pvscsi_req->cmp);
431 g_free(pvscsi_req);
432 has_completed = true;
433 }
434
435 if (has_completed) {
436 pvscsi_ring_flush_cmp(&s->rings);
437 pvscsi_raise_completion_interrupt(s);
438 }
439 }
440
441 static void
442 pvscsi_reset_adapter(PVSCSIState *s)
443 {
444 s->resetting++;
445 qbus_reset_all(BUS(&s->bus));
446 s->resetting--;
447 pvscsi_process_completion_queue(s);
448 assert(QTAILQ_EMPTY(&s->pending_queue));
449 pvscsi_reset_state(s);
450 }
451
452 static void
453 pvscsi_schedule_completion_processing(PVSCSIState *s)
454 {
455 /* Try putting more complete requests on the ring. */
456 if (!QTAILQ_EMPTY(&s->completion_queue)) {
457 qemu_bh_schedule(s->completion_worker);
458 }
459 }
460
461 static void
462 pvscsi_complete_request(PVSCSIState *s, PVSCSIRequest *r)
463 {
464 assert(!r->completed);
465
466 trace_pvscsi_complete_request(r->cmp.context, r->cmp.dataLen,
467 r->sense_key);
468 if (r->sreq != NULL) {
469 scsi_req_unref(r->sreq);
470 r->sreq = NULL;
471 }
472 r->completed = 1;
473 QTAILQ_REMOVE(&s->pending_queue, r, next);
474 QTAILQ_INSERT_TAIL(&s->completion_queue, r, next);
475 pvscsi_schedule_completion_processing(s);
476 }
477
478 static QEMUSGList *pvscsi_get_sg_list(SCSIRequest *r)
479 {
480 PVSCSIRequest *req = r->hba_private;
481
482 trace_pvscsi_get_sg_list(req->sgl.nsg, req->sgl.size);
483
484 return &req->sgl;
485 }
486
487 static void
488 pvscsi_get_next_sg_elem(PVSCSISGState *sg)
489 {
490 struct PVSCSISGElement elem;
491
492 cpu_physical_memory_read(sg->elemAddr, &elem, sizeof(elem));
493 if ((elem.flags & ~PVSCSI_KNOWN_FLAGS) != 0) {
494 /*
495 * There is PVSCSI_SGE_FLAG_CHAIN_ELEMENT flag described in
496 * header file but its value is unknown. This flag requires
497 * additional processing, so we put warning here to catch it
498 * some day and make proper implementation
499 */
500 trace_pvscsi_get_next_sg_elem(elem.flags);
501 }
502
503 sg->elemAddr += sizeof(elem);
504 sg->dataAddr = elem.addr;
505 sg->resid = elem.length;
506 }
507
508 static void
509 pvscsi_write_sense(PVSCSIRequest *r, uint8_t *sense, int len)
510 {
511 r->cmp.senseLen = MIN(r->req.senseLen, len);
512 r->sense_key = sense[(sense[0] & 2) ? 1 : 2];
513 cpu_physical_memory_write(r->req.senseAddr, sense, r->cmp.senseLen);
514 }
515
516 static void
517 pvscsi_command_complete(SCSIRequest *req, uint32_t status, size_t resid)
518 {
519 PVSCSIRequest *pvscsi_req = req->hba_private;
520 PVSCSIState *s;
521
522 if (!pvscsi_req) {
523 trace_pvscsi_command_complete_not_found(req->tag);
524 return;
525 }
526 s = pvscsi_req->dev;
527
528 if (resid) {
529 /* Short transfer. */
530 trace_pvscsi_command_complete_data_run();
531 pvscsi_req->cmp.hostStatus = BTSTAT_DATARUN;
532 }
533
534 pvscsi_req->cmp.scsiStatus = status;
535 if (pvscsi_req->cmp.scsiStatus == CHECK_CONDITION) {
536 uint8_t sense[SCSI_SENSE_BUF_SIZE];
537 int sense_len =
538 scsi_req_get_sense(pvscsi_req->sreq, sense, sizeof(sense));
539
540 trace_pvscsi_command_complete_sense_len(sense_len);
541 pvscsi_write_sense(pvscsi_req, sense, sense_len);
542 }
543 qemu_sglist_destroy(&pvscsi_req->sgl);
544 pvscsi_complete_request(s, pvscsi_req);
545 }
546
547 static void
548 pvscsi_send_msg(PVSCSIState *s, SCSIDevice *dev, uint32_t msg_type)
549 {
550 if (s->msg_ring_info_valid && pvscsi_ring_msg_has_room(&s->rings)) {
551 PVSCSIMsgDescDevStatusChanged msg = {0};
552
553 msg.type = msg_type;
554 msg.bus = dev->channel;
555 msg.target = dev->id;
556 msg.lun[1] = dev->lun;
557
558 pvscsi_msg_ring_put(s, (PVSCSIRingMsgDesc *)&msg);
559 pvscsi_ring_flush_msg(&s->rings);
560 pvscsi_raise_message_interrupt(s);
561 }
562 }
563
564 static void
565 pvscsi_hotplug(HotplugHandler *hotplug_dev, DeviceState *dev, Error **errp)
566 {
567 PVSCSIState *s = PVSCSI(hotplug_dev);
568
569 pvscsi_send_msg(s, SCSI_DEVICE(dev), PVSCSI_MSG_DEV_ADDED);
570 }
571
572 static void
573 pvscsi_hot_unplug(HotplugHandler *hotplug_dev, DeviceState *dev, Error **errp)
574 {
575 PVSCSIState *s = PVSCSI(hotplug_dev);
576
577 pvscsi_send_msg(s, SCSI_DEVICE(dev), PVSCSI_MSG_DEV_REMOVED);
578 qdev_simple_device_unplug_cb(hotplug_dev, dev, errp);
579 }
580
581 static void
582 pvscsi_request_cancelled(SCSIRequest *req)
583 {
584 PVSCSIRequest *pvscsi_req = req->hba_private;
585 PVSCSIState *s = pvscsi_req->dev;
586
587 if (pvscsi_req->completed) {
588 return;
589 }
590
591 if (pvscsi_req->dev->resetting) {
592 pvscsi_req->cmp.hostStatus = BTSTAT_BUSRESET;
593 } else {
594 pvscsi_req->cmp.hostStatus = BTSTAT_ABORTQUEUE;
595 }
596
597 pvscsi_complete_request(s, pvscsi_req);
598 }
599
600 static SCSIDevice*
601 pvscsi_device_find(PVSCSIState *s, int channel, int target,
602 uint8_t *requested_lun, uint8_t *target_lun)
603 {
604 if (requested_lun[0] || requested_lun[2] || requested_lun[3] ||
605 requested_lun[4] || requested_lun[5] || requested_lun[6] ||
606 requested_lun[7] || (target > PVSCSI_MAX_DEVS)) {
607 return NULL;
608 } else {
609 *target_lun = requested_lun[1];
610 return scsi_device_find(&s->bus, channel, target, *target_lun);
611 }
612 }
613
614 static PVSCSIRequest *
615 pvscsi_queue_pending_descriptor(PVSCSIState *s, SCSIDevice **d,
616 struct PVSCSIRingReqDesc *descr)
617 {
618 PVSCSIRequest *pvscsi_req;
619 uint8_t lun;
620
621 pvscsi_req = g_malloc0(sizeof(*pvscsi_req));
622 pvscsi_req->dev = s;
623 pvscsi_req->req = *descr;
624 pvscsi_req->cmp.context = pvscsi_req->req.context;
625 QTAILQ_INSERT_TAIL(&s->pending_queue, pvscsi_req, next);
626
627 *d = pvscsi_device_find(s, descr->bus, descr->target, descr->lun, &lun);
628 if (*d) {
629 pvscsi_req->lun = lun;
630 }
631
632 return pvscsi_req;
633 }
634
635 static void
636 pvscsi_convert_sglist(PVSCSIRequest *r)
637 {
638 uint32_t chunk_size, elmcnt = 0;
639 uint64_t data_length = r->req.dataLen;
640 PVSCSISGState sg = r->sg;
641 while (data_length && elmcnt < PVSCSI_MAX_SG_ELEM) {
642 while (!sg.resid && elmcnt++ < PVSCSI_MAX_SG_ELEM) {
643 pvscsi_get_next_sg_elem(&sg);
644 trace_pvscsi_convert_sglist(r->req.context, r->sg.dataAddr,
645 r->sg.resid);
646 }
647 chunk_size = MIN(data_length, sg.resid);
648 if (chunk_size) {
649 qemu_sglist_add(&r->sgl, sg.dataAddr, chunk_size);
650 }
651
652 sg.dataAddr += chunk_size;
653 data_length -= chunk_size;
654 sg.resid -= chunk_size;
655 }
656 }
657
658 static void
659 pvscsi_build_sglist(PVSCSIState *s, PVSCSIRequest *r)
660 {
661 PCIDevice *d = PCI_DEVICE(s);
662
663 pci_dma_sglist_init(&r->sgl, d, 1);
664 if (r->req.flags & PVSCSI_FLAG_CMD_WITH_SG_LIST) {
665 pvscsi_convert_sglist(r);
666 } else {
667 qemu_sglist_add(&r->sgl, r->req.dataAddr, r->req.dataLen);
668 }
669 }
670
671 static void
672 pvscsi_process_request_descriptor(PVSCSIState *s,
673 struct PVSCSIRingReqDesc *descr)
674 {
675 SCSIDevice *d;
676 PVSCSIRequest *r = pvscsi_queue_pending_descriptor(s, &d, descr);
677 int64_t n;
678
679 trace_pvscsi_process_req_descr(descr->cdb[0], descr->context);
680
681 if (!d) {
682 r->cmp.hostStatus = BTSTAT_SELTIMEO;
683 trace_pvscsi_process_req_descr_unknown_device();
684 pvscsi_complete_request(s, r);
685 return;
686 }
687
688 if (descr->flags & PVSCSI_FLAG_CMD_WITH_SG_LIST) {
689 r->sg.elemAddr = descr->dataAddr;
690 }
691
692 r->sreq = scsi_req_new(d, descr->context, r->lun, descr->cdb, r);
693 if (r->sreq->cmd.mode == SCSI_XFER_FROM_DEV &&
694 (descr->flags & PVSCSI_FLAG_CMD_DIR_TODEVICE)) {
695 r->cmp.hostStatus = BTSTAT_BADMSG;
696 trace_pvscsi_process_req_descr_invalid_dir();
697 scsi_req_cancel(r->sreq);
698 return;
699 }
700 if (r->sreq->cmd.mode == SCSI_XFER_TO_DEV &&
701 (descr->flags & PVSCSI_FLAG_CMD_DIR_TOHOST)) {
702 r->cmp.hostStatus = BTSTAT_BADMSG;
703 trace_pvscsi_process_req_descr_invalid_dir();
704 scsi_req_cancel(r->sreq);
705 return;
706 }
707
708 pvscsi_build_sglist(s, r);
709 n = scsi_req_enqueue(r->sreq);
710
711 if (n) {
712 scsi_req_continue(r->sreq);
713 }
714 }
715
716 static void
717 pvscsi_process_io(PVSCSIState *s)
718 {
719 PVSCSIRingReqDesc descr;
720 hwaddr next_descr_pa;
721
722 if (!s->rings_info_valid) {
723 return;
724 }
725
726 while ((next_descr_pa = pvscsi_ring_pop_req_descr(&s->rings)) != 0) {
727
728 /* Only read after production index verification */
729 smp_rmb();
730
731 trace_pvscsi_process_io(next_descr_pa);
732 cpu_physical_memory_read(next_descr_pa, &descr, sizeof(descr));
733 pvscsi_process_request_descriptor(s, &descr);
734 }
735
736 pvscsi_ring_flush_req(&s->rings);
737 }
738
739 static void
740 pvscsi_dbg_dump_tx_rings_config(PVSCSICmdDescSetupRings *rc)
741 {
742 int i;
743 trace_pvscsi_tx_rings_ppn("Rings State", rc->ringsStatePPN);
744
745 trace_pvscsi_tx_rings_num_pages("Request Ring", rc->reqRingNumPages);
746 for (i = 0; i < rc->reqRingNumPages; i++) {
747 trace_pvscsi_tx_rings_ppn("Request Ring", rc->reqRingPPNs[i]);
748 }
749
750 trace_pvscsi_tx_rings_num_pages("Confirm Ring", rc->cmpRingNumPages);
751 for (i = 0; i < rc->cmpRingNumPages; i++) {
752 trace_pvscsi_tx_rings_ppn("Confirm Ring", rc->cmpRingPPNs[i]);
753 }
754 }
755
756 static uint64_t
757 pvscsi_on_cmd_config(PVSCSIState *s)
758 {
759 trace_pvscsi_on_cmd_noimpl("PVSCSI_CMD_CONFIG");
760 return PVSCSI_COMMAND_PROCESSING_FAILED;
761 }
762
763 static uint64_t
764 pvscsi_on_cmd_unplug(PVSCSIState *s)
765 {
766 trace_pvscsi_on_cmd_noimpl("PVSCSI_CMD_DEVICE_UNPLUG");
767 return PVSCSI_COMMAND_PROCESSING_FAILED;
768 }
769
770 static uint64_t
771 pvscsi_on_issue_scsi(PVSCSIState *s)
772 {
773 trace_pvscsi_on_cmd_noimpl("PVSCSI_CMD_ISSUE_SCSI");
774 return PVSCSI_COMMAND_PROCESSING_FAILED;
775 }
776
777 static uint64_t
778 pvscsi_on_cmd_setup_rings(PVSCSIState *s)
779 {
780 PVSCSICmdDescSetupRings *rc =
781 (PVSCSICmdDescSetupRings *) s->curr_cmd_data;
782
783 trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_SETUP_RINGS");
784
785 if (!rc->reqRingNumPages
786 || rc->reqRingNumPages > PVSCSI_SETUP_RINGS_MAX_NUM_PAGES
787 || !rc->cmpRingNumPages
788 || rc->cmpRingNumPages > PVSCSI_SETUP_RINGS_MAX_NUM_PAGES) {
789 return PVSCSI_COMMAND_PROCESSING_FAILED;
790 }
791
792 pvscsi_dbg_dump_tx_rings_config(rc);
793 pvscsi_ring_init_data(&s->rings, rc);
794
795 s->rings_info_valid = TRUE;
796 return PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
797 }
798
799 static uint64_t
800 pvscsi_on_cmd_abort(PVSCSIState *s)
801 {
802 PVSCSICmdDescAbortCmd *cmd = (PVSCSICmdDescAbortCmd *) s->curr_cmd_data;
803 PVSCSIRequest *r, *next;
804
805 trace_pvscsi_on_cmd_abort(cmd->context, cmd->target);
806
807 QTAILQ_FOREACH_SAFE(r, &s->pending_queue, next, next) {
808 if (r->req.context == cmd->context) {
809 break;
810 }
811 }
812 if (r) {
813 assert(!r->completed);
814 r->cmp.hostStatus = BTSTAT_ABORTQUEUE;
815 scsi_req_cancel(r->sreq);
816 }
817
818 return PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
819 }
820
821 static uint64_t
822 pvscsi_on_cmd_unknown(PVSCSIState *s)
823 {
824 trace_pvscsi_on_cmd_unknown_data(s->curr_cmd_data[0]);
825 return PVSCSI_COMMAND_PROCESSING_FAILED;
826 }
827
828 static uint64_t
829 pvscsi_on_cmd_reset_device(PVSCSIState *s)
830 {
831 uint8_t target_lun = 0;
832 struct PVSCSICmdDescResetDevice *cmd =
833 (struct PVSCSICmdDescResetDevice *) s->curr_cmd_data;
834 SCSIDevice *sdev;
835
836 sdev = pvscsi_device_find(s, 0, cmd->target, cmd->lun, &target_lun);
837
838 trace_pvscsi_on_cmd_reset_dev(cmd->target, (int) target_lun, sdev);
839
840 if (sdev != NULL) {
841 s->resetting++;
842 device_legacy_reset(&sdev->qdev);
843 s->resetting--;
844 return PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
845 }
846
847 return PVSCSI_COMMAND_PROCESSING_FAILED;
848 }
849
850 static uint64_t
851 pvscsi_on_cmd_reset_bus(PVSCSIState *s)
852 {
853 trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_RESET_BUS");
854
855 s->resetting++;
856 qbus_reset_all(BUS(&s->bus));
857 s->resetting--;
858 return PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
859 }
860
861 static uint64_t
862 pvscsi_on_cmd_setup_msg_ring(PVSCSIState *s)
863 {
864 PVSCSICmdDescSetupMsgRing *rc =
865 (PVSCSICmdDescSetupMsgRing *) s->curr_cmd_data;
866
867 trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_SETUP_MSG_RING");
868
869 if (!s->use_msg) {
870 return PVSCSI_COMMAND_PROCESSING_FAILED;
871 }
872
873 if (s->rings_info_valid) {
874 if (pvscsi_ring_init_msg(&s->rings, rc) < 0) {
875 return PVSCSI_COMMAND_PROCESSING_FAILED;
876 }
877 s->msg_ring_info_valid = TRUE;
878 }
879 return sizeof(PVSCSICmdDescSetupMsgRing) / sizeof(uint32_t);
880 }
881
882 static uint64_t
883 pvscsi_on_cmd_adapter_reset(PVSCSIState *s)
884 {
885 trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_ADAPTER_RESET");
886
887 pvscsi_reset_adapter(s);
888 return PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
889 }
890
891 static const struct {
892 int data_size;
893 uint64_t (*handler_fn)(PVSCSIState *s);
894 } pvscsi_commands[] = {
895 [PVSCSI_CMD_FIRST] = {
896 .data_size = 0,
897 .handler_fn = pvscsi_on_cmd_unknown,
898 },
899
900 /* Not implemented, data size defined based on what arrives on windows */
901 [PVSCSI_CMD_CONFIG] = {
902 .data_size = 6 * sizeof(uint32_t),
903 .handler_fn = pvscsi_on_cmd_config,
904 },
905
906 /* Command not implemented, data size is unknown */
907 [PVSCSI_CMD_ISSUE_SCSI] = {
908 .data_size = 0,
909 .handler_fn = pvscsi_on_issue_scsi,
910 },
911
912 /* Command not implemented, data size is unknown */
913 [PVSCSI_CMD_DEVICE_UNPLUG] = {
914 .data_size = 0,
915 .handler_fn = pvscsi_on_cmd_unplug,
916 },
917
918 [PVSCSI_CMD_SETUP_RINGS] = {
919 .data_size = sizeof(PVSCSICmdDescSetupRings),
920 .handler_fn = pvscsi_on_cmd_setup_rings,
921 },
922
923 [PVSCSI_CMD_RESET_DEVICE] = {
924 .data_size = sizeof(struct PVSCSICmdDescResetDevice),
925 .handler_fn = pvscsi_on_cmd_reset_device,
926 },
927
928 [PVSCSI_CMD_RESET_BUS] = {
929 .data_size = 0,
930 .handler_fn = pvscsi_on_cmd_reset_bus,
931 },
932
933 [PVSCSI_CMD_SETUP_MSG_RING] = {
934 .data_size = sizeof(PVSCSICmdDescSetupMsgRing),
935 .handler_fn = pvscsi_on_cmd_setup_msg_ring,
936 },
937
938 [PVSCSI_CMD_ADAPTER_RESET] = {
939 .data_size = 0,
940 .handler_fn = pvscsi_on_cmd_adapter_reset,
941 },
942
943 [PVSCSI_CMD_ABORT_CMD] = {
944 .data_size = sizeof(struct PVSCSICmdDescAbortCmd),
945 .handler_fn = pvscsi_on_cmd_abort,
946 },
947 };
948
949 static void
950 pvscsi_do_command_processing(PVSCSIState *s)
951 {
952 size_t bytes_arrived = s->curr_cmd_data_cntr * sizeof(uint32_t);
953
954 assert(s->curr_cmd < PVSCSI_CMD_LAST);
955 if (bytes_arrived >= pvscsi_commands[s->curr_cmd].data_size) {
956 s->reg_command_status = pvscsi_commands[s->curr_cmd].handler_fn(s);
957 s->curr_cmd = PVSCSI_CMD_FIRST;
958 s->curr_cmd_data_cntr = 0;
959 }
960 }
961
962 static void
963 pvscsi_on_command_data(PVSCSIState *s, uint32_t value)
964 {
965 size_t bytes_arrived = s->curr_cmd_data_cntr * sizeof(uint32_t);
966
967 assert(bytes_arrived < sizeof(s->curr_cmd_data));
968 s->curr_cmd_data[s->curr_cmd_data_cntr++] = value;
969
970 pvscsi_do_command_processing(s);
971 }
972
973 static void
974 pvscsi_on_command(PVSCSIState *s, uint64_t cmd_id)
975 {
976 if ((cmd_id > PVSCSI_CMD_FIRST) && (cmd_id < PVSCSI_CMD_LAST)) {
977 s->curr_cmd = cmd_id;
978 } else {
979 s->curr_cmd = PVSCSI_CMD_FIRST;
980 trace_pvscsi_on_cmd_unknown(cmd_id);
981 }
982
983 s->curr_cmd_data_cntr = 0;
984 s->reg_command_status = PVSCSI_COMMAND_NOT_ENOUGH_DATA;
985
986 pvscsi_do_command_processing(s);
987 }
988
989 static void
990 pvscsi_io_write(void *opaque, hwaddr addr,
991 uint64_t val, unsigned size)
992 {
993 PVSCSIState *s = opaque;
994
995 switch (addr) {
996 case PVSCSI_REG_OFFSET_COMMAND:
997 pvscsi_on_command(s, val);
998 break;
999
1000 case PVSCSI_REG_OFFSET_COMMAND_DATA:
1001 pvscsi_on_command_data(s, (uint32_t) val);
1002 break;
1003
1004 case PVSCSI_REG_OFFSET_INTR_STATUS:
1005 trace_pvscsi_io_write("PVSCSI_REG_OFFSET_INTR_STATUS", val);
1006 s->reg_interrupt_status &= ~val;
1007 pvscsi_update_irq_status(s);
1008 pvscsi_schedule_completion_processing(s);
1009 break;
1010
1011 case PVSCSI_REG_OFFSET_INTR_MASK:
1012 trace_pvscsi_io_write("PVSCSI_REG_OFFSET_INTR_MASK", val);
1013 s->reg_interrupt_enabled = val;
1014 pvscsi_update_irq_status(s);
1015 break;
1016
1017 case PVSCSI_REG_OFFSET_KICK_NON_RW_IO:
1018 trace_pvscsi_io_write("PVSCSI_REG_OFFSET_KICK_NON_RW_IO", val);
1019 pvscsi_process_io(s);
1020 break;
1021
1022 case PVSCSI_REG_OFFSET_KICK_RW_IO:
1023 trace_pvscsi_io_write("PVSCSI_REG_OFFSET_KICK_RW_IO", val);
1024 pvscsi_process_io(s);
1025 break;
1026
1027 case PVSCSI_REG_OFFSET_DEBUG:
1028 trace_pvscsi_io_write("PVSCSI_REG_OFFSET_DEBUG", val);
1029 break;
1030
1031 default:
1032 trace_pvscsi_io_write_unknown(addr, size, val);
1033 break;
1034 }
1035
1036 }
1037
1038 static uint64_t
1039 pvscsi_io_read(void *opaque, hwaddr addr, unsigned size)
1040 {
1041 PVSCSIState *s = opaque;
1042
1043 switch (addr) {
1044 case PVSCSI_REG_OFFSET_INTR_STATUS:
1045 trace_pvscsi_io_read("PVSCSI_REG_OFFSET_INTR_STATUS",
1046 s->reg_interrupt_status);
1047 return s->reg_interrupt_status;
1048
1049 case PVSCSI_REG_OFFSET_INTR_MASK:
1050 trace_pvscsi_io_read("PVSCSI_REG_OFFSET_INTR_MASK",
1051 s->reg_interrupt_status);
1052 return s->reg_interrupt_enabled;
1053
1054 case PVSCSI_REG_OFFSET_COMMAND_STATUS:
1055 trace_pvscsi_io_read("PVSCSI_REG_OFFSET_COMMAND_STATUS",
1056 s->reg_interrupt_status);
1057 return s->reg_command_status;
1058
1059 default:
1060 trace_pvscsi_io_read_unknown(addr, size);
1061 return 0;
1062 }
1063 }
1064
1065
1066 static void
1067 pvscsi_init_msi(PVSCSIState *s)
1068 {
1069 int res;
1070 PCIDevice *d = PCI_DEVICE(s);
1071
1072 res = msi_init(d, PVSCSI_MSI_OFFSET(s), PVSCSI_MSIX_NUM_VECTORS,
1073 PVSCSI_USE_64BIT, PVSCSI_PER_VECTOR_MASK, NULL);
1074 if (res < 0) {
1075 trace_pvscsi_init_msi_fail(res);
1076 s->msi_used = false;
1077 } else {
1078 s->msi_used = true;
1079 }
1080 }
1081
1082 static void
1083 pvscsi_cleanup_msi(PVSCSIState *s)
1084 {
1085 PCIDevice *d = PCI_DEVICE(s);
1086
1087 msi_uninit(d);
1088 }
1089
1090 static const MemoryRegionOps pvscsi_ops = {
1091 .read = pvscsi_io_read,
1092 .write = pvscsi_io_write,
1093 .endianness = DEVICE_LITTLE_ENDIAN,
1094 .impl = {
1095 .min_access_size = 4,
1096 .max_access_size = 4,
1097 },
1098 };
1099
1100 static const struct SCSIBusInfo pvscsi_scsi_info = {
1101 .tcq = true,
1102 .max_target = PVSCSI_MAX_DEVS,
1103 .max_channel = 0,
1104 .max_lun = 0,
1105
1106 .get_sg_list = pvscsi_get_sg_list,
1107 .complete = pvscsi_command_complete,
1108 .cancel = pvscsi_request_cancelled,
1109 };
1110
1111 static void
1112 pvscsi_realizefn(PCIDevice *pci_dev, Error **errp)
1113 {
1114 PVSCSIState *s = PVSCSI(pci_dev);
1115
1116 trace_pvscsi_state("init");
1117
1118 /* PCI subsystem ID, subsystem vendor ID, revision */
1119 if (PVSCSI_USE_OLD_PCI_CONFIGURATION(s)) {
1120 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 0x1000);
1121 } else {
1122 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
1123 PCI_VENDOR_ID_VMWARE);
1124 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
1125 PCI_DEVICE_ID_VMWARE_PVSCSI);
1126 pci_config_set_revision(pci_dev->config, 0x2);
1127 }
1128
1129 /* PCI latency timer = 255 */
1130 pci_dev->config[PCI_LATENCY_TIMER] = 0xff;
1131
1132 /* Interrupt pin A */
1133 pci_config_set_interrupt_pin(pci_dev->config, 1);
1134
1135 memory_region_init_io(&s->io_space, OBJECT(s), &pvscsi_ops, s,
1136 "pvscsi-io", PVSCSI_MEM_SPACE_SIZE);
1137 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->io_space);
1138
1139 pvscsi_init_msi(s);
1140
1141 if (pci_is_express(pci_dev) && pci_bus_is_express(pci_get_bus(pci_dev))) {
1142 pcie_endpoint_cap_init(pci_dev, PVSCSI_EXP_EP_OFFSET);
1143 }
1144
1145 s->completion_worker = qemu_bh_new(pvscsi_process_completion_queue, s);
1146
1147 scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(pci_dev),
1148 &pvscsi_scsi_info, NULL);
1149 /* override default SCSI bus hotplug-handler, with pvscsi's one */
1150 qbus_set_hotplug_handler(BUS(&s->bus), OBJECT(s));
1151 pvscsi_reset_state(s);
1152 }
1153
1154 static void
1155 pvscsi_uninit(PCIDevice *pci_dev)
1156 {
1157 PVSCSIState *s = PVSCSI(pci_dev);
1158
1159 trace_pvscsi_state("uninit");
1160 qemu_bh_delete(s->completion_worker);
1161
1162 pvscsi_cleanup_msi(s);
1163 }
1164
1165 static void
1166 pvscsi_reset(DeviceState *dev)
1167 {
1168 PCIDevice *d = PCI_DEVICE(dev);
1169 PVSCSIState *s = PVSCSI(d);
1170
1171 trace_pvscsi_state("reset");
1172 pvscsi_reset_adapter(s);
1173 }
1174
1175 static int
1176 pvscsi_pre_save(void *opaque)
1177 {
1178 PVSCSIState *s = (PVSCSIState *) opaque;
1179
1180 trace_pvscsi_state("presave");
1181
1182 assert(QTAILQ_EMPTY(&s->pending_queue));
1183 assert(QTAILQ_EMPTY(&s->completion_queue));
1184
1185 return 0;
1186 }
1187
1188 static int
1189 pvscsi_post_load(void *opaque, int version_id)
1190 {
1191 trace_pvscsi_state("postload");
1192 return 0;
1193 }
1194
1195 static bool pvscsi_vmstate_need_pcie_device(void *opaque)
1196 {
1197 PVSCSIState *s = PVSCSI(opaque);
1198
1199 return !(s->compat_flags & PVSCSI_COMPAT_DISABLE_PCIE);
1200 }
1201
1202 static bool pvscsi_vmstate_test_pci_device(void *opaque, int version_id)
1203 {
1204 return !pvscsi_vmstate_need_pcie_device(opaque);
1205 }
1206
1207 static const VMStateDescription vmstate_pvscsi_pcie_device = {
1208 .name = "pvscsi/pcie",
1209 .needed = pvscsi_vmstate_need_pcie_device,
1210 .fields = (VMStateField[]) {
1211 VMSTATE_PCI_DEVICE(parent_obj, PVSCSIState),
1212 VMSTATE_END_OF_LIST()
1213 }
1214 };
1215
1216 static const VMStateDescription vmstate_pvscsi = {
1217 .name = "pvscsi",
1218 .version_id = 0,
1219 .minimum_version_id = 0,
1220 .pre_save = pvscsi_pre_save,
1221 .post_load = pvscsi_post_load,
1222 .fields = (VMStateField[]) {
1223 VMSTATE_STRUCT_TEST(parent_obj, PVSCSIState,
1224 pvscsi_vmstate_test_pci_device, 0,
1225 vmstate_pci_device, PCIDevice),
1226 VMSTATE_UINT8(msi_used, PVSCSIState),
1227 VMSTATE_UINT32(resetting, PVSCSIState),
1228 VMSTATE_UINT64(reg_interrupt_status, PVSCSIState),
1229 VMSTATE_UINT64(reg_interrupt_enabled, PVSCSIState),
1230 VMSTATE_UINT64(reg_command_status, PVSCSIState),
1231 VMSTATE_UINT64(curr_cmd, PVSCSIState),
1232 VMSTATE_UINT32(curr_cmd_data_cntr, PVSCSIState),
1233 VMSTATE_UINT32_ARRAY(curr_cmd_data, PVSCSIState,
1234 ARRAY_SIZE(((PVSCSIState *)NULL)->curr_cmd_data)),
1235 VMSTATE_UINT8(rings_info_valid, PVSCSIState),
1236 VMSTATE_UINT8(msg_ring_info_valid, PVSCSIState),
1237 VMSTATE_UINT8(use_msg, PVSCSIState),
1238
1239 VMSTATE_UINT64(rings.rs_pa, PVSCSIState),
1240 VMSTATE_UINT32(rings.txr_len_mask, PVSCSIState),
1241 VMSTATE_UINT32(rings.rxr_len_mask, PVSCSIState),
1242 VMSTATE_UINT64_ARRAY(rings.req_ring_pages_pa, PVSCSIState,
1243 PVSCSI_SETUP_RINGS_MAX_NUM_PAGES),
1244 VMSTATE_UINT64_ARRAY(rings.cmp_ring_pages_pa, PVSCSIState,
1245 PVSCSI_SETUP_RINGS_MAX_NUM_PAGES),
1246 VMSTATE_UINT64(rings.consumed_ptr, PVSCSIState),
1247 VMSTATE_UINT64(rings.filled_cmp_ptr, PVSCSIState),
1248
1249 VMSTATE_END_OF_LIST()
1250 },
1251 .subsections = (const VMStateDescription*[]) {
1252 &vmstate_pvscsi_pcie_device,
1253 NULL
1254 }
1255 };
1256
1257 static Property pvscsi_properties[] = {
1258 DEFINE_PROP_UINT8("use_msg", PVSCSIState, use_msg, 1),
1259 DEFINE_PROP_BIT("x-old-pci-configuration", PVSCSIState, compat_flags,
1260 PVSCSI_COMPAT_OLD_PCI_CONFIGURATION_BIT, false),
1261 DEFINE_PROP_BIT("x-disable-pcie", PVSCSIState, compat_flags,
1262 PVSCSI_COMPAT_DISABLE_PCIE_BIT, false),
1263 DEFINE_PROP_END_OF_LIST(),
1264 };
1265
1266 static void pvscsi_realize(DeviceState *qdev, Error **errp)
1267 {
1268 PVSCSIClass *pvs_c = PVSCSI_DEVICE_GET_CLASS(qdev);
1269 PCIDevice *pci_dev = PCI_DEVICE(qdev);
1270 PVSCSIState *s = PVSCSI(qdev);
1271
1272 if (!(s->compat_flags & PVSCSI_COMPAT_DISABLE_PCIE)) {
1273 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1274 }
1275
1276 pvs_c->parent_dc_realize(qdev, errp);
1277 }
1278
1279 static void pvscsi_class_init(ObjectClass *klass, void *data)
1280 {
1281 DeviceClass *dc = DEVICE_CLASS(klass);
1282 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1283 PVSCSIClass *pvs_k = PVSCSI_DEVICE_CLASS(klass);
1284 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
1285
1286 k->realize = pvscsi_realizefn;
1287 k->exit = pvscsi_uninit;
1288 k->vendor_id = PCI_VENDOR_ID_VMWARE;
1289 k->device_id = PCI_DEVICE_ID_VMWARE_PVSCSI;
1290 k->class_id = PCI_CLASS_STORAGE_SCSI;
1291 k->subsystem_id = 0x1000;
1292 device_class_set_parent_realize(dc, pvscsi_realize,
1293 &pvs_k->parent_dc_realize);
1294 dc->reset = pvscsi_reset;
1295 dc->vmsd = &vmstate_pvscsi;
1296 device_class_set_props(dc, pvscsi_properties);
1297 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
1298 hc->unplug = pvscsi_hot_unplug;
1299 hc->plug = pvscsi_hotplug;
1300 }
1301
1302 static const TypeInfo pvscsi_info = {
1303 .name = TYPE_PVSCSI,
1304 .parent = TYPE_PCI_DEVICE,
1305 .class_size = sizeof(PVSCSIClass),
1306 .instance_size = sizeof(PVSCSIState),
1307 .class_init = pvscsi_class_init,
1308 .interfaces = (InterfaceInfo[]) {
1309 { TYPE_HOTPLUG_HANDLER },
1310 { INTERFACE_PCIE_DEVICE },
1311 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
1312 { }
1313 }
1314 };
1315
1316 static void
1317 pvscsi_register_types(void)
1318 {
1319 type_register_static(&pvscsi_info);
1320 }
1321
1322 type_init(pvscsi_register_types);