17ad5465a76bff7537337bba104771769f47f3d4
[qemu.git] / hw / sd / sdhci.c
1 /*
2 * SD Association Host Standard Specification v2.0 controller emulation
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * Mitsyanko Igor <i.mitsyanko@samsung.com>
6 * Peter A.G. Crosthwaite <peter.crosthwaite@petalogix.com>
7 *
8 * Based on MMC controller for Samsung S5PC1xx-based board emulation
9 * by Alexey Merkulov and Vladimir Monakhov.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
19 * See the GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, see <http://www.gnu.org/licenses/>.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "qemu/error-report.h"
28 #include "qapi/error.h"
29 #include "hw/hw.h"
30 #include "sysemu/dma.h"
31 #include "qemu/timer.h"
32 #include "qemu/bitops.h"
33 #include "hw/sd/sdhci.h"
34 #include "sdhci-internal.h"
35 #include "qemu/log.h"
36 #include "trace.h"
37
38 #define TYPE_SDHCI_BUS "sdhci-bus"
39 #define SDHCI_BUS(obj) OBJECT_CHECK(SDBus, (obj), TYPE_SDHCI_BUS)
40
41 #define MASKED_WRITE(reg, mask, val) (reg = (reg & (mask)) | (val))
42
43 static inline unsigned int sdhci_get_fifolen(SDHCIState *s)
44 {
45 return 1 << (9 + FIELD_EX32(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH));
46 }
47
48 /* return true on error */
49 static bool sdhci_check_capab_freq_range(SDHCIState *s, const char *desc,
50 uint8_t freq, Error **errp)
51 {
52 if (s->sd_spec_version >= 3) {
53 return false;
54 }
55 switch (freq) {
56 case 0:
57 case 10 ... 63:
58 break;
59 default:
60 error_setg(errp, "SD %s clock frequency can have value"
61 "in range 0-63 only", desc);
62 return true;
63 }
64 return false;
65 }
66
67 static void sdhci_check_capareg(SDHCIState *s, Error **errp)
68 {
69 uint64_t msk = s->capareg;
70 uint32_t val;
71 bool y;
72
73 switch (s->sd_spec_version) {
74 case 4:
75 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT_V4);
76 trace_sdhci_capareg("64-bit system bus (v4)", val);
77 msk = FIELD_DP64(msk, SDHC_CAPAB, BUS64BIT_V4, 0);
78
79 val = FIELD_EX64(s->capareg, SDHC_CAPAB, UHS_II);
80 trace_sdhci_capareg("UHS-II", val);
81 msk = FIELD_DP64(msk, SDHC_CAPAB, UHS_II, 0);
82
83 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA3);
84 trace_sdhci_capareg("ADMA3", val);
85 msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA3, 0);
86
87 /* fallthrough */
88 case 3:
89 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ASYNC_INT);
90 trace_sdhci_capareg("async interrupt", val);
91 msk = FIELD_DP64(msk, SDHC_CAPAB, ASYNC_INT, 0);
92
93 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SLOT_TYPE);
94 if (val) {
95 error_setg(errp, "slot-type not supported");
96 return;
97 }
98 trace_sdhci_capareg("slot type", val);
99 msk = FIELD_DP64(msk, SDHC_CAPAB, SLOT_TYPE, 0);
100
101 if (val != 2) {
102 val = FIELD_EX64(s->capareg, SDHC_CAPAB, EMBEDDED_8BIT);
103 trace_sdhci_capareg("8-bit bus", val);
104 }
105 msk = FIELD_DP64(msk, SDHC_CAPAB, EMBEDDED_8BIT, 0);
106
107 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS_SPEED);
108 trace_sdhci_capareg("bus speed mask", val);
109 msk = FIELD_DP64(msk, SDHC_CAPAB, BUS_SPEED, 0);
110
111 val = FIELD_EX64(s->capareg, SDHC_CAPAB, DRIVER_STRENGTH);
112 trace_sdhci_capareg("driver strength mask", val);
113 msk = FIELD_DP64(msk, SDHC_CAPAB, DRIVER_STRENGTH, 0);
114
115 val = FIELD_EX64(s->capareg, SDHC_CAPAB, TIMER_RETUNING);
116 trace_sdhci_capareg("timer re-tuning", val);
117 msk = FIELD_DP64(msk, SDHC_CAPAB, TIMER_RETUNING, 0);
118
119 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SDR50_TUNING);
120 trace_sdhci_capareg("use SDR50 tuning", val);
121 msk = FIELD_DP64(msk, SDHC_CAPAB, SDR50_TUNING, 0);
122
123 val = FIELD_EX64(s->capareg, SDHC_CAPAB, RETUNING_MODE);
124 trace_sdhci_capareg("re-tuning mode", val);
125 msk = FIELD_DP64(msk, SDHC_CAPAB, RETUNING_MODE, 0);
126
127 val = FIELD_EX64(s->capareg, SDHC_CAPAB, CLOCK_MULT);
128 trace_sdhci_capareg("clock multiplier", val);
129 msk = FIELD_DP64(msk, SDHC_CAPAB, CLOCK_MULT, 0);
130
131 /* fallthrough */
132 case 2: /* default version */
133 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA2);
134 trace_sdhci_capareg("ADMA2", val);
135 msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA2, 0);
136
137 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA1);
138 trace_sdhci_capareg("ADMA1", val);
139 msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA1, 0);
140
141 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT);
142 trace_sdhci_capareg("64-bit system bus (v3)", val);
143 msk = FIELD_DP64(msk, SDHC_CAPAB, BUS64BIT, 0);
144
145 /* fallthrough */
146 case 1:
147 y = FIELD_EX64(s->capareg, SDHC_CAPAB, TOUNIT);
148 msk = FIELD_DP64(msk, SDHC_CAPAB, TOUNIT, 0);
149
150 val = FIELD_EX64(s->capareg, SDHC_CAPAB, TOCLKFREQ);
151 trace_sdhci_capareg(y ? "timeout (MHz)" : "Timeout (KHz)", val);
152 if (sdhci_check_capab_freq_range(s, "timeout", val, errp)) {
153 return;
154 }
155 msk = FIELD_DP64(msk, SDHC_CAPAB, TOCLKFREQ, 0);
156
157 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BASECLKFREQ);
158 trace_sdhci_capareg(y ? "base (MHz)" : "Base (KHz)", val);
159 if (sdhci_check_capab_freq_range(s, "base", val, errp)) {
160 return;
161 }
162 msk = FIELD_DP64(msk, SDHC_CAPAB, BASECLKFREQ, 0);
163
164 val = FIELD_EX64(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH);
165 if (val >= 3) {
166 error_setg(errp, "block size can be 512, 1024 or 2048 only");
167 return;
168 }
169 trace_sdhci_capareg("max block length", sdhci_get_fifolen(s));
170 msk = FIELD_DP64(msk, SDHC_CAPAB, MAXBLOCKLENGTH, 0);
171
172 val = FIELD_EX64(s->capareg, SDHC_CAPAB, HIGHSPEED);
173 trace_sdhci_capareg("high speed", val);
174 msk = FIELD_DP64(msk, SDHC_CAPAB, HIGHSPEED, 0);
175
176 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SDMA);
177 trace_sdhci_capareg("SDMA", val);
178 msk = FIELD_DP64(msk, SDHC_CAPAB, SDMA, 0);
179
180 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SUSPRESUME);
181 trace_sdhci_capareg("suspend/resume", val);
182 msk = FIELD_DP64(msk, SDHC_CAPAB, SUSPRESUME, 0);
183
184 val = FIELD_EX64(s->capareg, SDHC_CAPAB, V33);
185 trace_sdhci_capareg("3.3v", val);
186 msk = FIELD_DP64(msk, SDHC_CAPAB, V33, 0);
187
188 val = FIELD_EX64(s->capareg, SDHC_CAPAB, V30);
189 trace_sdhci_capareg("3.0v", val);
190 msk = FIELD_DP64(msk, SDHC_CAPAB, V30, 0);
191
192 val = FIELD_EX64(s->capareg, SDHC_CAPAB, V18);
193 trace_sdhci_capareg("1.8v", val);
194 msk = FIELD_DP64(msk, SDHC_CAPAB, V18, 0);
195 break;
196
197 default:
198 error_setg(errp, "Unsupported spec version: %u", s->sd_spec_version);
199 }
200 if (msk) {
201 qemu_log_mask(LOG_UNIMP,
202 "SDHCI: unknown CAPAB mask: 0x%016" PRIx64 "\n", msk);
203 }
204 }
205
206 static uint8_t sdhci_slotint(SDHCIState *s)
207 {
208 return (s->norintsts & s->norintsigen) || (s->errintsts & s->errintsigen) ||
209 ((s->norintsts & SDHC_NIS_INSERT) && (s->wakcon & SDHC_WKUP_ON_INS)) ||
210 ((s->norintsts & SDHC_NIS_REMOVE) && (s->wakcon & SDHC_WKUP_ON_RMV));
211 }
212
213 static inline void sdhci_update_irq(SDHCIState *s)
214 {
215 qemu_set_irq(s->irq, sdhci_slotint(s));
216 }
217
218 static void sdhci_raise_insertion_irq(void *opaque)
219 {
220 SDHCIState *s = (SDHCIState *)opaque;
221
222 if (s->norintsts & SDHC_NIS_REMOVE) {
223 timer_mod(s->insert_timer,
224 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY);
225 } else {
226 s->prnsts = 0x1ff0000;
227 if (s->norintstsen & SDHC_NISEN_INSERT) {
228 s->norintsts |= SDHC_NIS_INSERT;
229 }
230 sdhci_update_irq(s);
231 }
232 }
233
234 static void sdhci_set_inserted(DeviceState *dev, bool level)
235 {
236 SDHCIState *s = (SDHCIState *)dev;
237
238 trace_sdhci_set_inserted(level ? "insert" : "eject");
239 if ((s->norintsts & SDHC_NIS_REMOVE) && level) {
240 /* Give target some time to notice card ejection */
241 timer_mod(s->insert_timer,
242 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY);
243 } else {
244 if (level) {
245 s->prnsts = 0x1ff0000;
246 if (s->norintstsen & SDHC_NISEN_INSERT) {
247 s->norintsts |= SDHC_NIS_INSERT;
248 }
249 } else {
250 s->prnsts = 0x1fa0000;
251 s->pwrcon &= ~SDHC_POWER_ON;
252 s->clkcon &= ~SDHC_CLOCK_SDCLK_EN;
253 if (s->norintstsen & SDHC_NISEN_REMOVE) {
254 s->norintsts |= SDHC_NIS_REMOVE;
255 }
256 }
257 sdhci_update_irq(s);
258 }
259 }
260
261 static void sdhci_set_readonly(DeviceState *dev, bool level)
262 {
263 SDHCIState *s = (SDHCIState *)dev;
264
265 if (level) {
266 s->prnsts &= ~SDHC_WRITE_PROTECT;
267 } else {
268 /* Write enabled */
269 s->prnsts |= SDHC_WRITE_PROTECT;
270 }
271 }
272
273 static void sdhci_reset(SDHCIState *s)
274 {
275 DeviceState *dev = DEVICE(s);
276
277 timer_del(s->insert_timer);
278 timer_del(s->transfer_timer);
279
280 /* Set all registers to 0. Capabilities/Version registers are not cleared
281 * and assumed to always preserve their value, given to them during
282 * initialization */
283 memset(&s->sdmasysad, 0, (uintptr_t)&s->capareg - (uintptr_t)&s->sdmasysad);
284
285 /* Reset other state based on current card insertion/readonly status */
286 sdhci_set_inserted(dev, sdbus_get_inserted(&s->sdbus));
287 sdhci_set_readonly(dev, sdbus_get_readonly(&s->sdbus));
288
289 s->data_count = 0;
290 s->stopped_state = sdhc_not_stopped;
291 s->pending_insert_state = false;
292 }
293
294 static void sdhci_poweron_reset(DeviceState *dev)
295 {
296 /* QOM (ie power-on) reset. This is identical to reset
297 * commanded via device register apart from handling of the
298 * 'pending insert on powerup' quirk.
299 */
300 SDHCIState *s = (SDHCIState *)dev;
301
302 sdhci_reset(s);
303
304 if (s->pending_insert_quirk) {
305 s->pending_insert_state = true;
306 }
307 }
308
309 static void sdhci_data_transfer(void *opaque);
310
311 static void sdhci_send_command(SDHCIState *s)
312 {
313 SDRequest request;
314 uint8_t response[16];
315 int rlen;
316
317 s->errintsts = 0;
318 s->acmd12errsts = 0;
319 request.cmd = s->cmdreg >> 8;
320 request.arg = s->argument;
321
322 trace_sdhci_send_command(request.cmd, request.arg);
323 rlen = sdbus_do_command(&s->sdbus, &request, response);
324
325 if (s->cmdreg & SDHC_CMD_RESPONSE) {
326 if (rlen == 4) {
327 s->rspreg[0] = ldl_be_p(response);
328 s->rspreg[1] = s->rspreg[2] = s->rspreg[3] = 0;
329 trace_sdhci_response4(s->rspreg[0]);
330 } else if (rlen == 16) {
331 s->rspreg[0] = ldl_be_p(&response[11]);
332 s->rspreg[1] = ldl_be_p(&response[7]);
333 s->rspreg[2] = ldl_be_p(&response[3]);
334 s->rspreg[3] = (response[0] << 16) | (response[1] << 8) |
335 response[2];
336 trace_sdhci_response16(s->rspreg[3], s->rspreg[2],
337 s->rspreg[1], s->rspreg[0]);
338 } else {
339 trace_sdhci_error("timeout waiting for command response");
340 if (s->errintstsen & SDHC_EISEN_CMDTIMEOUT) {
341 s->errintsts |= SDHC_EIS_CMDTIMEOUT;
342 s->norintsts |= SDHC_NIS_ERR;
343 }
344 }
345
346 if (!(s->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
347 (s->norintstsen & SDHC_NISEN_TRSCMP) &&
348 (s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY) {
349 s->norintsts |= SDHC_NIS_TRSCMP;
350 }
351 }
352
353 if (s->norintstsen & SDHC_NISEN_CMDCMP) {
354 s->norintsts |= SDHC_NIS_CMDCMP;
355 }
356
357 sdhci_update_irq(s);
358
359 if (s->blksize && (s->cmdreg & SDHC_CMD_DATA_PRESENT)) {
360 s->data_count = 0;
361 sdhci_data_transfer(s);
362 }
363 }
364
365 static void sdhci_end_transfer(SDHCIState *s)
366 {
367 /* Automatically send CMD12 to stop transfer if AutoCMD12 enabled */
368 if ((s->trnmod & SDHC_TRNS_ACMD12) != 0) {
369 SDRequest request;
370 uint8_t response[16];
371
372 request.cmd = 0x0C;
373 request.arg = 0;
374 trace_sdhci_end_transfer(request.cmd, request.arg);
375 sdbus_do_command(&s->sdbus, &request, response);
376 /* Auto CMD12 response goes to the upper Response register */
377 s->rspreg[3] = ldl_be_p(response);
378 }
379
380 s->prnsts &= ~(SDHC_DOING_READ | SDHC_DOING_WRITE |
381 SDHC_DAT_LINE_ACTIVE | SDHC_DATA_INHIBIT |
382 SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE);
383
384 if (s->norintstsen & SDHC_NISEN_TRSCMP) {
385 s->norintsts |= SDHC_NIS_TRSCMP;
386 }
387
388 sdhci_update_irq(s);
389 }
390
391 /*
392 * Programmed i/o data transfer
393 */
394 #define BLOCK_SIZE_MASK (4 * KiB - 1)
395
396 /* Fill host controller's read buffer with BLKSIZE bytes of data from card */
397 static void sdhci_read_block_from_card(SDHCIState *s)
398 {
399 int index = 0;
400 uint8_t data;
401 const uint16_t blk_size = s->blksize & BLOCK_SIZE_MASK;
402
403 if ((s->trnmod & SDHC_TRNS_MULTI) &&
404 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) {
405 return;
406 }
407
408 for (index = 0; index < blk_size; index++) {
409 data = sdbus_read_data(&s->sdbus);
410 if (!FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, EXECUTE_TUNING)) {
411 /* Device is not in tuning */
412 s->fifo_buffer[index] = data;
413 }
414 }
415
416 if (FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, EXECUTE_TUNING)) {
417 /* Device is in tuning */
418 s->hostctl2 &= ~R_SDHC_HOSTCTL2_EXECUTE_TUNING_MASK;
419 s->hostctl2 |= R_SDHC_HOSTCTL2_SAMPLING_CLKSEL_MASK;
420 s->prnsts &= ~(SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ |
421 SDHC_DATA_INHIBIT);
422 goto read_done;
423 }
424
425 /* New data now available for READ through Buffer Port Register */
426 s->prnsts |= SDHC_DATA_AVAILABLE;
427 if (s->norintstsen & SDHC_NISEN_RBUFRDY) {
428 s->norintsts |= SDHC_NIS_RBUFRDY;
429 }
430
431 /* Clear DAT line active status if that was the last block */
432 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 ||
433 ((s->trnmod & SDHC_TRNS_MULTI) && s->blkcnt == 1)) {
434 s->prnsts &= ~SDHC_DAT_LINE_ACTIVE;
435 }
436
437 /* If stop at block gap request was set and it's not the last block of
438 * data - generate Block Event interrupt */
439 if (s->stopped_state == sdhc_gap_read && (s->trnmod & SDHC_TRNS_MULTI) &&
440 s->blkcnt != 1) {
441 s->prnsts &= ~SDHC_DAT_LINE_ACTIVE;
442 if (s->norintstsen & SDHC_EISEN_BLKGAP) {
443 s->norintsts |= SDHC_EIS_BLKGAP;
444 }
445 }
446
447 read_done:
448 sdhci_update_irq(s);
449 }
450
451 /* Read @size byte of data from host controller @s BUFFER DATA PORT register */
452 static uint32_t sdhci_read_dataport(SDHCIState *s, unsigned size)
453 {
454 uint32_t value = 0;
455 int i;
456
457 /* first check that a valid data exists in host controller input buffer */
458 if ((s->prnsts & SDHC_DATA_AVAILABLE) == 0) {
459 trace_sdhci_error("read from empty buffer");
460 return 0;
461 }
462
463 for (i = 0; i < size; i++) {
464 value |= s->fifo_buffer[s->data_count] << i * 8;
465 s->data_count++;
466 /* check if we've read all valid data (blksize bytes) from buffer */
467 if ((s->data_count) >= (s->blksize & BLOCK_SIZE_MASK)) {
468 trace_sdhci_read_dataport(s->data_count);
469 s->prnsts &= ~SDHC_DATA_AVAILABLE; /* no more data in a buffer */
470 s->data_count = 0; /* next buff read must start at position [0] */
471
472 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
473 s->blkcnt--;
474 }
475
476 /* if that was the last block of data */
477 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 ||
478 ((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) ||
479 /* stop at gap request */
480 (s->stopped_state == sdhc_gap_read &&
481 !(s->prnsts & SDHC_DAT_LINE_ACTIVE))) {
482 sdhci_end_transfer(s);
483 } else { /* if there are more data, read next block from card */
484 sdhci_read_block_from_card(s);
485 }
486 break;
487 }
488 }
489
490 return value;
491 }
492
493 /* Write data from host controller FIFO to card */
494 static void sdhci_write_block_to_card(SDHCIState *s)
495 {
496 int index = 0;
497
498 if (s->prnsts & SDHC_SPACE_AVAILABLE) {
499 if (s->norintstsen & SDHC_NISEN_WBUFRDY) {
500 s->norintsts |= SDHC_NIS_WBUFRDY;
501 }
502 sdhci_update_irq(s);
503 return;
504 }
505
506 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
507 if (s->blkcnt == 0) {
508 return;
509 } else {
510 s->blkcnt--;
511 }
512 }
513
514 for (index = 0; index < (s->blksize & BLOCK_SIZE_MASK); index++) {
515 sdbus_write_data(&s->sdbus, s->fifo_buffer[index]);
516 }
517
518 /* Next data can be written through BUFFER DATORT register */
519 s->prnsts |= SDHC_SPACE_AVAILABLE;
520
521 /* Finish transfer if that was the last block of data */
522 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 ||
523 ((s->trnmod & SDHC_TRNS_MULTI) &&
524 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0))) {
525 sdhci_end_transfer(s);
526 } else if (s->norintstsen & SDHC_NISEN_WBUFRDY) {
527 s->norintsts |= SDHC_NIS_WBUFRDY;
528 }
529
530 /* Generate Block Gap Event if requested and if not the last block */
531 if (s->stopped_state == sdhc_gap_write && (s->trnmod & SDHC_TRNS_MULTI) &&
532 s->blkcnt > 0) {
533 s->prnsts &= ~SDHC_DOING_WRITE;
534 if (s->norintstsen & SDHC_EISEN_BLKGAP) {
535 s->norintsts |= SDHC_EIS_BLKGAP;
536 }
537 sdhci_end_transfer(s);
538 }
539
540 sdhci_update_irq(s);
541 }
542
543 /* Write @size bytes of @value data to host controller @s Buffer Data Port
544 * register */
545 static void sdhci_write_dataport(SDHCIState *s, uint32_t value, unsigned size)
546 {
547 unsigned i;
548
549 /* Check that there is free space left in a buffer */
550 if (!(s->prnsts & SDHC_SPACE_AVAILABLE)) {
551 trace_sdhci_error("Can't write to data buffer: buffer full");
552 return;
553 }
554
555 for (i = 0; i < size; i++) {
556 s->fifo_buffer[s->data_count] = value & 0xFF;
557 s->data_count++;
558 value >>= 8;
559 if (s->data_count >= (s->blksize & BLOCK_SIZE_MASK)) {
560 trace_sdhci_write_dataport(s->data_count);
561 s->data_count = 0;
562 s->prnsts &= ~SDHC_SPACE_AVAILABLE;
563 if (s->prnsts & SDHC_DOING_WRITE) {
564 sdhci_write_block_to_card(s);
565 }
566 }
567 }
568 }
569
570 /*
571 * Single DMA data transfer
572 */
573
574 /* Multi block SDMA transfer */
575 static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s)
576 {
577 bool page_aligned = false;
578 unsigned int n, begin;
579 const uint16_t block_size = s->blksize & BLOCK_SIZE_MASK;
580 uint32_t boundary_chk = 1 << (((s->blksize & ~BLOCK_SIZE_MASK) >> 12) + 12);
581 uint32_t boundary_count = boundary_chk - (s->sdmasysad % boundary_chk);
582
583 if (!(s->trnmod & SDHC_TRNS_BLK_CNT_EN) || !s->blkcnt) {
584 qemu_log_mask(LOG_UNIMP, "infinite transfer is not supported\n");
585 return;
586 }
587
588 /* XXX: Some sd/mmc drivers (for example, u-boot-slp) do not account for
589 * possible stop at page boundary if initial address is not page aligned,
590 * allow them to work properly */
591 if ((s->sdmasysad % boundary_chk) == 0) {
592 page_aligned = true;
593 }
594
595 if (s->trnmod & SDHC_TRNS_READ) {
596 s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT |
597 SDHC_DAT_LINE_ACTIVE;
598 while (s->blkcnt) {
599 if (s->data_count == 0) {
600 for (n = 0; n < block_size; n++) {
601 s->fifo_buffer[n] = sdbus_read_data(&s->sdbus);
602 }
603 }
604 begin = s->data_count;
605 if (((boundary_count + begin) < block_size) && page_aligned) {
606 s->data_count = boundary_count + begin;
607 boundary_count = 0;
608 } else {
609 s->data_count = block_size;
610 boundary_count -= block_size - begin;
611 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
612 s->blkcnt--;
613 }
614 }
615 dma_memory_write(s->dma_as, s->sdmasysad,
616 &s->fifo_buffer[begin], s->data_count - begin);
617 s->sdmasysad += s->data_count - begin;
618 if (s->data_count == block_size) {
619 s->data_count = 0;
620 }
621 if (page_aligned && boundary_count == 0) {
622 break;
623 }
624 }
625 } else {
626 s->prnsts |= SDHC_DOING_WRITE | SDHC_DATA_INHIBIT |
627 SDHC_DAT_LINE_ACTIVE;
628 while (s->blkcnt) {
629 begin = s->data_count;
630 if (((boundary_count + begin) < block_size) && page_aligned) {
631 s->data_count = boundary_count + begin;
632 boundary_count = 0;
633 } else {
634 s->data_count = block_size;
635 boundary_count -= block_size - begin;
636 }
637 dma_memory_read(s->dma_as, s->sdmasysad,
638 &s->fifo_buffer[begin], s->data_count - begin);
639 s->sdmasysad += s->data_count - begin;
640 if (s->data_count == block_size) {
641 for (n = 0; n < block_size; n++) {
642 sdbus_write_data(&s->sdbus, s->fifo_buffer[n]);
643 }
644 s->data_count = 0;
645 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
646 s->blkcnt--;
647 }
648 }
649 if (page_aligned && boundary_count == 0) {
650 break;
651 }
652 }
653 }
654
655 if (s->blkcnt == 0) {
656 sdhci_end_transfer(s);
657 } else {
658 if (s->norintstsen & SDHC_NISEN_DMA) {
659 s->norintsts |= SDHC_NIS_DMA;
660 }
661 sdhci_update_irq(s);
662 }
663 }
664
665 /* single block SDMA transfer */
666 static void sdhci_sdma_transfer_single_block(SDHCIState *s)
667 {
668 int n;
669 uint32_t datacnt = s->blksize & BLOCK_SIZE_MASK;
670
671 if (s->trnmod & SDHC_TRNS_READ) {
672 for (n = 0; n < datacnt; n++) {
673 s->fifo_buffer[n] = sdbus_read_data(&s->sdbus);
674 }
675 dma_memory_write(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt);
676 } else {
677 dma_memory_read(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt);
678 for (n = 0; n < datacnt; n++) {
679 sdbus_write_data(&s->sdbus, s->fifo_buffer[n]);
680 }
681 }
682 s->blkcnt--;
683
684 sdhci_end_transfer(s);
685 }
686
687 typedef struct ADMADescr {
688 hwaddr addr;
689 uint16_t length;
690 uint8_t attr;
691 uint8_t incr;
692 } ADMADescr;
693
694 static void get_adma_description(SDHCIState *s, ADMADescr *dscr)
695 {
696 uint32_t adma1 = 0;
697 uint64_t adma2 = 0;
698 hwaddr entry_addr = (hwaddr)s->admasysaddr;
699 switch (SDHC_DMA_TYPE(s->hostctl1)) {
700 case SDHC_CTRL_ADMA2_32:
701 dma_memory_read(s->dma_as, entry_addr, (uint8_t *)&adma2,
702 sizeof(adma2));
703 adma2 = le64_to_cpu(adma2);
704 /* The spec does not specify endianness of descriptor table.
705 * We currently assume that it is LE.
706 */
707 dscr->addr = (hwaddr)extract64(adma2, 32, 32) & ~0x3ull;
708 dscr->length = (uint16_t)extract64(adma2, 16, 16);
709 dscr->attr = (uint8_t)extract64(adma2, 0, 7);
710 dscr->incr = 8;
711 break;
712 case SDHC_CTRL_ADMA1_32:
713 dma_memory_read(s->dma_as, entry_addr, (uint8_t *)&adma1,
714 sizeof(adma1));
715 adma1 = le32_to_cpu(adma1);
716 dscr->addr = (hwaddr)(adma1 & 0xFFFFF000);
717 dscr->attr = (uint8_t)extract32(adma1, 0, 7);
718 dscr->incr = 4;
719 if ((dscr->attr & SDHC_ADMA_ATTR_ACT_MASK) == SDHC_ADMA_ATTR_SET_LEN) {
720 dscr->length = (uint16_t)extract32(adma1, 12, 16);
721 } else {
722 dscr->length = 4 * KiB;
723 }
724 break;
725 case SDHC_CTRL_ADMA2_64:
726 dma_memory_read(s->dma_as, entry_addr,
727 (uint8_t *)(&dscr->attr), 1);
728 dma_memory_read(s->dma_as, entry_addr + 2,
729 (uint8_t *)(&dscr->length), 2);
730 dscr->length = le16_to_cpu(dscr->length);
731 dma_memory_read(s->dma_as, entry_addr + 4,
732 (uint8_t *)(&dscr->addr), 8);
733 dscr->addr = le64_to_cpu(dscr->addr);
734 dscr->attr &= (uint8_t) ~0xC0;
735 dscr->incr = 12;
736 break;
737 }
738 }
739
740 /* Advanced DMA data transfer */
741
742 static void sdhci_do_adma(SDHCIState *s)
743 {
744 unsigned int n, begin, length;
745 const uint16_t block_size = s->blksize & BLOCK_SIZE_MASK;
746 ADMADescr dscr = {};
747 int i;
748
749 for (i = 0; i < SDHC_ADMA_DESCS_PER_DELAY; ++i) {
750 s->admaerr &= ~SDHC_ADMAERR_LENGTH_MISMATCH;
751
752 get_adma_description(s, &dscr);
753 trace_sdhci_adma_loop(dscr.addr, dscr.length, dscr.attr);
754
755 if ((dscr.attr & SDHC_ADMA_ATTR_VALID) == 0) {
756 /* Indicate that error occurred in ST_FDS state */
757 s->admaerr &= ~SDHC_ADMAERR_STATE_MASK;
758 s->admaerr |= SDHC_ADMAERR_STATE_ST_FDS;
759
760 /* Generate ADMA error interrupt */
761 if (s->errintstsen & SDHC_EISEN_ADMAERR) {
762 s->errintsts |= SDHC_EIS_ADMAERR;
763 s->norintsts |= SDHC_NIS_ERR;
764 }
765
766 sdhci_update_irq(s);
767 return;
768 }
769
770 length = dscr.length ? dscr.length : 64 * KiB;
771
772 switch (dscr.attr & SDHC_ADMA_ATTR_ACT_MASK) {
773 case SDHC_ADMA_ATTR_ACT_TRAN: /* data transfer */
774
775 if (s->trnmod & SDHC_TRNS_READ) {
776 while (length) {
777 if (s->data_count == 0) {
778 for (n = 0; n < block_size; n++) {
779 s->fifo_buffer[n] = sdbus_read_data(&s->sdbus);
780 }
781 }
782 begin = s->data_count;
783 if ((length + begin) < block_size) {
784 s->data_count = length + begin;
785 length = 0;
786 } else {
787 s->data_count = block_size;
788 length -= block_size - begin;
789 }
790 dma_memory_write(s->dma_as, dscr.addr,
791 &s->fifo_buffer[begin],
792 s->data_count - begin);
793 dscr.addr += s->data_count - begin;
794 if (s->data_count == block_size) {
795 s->data_count = 0;
796 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
797 s->blkcnt--;
798 if (s->blkcnt == 0) {
799 break;
800 }
801 }
802 }
803 }
804 } else {
805 while (length) {
806 begin = s->data_count;
807 if ((length + begin) < block_size) {
808 s->data_count = length + begin;
809 length = 0;
810 } else {
811 s->data_count = block_size;
812 length -= block_size - begin;
813 }
814 dma_memory_read(s->dma_as, dscr.addr,
815 &s->fifo_buffer[begin],
816 s->data_count - begin);
817 dscr.addr += s->data_count - begin;
818 if (s->data_count == block_size) {
819 for (n = 0; n < block_size; n++) {
820 sdbus_write_data(&s->sdbus, s->fifo_buffer[n]);
821 }
822 s->data_count = 0;
823 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
824 s->blkcnt--;
825 if (s->blkcnt == 0) {
826 break;
827 }
828 }
829 }
830 }
831 }
832 s->admasysaddr += dscr.incr;
833 break;
834 case SDHC_ADMA_ATTR_ACT_LINK: /* link to next descriptor table */
835 s->admasysaddr = dscr.addr;
836 trace_sdhci_adma("link", s->admasysaddr);
837 break;
838 default:
839 s->admasysaddr += dscr.incr;
840 break;
841 }
842
843 if (dscr.attr & SDHC_ADMA_ATTR_INT) {
844 trace_sdhci_adma("interrupt", s->admasysaddr);
845 if (s->norintstsen & SDHC_NISEN_DMA) {
846 s->norintsts |= SDHC_NIS_DMA;
847 }
848
849 sdhci_update_irq(s);
850 }
851
852 /* ADMA transfer terminates if blkcnt == 0 or by END attribute */
853 if (((s->trnmod & SDHC_TRNS_BLK_CNT_EN) &&
854 (s->blkcnt == 0)) || (dscr.attr & SDHC_ADMA_ATTR_END)) {
855 trace_sdhci_adma_transfer_completed();
856 if (length || ((dscr.attr & SDHC_ADMA_ATTR_END) &&
857 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) &&
858 s->blkcnt != 0)) {
859 trace_sdhci_error("SD/MMC host ADMA length mismatch");
860 s->admaerr |= SDHC_ADMAERR_LENGTH_MISMATCH |
861 SDHC_ADMAERR_STATE_ST_TFR;
862 if (s->errintstsen & SDHC_EISEN_ADMAERR) {
863 trace_sdhci_error("Set ADMA error flag");
864 s->errintsts |= SDHC_EIS_ADMAERR;
865 s->norintsts |= SDHC_NIS_ERR;
866 }
867
868 sdhci_update_irq(s);
869 }
870 sdhci_end_transfer(s);
871 return;
872 }
873
874 }
875
876 /* we have unfinished business - reschedule to continue ADMA */
877 timer_mod(s->transfer_timer,
878 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_TRANSFER_DELAY);
879 }
880
881 /* Perform data transfer according to controller configuration */
882
883 static void sdhci_data_transfer(void *opaque)
884 {
885 SDHCIState *s = (SDHCIState *)opaque;
886
887 if (s->trnmod & SDHC_TRNS_DMA) {
888 switch (SDHC_DMA_TYPE(s->hostctl1)) {
889 case SDHC_CTRL_SDMA:
890 if ((s->blkcnt == 1) || !(s->trnmod & SDHC_TRNS_MULTI)) {
891 sdhci_sdma_transfer_single_block(s);
892 } else {
893 sdhci_sdma_transfer_multi_blocks(s);
894 }
895
896 break;
897 case SDHC_CTRL_ADMA1_32:
898 if (!(s->capareg & R_SDHC_CAPAB_ADMA1_MASK)) {
899 trace_sdhci_error("ADMA1 not supported");
900 break;
901 }
902
903 sdhci_do_adma(s);
904 break;
905 case SDHC_CTRL_ADMA2_32:
906 if (!(s->capareg & R_SDHC_CAPAB_ADMA2_MASK)) {
907 trace_sdhci_error("ADMA2 not supported");
908 break;
909 }
910
911 sdhci_do_adma(s);
912 break;
913 case SDHC_CTRL_ADMA2_64:
914 if (!(s->capareg & R_SDHC_CAPAB_ADMA2_MASK) ||
915 !(s->capareg & R_SDHC_CAPAB_BUS64BIT_MASK)) {
916 trace_sdhci_error("64 bit ADMA not supported");
917 break;
918 }
919
920 sdhci_do_adma(s);
921 break;
922 default:
923 trace_sdhci_error("Unsupported DMA type");
924 break;
925 }
926 } else {
927 if ((s->trnmod & SDHC_TRNS_READ) && sdbus_data_ready(&s->sdbus)) {
928 s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT |
929 SDHC_DAT_LINE_ACTIVE;
930 sdhci_read_block_from_card(s);
931 } else {
932 s->prnsts |= SDHC_DOING_WRITE | SDHC_DAT_LINE_ACTIVE |
933 SDHC_SPACE_AVAILABLE | SDHC_DATA_INHIBIT;
934 sdhci_write_block_to_card(s);
935 }
936 }
937 }
938
939 static bool sdhci_can_issue_command(SDHCIState *s)
940 {
941 if (!SDHC_CLOCK_IS_ON(s->clkcon) ||
942 (((s->prnsts & SDHC_DATA_INHIBIT) || s->stopped_state) &&
943 ((s->cmdreg & SDHC_CMD_DATA_PRESENT) ||
944 ((s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY &&
945 !(SDHC_COMMAND_TYPE(s->cmdreg) == SDHC_CMD_ABORT))))) {
946 return false;
947 }
948
949 return true;
950 }
951
952 /* The Buffer Data Port register must be accessed in sequential and
953 * continuous manner */
954 static inline bool
955 sdhci_buff_access_is_sequential(SDHCIState *s, unsigned byte_num)
956 {
957 if ((s->data_count & 0x3) != byte_num) {
958 trace_sdhci_error("Non-sequential access to Buffer Data Port register"
959 "is prohibited\n");
960 return false;
961 }
962 return true;
963 }
964
965 static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size)
966 {
967 SDHCIState *s = (SDHCIState *)opaque;
968 uint32_t ret = 0;
969
970 switch (offset & ~0x3) {
971 case SDHC_SYSAD:
972 ret = s->sdmasysad;
973 break;
974 case SDHC_BLKSIZE:
975 ret = s->blksize | (s->blkcnt << 16);
976 break;
977 case SDHC_ARGUMENT:
978 ret = s->argument;
979 break;
980 case SDHC_TRNMOD:
981 ret = s->trnmod | (s->cmdreg << 16);
982 break;
983 case SDHC_RSPREG0 ... SDHC_RSPREG3:
984 ret = s->rspreg[((offset & ~0x3) - SDHC_RSPREG0) >> 2];
985 break;
986 case SDHC_BDATA:
987 if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) {
988 ret = sdhci_read_dataport(s, size);
989 trace_sdhci_access("rd", size << 3, offset, "->", ret, ret);
990 return ret;
991 }
992 break;
993 case SDHC_PRNSTS:
994 ret = s->prnsts;
995 ret = FIELD_DP32(ret, SDHC_PRNSTS, DAT_LVL,
996 sdbus_get_dat_lines(&s->sdbus));
997 ret = FIELD_DP32(ret, SDHC_PRNSTS, CMD_LVL,
998 sdbus_get_cmd_line(&s->sdbus));
999 break;
1000 case SDHC_HOSTCTL:
1001 ret = s->hostctl1 | (s->pwrcon << 8) | (s->blkgap << 16) |
1002 (s->wakcon << 24);
1003 break;
1004 case SDHC_CLKCON:
1005 ret = s->clkcon | (s->timeoutcon << 16);
1006 break;
1007 case SDHC_NORINTSTS:
1008 ret = s->norintsts | (s->errintsts << 16);
1009 break;
1010 case SDHC_NORINTSTSEN:
1011 ret = s->norintstsen | (s->errintstsen << 16);
1012 break;
1013 case SDHC_NORINTSIGEN:
1014 ret = s->norintsigen | (s->errintsigen << 16);
1015 break;
1016 case SDHC_ACMD12ERRSTS:
1017 ret = s->acmd12errsts | (s->hostctl2 << 16);
1018 break;
1019 case SDHC_CAPAB:
1020 ret = (uint32_t)s->capareg;
1021 break;
1022 case SDHC_CAPAB + 4:
1023 ret = (uint32_t)(s->capareg >> 32);
1024 break;
1025 case SDHC_MAXCURR:
1026 ret = (uint32_t)s->maxcurr;
1027 break;
1028 case SDHC_MAXCURR + 4:
1029 ret = (uint32_t)(s->maxcurr >> 32);
1030 break;
1031 case SDHC_ADMAERR:
1032 ret = s->admaerr;
1033 break;
1034 case SDHC_ADMASYSADDR:
1035 ret = (uint32_t)s->admasysaddr;
1036 break;
1037 case SDHC_ADMASYSADDR + 4:
1038 ret = (uint32_t)(s->admasysaddr >> 32);
1039 break;
1040 case SDHC_SLOT_INT_STATUS:
1041 ret = (s->version << 16) | sdhci_slotint(s);
1042 break;
1043 default:
1044 qemu_log_mask(LOG_UNIMP, "SDHC rd_%ub @0x%02" HWADDR_PRIx " "
1045 "not implemented\n", size, offset);
1046 break;
1047 }
1048
1049 ret >>= (offset & 0x3) * 8;
1050 ret &= (1ULL << (size * 8)) - 1;
1051 trace_sdhci_access("rd", size << 3, offset, "->", ret, ret);
1052 return ret;
1053 }
1054
1055 static inline void sdhci_blkgap_write(SDHCIState *s, uint8_t value)
1056 {
1057 if ((value & SDHC_STOP_AT_GAP_REQ) && (s->blkgap & SDHC_STOP_AT_GAP_REQ)) {
1058 return;
1059 }
1060 s->blkgap = value & SDHC_STOP_AT_GAP_REQ;
1061
1062 if ((value & SDHC_CONTINUE_REQ) && s->stopped_state &&
1063 (s->blkgap & SDHC_STOP_AT_GAP_REQ) == 0) {
1064 if (s->stopped_state == sdhc_gap_read) {
1065 s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ;
1066 sdhci_read_block_from_card(s);
1067 } else {
1068 s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_WRITE;
1069 sdhci_write_block_to_card(s);
1070 }
1071 s->stopped_state = sdhc_not_stopped;
1072 } else if (!s->stopped_state && (value & SDHC_STOP_AT_GAP_REQ)) {
1073 if (s->prnsts & SDHC_DOING_READ) {
1074 s->stopped_state = sdhc_gap_read;
1075 } else if (s->prnsts & SDHC_DOING_WRITE) {
1076 s->stopped_state = sdhc_gap_write;
1077 }
1078 }
1079 }
1080
1081 static inline void sdhci_reset_write(SDHCIState *s, uint8_t value)
1082 {
1083 switch (value) {
1084 case SDHC_RESET_ALL:
1085 sdhci_reset(s);
1086 break;
1087 case SDHC_RESET_CMD:
1088 s->prnsts &= ~SDHC_CMD_INHIBIT;
1089 s->norintsts &= ~SDHC_NIS_CMDCMP;
1090 break;
1091 case SDHC_RESET_DATA:
1092 s->data_count = 0;
1093 s->prnsts &= ~(SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE |
1094 SDHC_DOING_READ | SDHC_DOING_WRITE |
1095 SDHC_DATA_INHIBIT | SDHC_DAT_LINE_ACTIVE);
1096 s->blkgap &= ~(SDHC_STOP_AT_GAP_REQ | SDHC_CONTINUE_REQ);
1097 s->stopped_state = sdhc_not_stopped;
1098 s->norintsts &= ~(SDHC_NIS_WBUFRDY | SDHC_NIS_RBUFRDY |
1099 SDHC_NIS_DMA | SDHC_NIS_TRSCMP | SDHC_NIS_BLKGAP);
1100 break;
1101 }
1102 }
1103
1104 static void
1105 sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
1106 {
1107 SDHCIState *s = (SDHCIState *)opaque;
1108 unsigned shift = 8 * (offset & 0x3);
1109 uint32_t mask = ~(((1ULL << (size * 8)) - 1) << shift);
1110 uint32_t value = val;
1111 value <<= shift;
1112
1113 switch (offset & ~0x3) {
1114 case SDHC_SYSAD:
1115 s->sdmasysad = (s->sdmasysad & mask) | value;
1116 MASKED_WRITE(s->sdmasysad, mask, value);
1117 /* Writing to last byte of sdmasysad might trigger transfer */
1118 if (!(mask & 0xFF000000) && TRANSFERRING_DATA(s->prnsts) && s->blkcnt &&
1119 s->blksize && SDHC_DMA_TYPE(s->hostctl1) == SDHC_CTRL_SDMA) {
1120 if (s->trnmod & SDHC_TRNS_MULTI) {
1121 sdhci_sdma_transfer_multi_blocks(s);
1122 } else {
1123 sdhci_sdma_transfer_single_block(s);
1124 }
1125 }
1126 break;
1127 case SDHC_BLKSIZE:
1128 if (!TRANSFERRING_DATA(s->prnsts)) {
1129 MASKED_WRITE(s->blksize, mask, value);
1130 MASKED_WRITE(s->blkcnt, mask >> 16, value >> 16);
1131 }
1132
1133 /* Limit block size to the maximum buffer size */
1134 if (extract32(s->blksize, 0, 12) > s->buf_maxsz) {
1135 qemu_log_mask(LOG_GUEST_ERROR, "%s: Size 0x%x is larger than " \
1136 "the maximum buffer 0x%x", __func__, s->blksize,
1137 s->buf_maxsz);
1138
1139 s->blksize = deposit32(s->blksize, 0, 12, s->buf_maxsz);
1140 }
1141
1142 break;
1143 case SDHC_ARGUMENT:
1144 MASKED_WRITE(s->argument, mask, value);
1145 break;
1146 case SDHC_TRNMOD:
1147 /* DMA can be enabled only if it is supported as indicated by
1148 * capabilities register */
1149 if (!(s->capareg & R_SDHC_CAPAB_SDMA_MASK)) {
1150 value &= ~SDHC_TRNS_DMA;
1151 }
1152 MASKED_WRITE(s->trnmod, mask, value & SDHC_TRNMOD_MASK);
1153 MASKED_WRITE(s->cmdreg, mask >> 16, value >> 16);
1154
1155 /* Writing to the upper byte of CMDREG triggers SD command generation */
1156 if ((mask & 0xFF000000) || !sdhci_can_issue_command(s)) {
1157 break;
1158 }
1159
1160 sdhci_send_command(s);
1161 break;
1162 case SDHC_BDATA:
1163 if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) {
1164 sdhci_write_dataport(s, value >> shift, size);
1165 }
1166 break;
1167 case SDHC_HOSTCTL:
1168 if (!(mask & 0xFF0000)) {
1169 sdhci_blkgap_write(s, value >> 16);
1170 }
1171 MASKED_WRITE(s->hostctl1, mask, value);
1172 MASKED_WRITE(s->pwrcon, mask >> 8, value >> 8);
1173 MASKED_WRITE(s->wakcon, mask >> 24, value >> 24);
1174 if (!(s->prnsts & SDHC_CARD_PRESENT) || ((s->pwrcon >> 1) & 0x7) < 5 ||
1175 !(s->capareg & (1 << (31 - ((s->pwrcon >> 1) & 0x7))))) {
1176 s->pwrcon &= ~SDHC_POWER_ON;
1177 }
1178 break;
1179 case SDHC_CLKCON:
1180 if (!(mask & 0xFF000000)) {
1181 sdhci_reset_write(s, value >> 24);
1182 }
1183 MASKED_WRITE(s->clkcon, mask, value);
1184 MASKED_WRITE(s->timeoutcon, mask >> 16, value >> 16);
1185 if (s->clkcon & SDHC_CLOCK_INT_EN) {
1186 s->clkcon |= SDHC_CLOCK_INT_STABLE;
1187 } else {
1188 s->clkcon &= ~SDHC_CLOCK_INT_STABLE;
1189 }
1190 break;
1191 case SDHC_NORINTSTS:
1192 if (s->norintstsen & SDHC_NISEN_CARDINT) {
1193 value &= ~SDHC_NIS_CARDINT;
1194 }
1195 s->norintsts &= mask | ~value;
1196 s->errintsts &= (mask >> 16) | ~(value >> 16);
1197 if (s->errintsts) {
1198 s->norintsts |= SDHC_NIS_ERR;
1199 } else {
1200 s->norintsts &= ~SDHC_NIS_ERR;
1201 }
1202 sdhci_update_irq(s);
1203 break;
1204 case SDHC_NORINTSTSEN:
1205 MASKED_WRITE(s->norintstsen, mask, value);
1206 MASKED_WRITE(s->errintstsen, mask >> 16, value >> 16);
1207 s->norintsts &= s->norintstsen;
1208 s->errintsts &= s->errintstsen;
1209 if (s->errintsts) {
1210 s->norintsts |= SDHC_NIS_ERR;
1211 } else {
1212 s->norintsts &= ~SDHC_NIS_ERR;
1213 }
1214 /* Quirk for Raspberry Pi: pending card insert interrupt
1215 * appears when first enabled after power on */
1216 if ((s->norintstsen & SDHC_NISEN_INSERT) && s->pending_insert_state) {
1217 assert(s->pending_insert_quirk);
1218 s->norintsts |= SDHC_NIS_INSERT;
1219 s->pending_insert_state = false;
1220 }
1221 sdhci_update_irq(s);
1222 break;
1223 case SDHC_NORINTSIGEN:
1224 MASKED_WRITE(s->norintsigen, mask, value);
1225 MASKED_WRITE(s->errintsigen, mask >> 16, value >> 16);
1226 sdhci_update_irq(s);
1227 break;
1228 case SDHC_ADMAERR:
1229 MASKED_WRITE(s->admaerr, mask, value);
1230 break;
1231 case SDHC_ADMASYSADDR:
1232 s->admasysaddr = (s->admasysaddr & (0xFFFFFFFF00000000ULL |
1233 (uint64_t)mask)) | (uint64_t)value;
1234 break;
1235 case SDHC_ADMASYSADDR + 4:
1236 s->admasysaddr = (s->admasysaddr & (0x00000000FFFFFFFFULL |
1237 ((uint64_t)mask << 32))) | ((uint64_t)value << 32);
1238 break;
1239 case SDHC_FEAER:
1240 s->acmd12errsts |= value;
1241 s->errintsts |= (value >> 16) & s->errintstsen;
1242 if (s->acmd12errsts) {
1243 s->errintsts |= SDHC_EIS_CMD12ERR;
1244 }
1245 if (s->errintsts) {
1246 s->norintsts |= SDHC_NIS_ERR;
1247 }
1248 sdhci_update_irq(s);
1249 break;
1250 case SDHC_ACMD12ERRSTS:
1251 MASKED_WRITE(s->acmd12errsts, mask, value & UINT16_MAX);
1252 if (s->uhs_mode >= UHS_I) {
1253 MASKED_WRITE(s->hostctl2, mask >> 16, value >> 16);
1254
1255 if (FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, V18_ENA)) {
1256 sdbus_set_voltage(&s->sdbus, SD_VOLTAGE_1_8V);
1257 } else {
1258 sdbus_set_voltage(&s->sdbus, SD_VOLTAGE_3_3V);
1259 }
1260 }
1261 break;
1262
1263 case SDHC_CAPAB:
1264 case SDHC_CAPAB + 4:
1265 case SDHC_MAXCURR:
1266 case SDHC_MAXCURR + 4:
1267 qemu_log_mask(LOG_GUEST_ERROR, "SDHC wr_%ub @0x%02" HWADDR_PRIx
1268 " <- 0x%08x read-only\n", size, offset, value >> shift);
1269 break;
1270
1271 default:
1272 qemu_log_mask(LOG_UNIMP, "SDHC wr_%ub @0x%02" HWADDR_PRIx " <- 0x%08x "
1273 "not implemented\n", size, offset, value >> shift);
1274 break;
1275 }
1276 trace_sdhci_access("wr", size << 3, offset, "<-",
1277 value >> shift, value >> shift);
1278 }
1279
1280 static const MemoryRegionOps sdhci_mmio_ops = {
1281 .read = sdhci_read,
1282 .write = sdhci_write,
1283 .valid = {
1284 .min_access_size = 1,
1285 .max_access_size = 4,
1286 .unaligned = false
1287 },
1288 .endianness = DEVICE_LITTLE_ENDIAN,
1289 };
1290
1291 static void sdhci_init_readonly_registers(SDHCIState *s, Error **errp)
1292 {
1293 Error *local_err = NULL;
1294
1295 switch (s->sd_spec_version) {
1296 case 2 ... 3:
1297 break;
1298 default:
1299 error_setg(errp, "Only Spec v2/v3 are supported");
1300 return;
1301 }
1302 s->version = (SDHC_HCVER_VENDOR << 8) | (s->sd_spec_version - 1);
1303
1304 sdhci_check_capareg(s, &local_err);
1305 if (local_err) {
1306 error_propagate(errp, local_err);
1307 return;
1308 }
1309 }
1310
1311 /* --- qdev common --- */
1312
1313 void sdhci_initfn(SDHCIState *s)
1314 {
1315 qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
1316 TYPE_SDHCI_BUS, DEVICE(s), "sd-bus");
1317
1318 s->insert_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_raise_insertion_irq, s);
1319 s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_data_transfer, s);
1320
1321 s->io_ops = &sdhci_mmio_ops;
1322 }
1323
1324 void sdhci_uninitfn(SDHCIState *s)
1325 {
1326 timer_del(s->insert_timer);
1327 timer_free(s->insert_timer);
1328 timer_del(s->transfer_timer);
1329 timer_free(s->transfer_timer);
1330
1331 g_free(s->fifo_buffer);
1332 s->fifo_buffer = NULL;
1333 }
1334
1335 void sdhci_common_realize(SDHCIState *s, Error **errp)
1336 {
1337 Error *local_err = NULL;
1338
1339 sdhci_init_readonly_registers(s, &local_err);
1340 if (local_err) {
1341 error_propagate(errp, local_err);
1342 return;
1343 }
1344 s->buf_maxsz = sdhci_get_fifolen(s);
1345 s->fifo_buffer = g_malloc0(s->buf_maxsz);
1346
1347 memory_region_init_io(&s->iomem, OBJECT(s), s->io_ops, s, "sdhci",
1348 SDHC_REGISTERS_MAP_SIZE);
1349 }
1350
1351 void sdhci_common_unrealize(SDHCIState *s, Error **errp)
1352 {
1353 /* This function is expected to be called only once for each class:
1354 * - SysBus: via DeviceClass->unrealize(),
1355 * - PCI: via PCIDeviceClass->exit().
1356 * However to avoid double-free and/or use-after-free we still nullify
1357 * this variable (better safe than sorry!). */
1358 g_free(s->fifo_buffer);
1359 s->fifo_buffer = NULL;
1360 }
1361
1362 static bool sdhci_pending_insert_vmstate_needed(void *opaque)
1363 {
1364 SDHCIState *s = opaque;
1365
1366 return s->pending_insert_state;
1367 }
1368
1369 static const VMStateDescription sdhci_pending_insert_vmstate = {
1370 .name = "sdhci/pending-insert",
1371 .version_id = 1,
1372 .minimum_version_id = 1,
1373 .needed = sdhci_pending_insert_vmstate_needed,
1374 .fields = (VMStateField[]) {
1375 VMSTATE_BOOL(pending_insert_state, SDHCIState),
1376 VMSTATE_END_OF_LIST()
1377 },
1378 };
1379
1380 const VMStateDescription sdhci_vmstate = {
1381 .name = "sdhci",
1382 .version_id = 1,
1383 .minimum_version_id = 1,
1384 .fields = (VMStateField[]) {
1385 VMSTATE_UINT32(sdmasysad, SDHCIState),
1386 VMSTATE_UINT16(blksize, SDHCIState),
1387 VMSTATE_UINT16(blkcnt, SDHCIState),
1388 VMSTATE_UINT32(argument, SDHCIState),
1389 VMSTATE_UINT16(trnmod, SDHCIState),
1390 VMSTATE_UINT16(cmdreg, SDHCIState),
1391 VMSTATE_UINT32_ARRAY(rspreg, SDHCIState, 4),
1392 VMSTATE_UINT32(prnsts, SDHCIState),
1393 VMSTATE_UINT8(hostctl1, SDHCIState),
1394 VMSTATE_UINT8(pwrcon, SDHCIState),
1395 VMSTATE_UINT8(blkgap, SDHCIState),
1396 VMSTATE_UINT8(wakcon, SDHCIState),
1397 VMSTATE_UINT16(clkcon, SDHCIState),
1398 VMSTATE_UINT8(timeoutcon, SDHCIState),
1399 VMSTATE_UINT8(admaerr, SDHCIState),
1400 VMSTATE_UINT16(norintsts, SDHCIState),
1401 VMSTATE_UINT16(errintsts, SDHCIState),
1402 VMSTATE_UINT16(norintstsen, SDHCIState),
1403 VMSTATE_UINT16(errintstsen, SDHCIState),
1404 VMSTATE_UINT16(norintsigen, SDHCIState),
1405 VMSTATE_UINT16(errintsigen, SDHCIState),
1406 VMSTATE_UINT16(acmd12errsts, SDHCIState),
1407 VMSTATE_UINT16(data_count, SDHCIState),
1408 VMSTATE_UINT64(admasysaddr, SDHCIState),
1409 VMSTATE_UINT8(stopped_state, SDHCIState),
1410 VMSTATE_VBUFFER_UINT32(fifo_buffer, SDHCIState, 1, NULL, buf_maxsz),
1411 VMSTATE_TIMER_PTR(insert_timer, SDHCIState),
1412 VMSTATE_TIMER_PTR(transfer_timer, SDHCIState),
1413 VMSTATE_END_OF_LIST()
1414 },
1415 .subsections = (const VMStateDescription*[]) {
1416 &sdhci_pending_insert_vmstate,
1417 NULL
1418 },
1419 };
1420
1421 void sdhci_common_class_init(ObjectClass *klass, void *data)
1422 {
1423 DeviceClass *dc = DEVICE_CLASS(klass);
1424
1425 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
1426 dc->vmsd = &sdhci_vmstate;
1427 dc->reset = sdhci_poweron_reset;
1428 }
1429
1430 /* --- qdev SysBus --- */
1431
1432 static Property sdhci_sysbus_properties[] = {
1433 DEFINE_SDHCI_COMMON_PROPERTIES(SDHCIState),
1434 DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, pending_insert_quirk,
1435 false),
1436 DEFINE_PROP_LINK("dma", SDHCIState,
1437 dma_mr, TYPE_MEMORY_REGION, MemoryRegion *),
1438 DEFINE_PROP_END_OF_LIST(),
1439 };
1440
1441 static void sdhci_sysbus_init(Object *obj)
1442 {
1443 SDHCIState *s = SYSBUS_SDHCI(obj);
1444
1445 sdhci_initfn(s);
1446 }
1447
1448 static void sdhci_sysbus_finalize(Object *obj)
1449 {
1450 SDHCIState *s = SYSBUS_SDHCI(obj);
1451
1452 if (s->dma_mr) {
1453 object_unparent(OBJECT(s->dma_mr));
1454 }
1455
1456 sdhci_uninitfn(s);
1457 }
1458
1459 static void sdhci_sysbus_realize(DeviceState *dev, Error ** errp)
1460 {
1461 SDHCIState *s = SYSBUS_SDHCI(dev);
1462 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1463 Error *local_err = NULL;
1464
1465 sdhci_common_realize(s, &local_err);
1466 if (local_err) {
1467 error_propagate(errp, local_err);
1468 return;
1469 }
1470
1471 if (s->dma_mr) {
1472 s->dma_as = &s->sysbus_dma_as;
1473 address_space_init(s->dma_as, s->dma_mr, "sdhci-dma");
1474 } else {
1475 /* use system_memory() if property "dma" not set */
1476 s->dma_as = &address_space_memory;
1477 }
1478
1479 sysbus_init_irq(sbd, &s->irq);
1480
1481 sysbus_init_mmio(sbd, &s->iomem);
1482 }
1483
1484 static void sdhci_sysbus_unrealize(DeviceState *dev, Error **errp)
1485 {
1486 SDHCIState *s = SYSBUS_SDHCI(dev);
1487
1488 sdhci_common_unrealize(s, &error_abort);
1489
1490 if (s->dma_mr) {
1491 address_space_destroy(s->dma_as);
1492 }
1493 }
1494
1495 static void sdhci_sysbus_class_init(ObjectClass *klass, void *data)
1496 {
1497 DeviceClass *dc = DEVICE_CLASS(klass);
1498
1499 dc->props = sdhci_sysbus_properties;
1500 dc->realize = sdhci_sysbus_realize;
1501 dc->unrealize = sdhci_sysbus_unrealize;
1502
1503 sdhci_common_class_init(klass, data);
1504 }
1505
1506 static const TypeInfo sdhci_sysbus_info = {
1507 .name = TYPE_SYSBUS_SDHCI,
1508 .parent = TYPE_SYS_BUS_DEVICE,
1509 .instance_size = sizeof(SDHCIState),
1510 .instance_init = sdhci_sysbus_init,
1511 .instance_finalize = sdhci_sysbus_finalize,
1512 .class_init = sdhci_sysbus_class_init,
1513 };
1514
1515 /* --- qdev bus master --- */
1516
1517 static void sdhci_bus_class_init(ObjectClass *klass, void *data)
1518 {
1519 SDBusClass *sbc = SD_BUS_CLASS(klass);
1520
1521 sbc->set_inserted = sdhci_set_inserted;
1522 sbc->set_readonly = sdhci_set_readonly;
1523 }
1524
1525 static const TypeInfo sdhci_bus_info = {
1526 .name = TYPE_SDHCI_BUS,
1527 .parent = TYPE_SD_BUS,
1528 .instance_size = sizeof(SDBus),
1529 .class_init = sdhci_bus_class_init,
1530 };
1531
1532 static uint64_t usdhc_read(void *opaque, hwaddr offset, unsigned size)
1533 {
1534 SDHCIState *s = SYSBUS_SDHCI(opaque);
1535 uint32_t ret;
1536 uint16_t hostctl1;
1537
1538 switch (offset) {
1539 default:
1540 return sdhci_read(opaque, offset, size);
1541
1542 case SDHC_HOSTCTL:
1543 /*
1544 * For a detailed explanation on the following bit
1545 * manipulation code see comments in a similar part of
1546 * usdhc_write()
1547 */
1548 hostctl1 = SDHC_DMA_TYPE(s->hostctl1) << (8 - 3);
1549
1550 if (s->hostctl1 & SDHC_CTRL_8BITBUS) {
1551 hostctl1 |= ESDHC_CTRL_8BITBUS;
1552 }
1553
1554 if (s->hostctl1 & SDHC_CTRL_4BITBUS) {
1555 hostctl1 |= ESDHC_CTRL_4BITBUS;
1556 }
1557
1558 ret = hostctl1;
1559 ret |= (uint32_t)s->blkgap << 16;
1560 ret |= (uint32_t)s->wakcon << 24;
1561
1562 break;
1563
1564 case SDHC_PRNSTS:
1565 /* Add SDSTB (SD Clock Stable) bit to PRNSTS */
1566 ret = sdhci_read(opaque, offset, size) & ~ESDHC_PRNSTS_SDSTB;
1567 if (s->clkcon & SDHC_CLOCK_INT_STABLE) {
1568 ret |= ESDHC_PRNSTS_SDSTB;
1569 }
1570 break;
1571
1572 case ESDHC_DLL_CTRL:
1573 case ESDHC_TUNE_CTRL_STATUS:
1574 case ESDHC_UNDOCUMENTED_REG27:
1575 case ESDHC_TUNING_CTRL:
1576 case ESDHC_VENDOR_SPEC:
1577 case ESDHC_MIX_CTRL:
1578 case ESDHC_WTMK_LVL:
1579 ret = 0;
1580 break;
1581 }
1582
1583 return ret;
1584 }
1585
1586 static void
1587 usdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
1588 {
1589 SDHCIState *s = SYSBUS_SDHCI(opaque);
1590 uint8_t hostctl1;
1591 uint32_t value = (uint32_t)val;
1592
1593 switch (offset) {
1594 case ESDHC_DLL_CTRL:
1595 case ESDHC_TUNE_CTRL_STATUS:
1596 case ESDHC_UNDOCUMENTED_REG27:
1597 case ESDHC_TUNING_CTRL:
1598 case ESDHC_WTMK_LVL:
1599 case ESDHC_VENDOR_SPEC:
1600 break;
1601
1602 case SDHC_HOSTCTL:
1603 /*
1604 * Here's What ESDHCI has at offset 0x28 (SDHC_HOSTCTL)
1605 *
1606 * 7 6 5 4 3 2 1 0
1607 * |-----------+--------+--------+-----------+----------+---------|
1608 * | Card | Card | Endian | DATA3 | Data | Led |
1609 * | Detect | Detect | Mode | as Card | Transfer | Control |
1610 * | Signal | Test | | Detection | Width | |
1611 * | Selection | Level | | Pin | | |
1612 * |-----------+--------+--------+-----------+----------+---------|
1613 *
1614 * and 0x29
1615 *
1616 * 15 10 9 8
1617 * |----------+------|
1618 * | Reserved | DMA |
1619 * | | Sel. |
1620 * | | |
1621 * |----------+------|
1622 *
1623 * and here's what SDCHI spec expects those offsets to be:
1624 *
1625 * 0x28 (Host Control Register)
1626 *
1627 * 7 6 5 4 3 2 1 0
1628 * |--------+--------+----------+------+--------+----------+---------|
1629 * | Card | Card | Extended | DMA | High | Data | LED |
1630 * | Detect | Detect | Data | Sel. | Speed | Transfer | Control |
1631 * | Signal | Test | Transfer | | Enable | Width | |
1632 * | Sel. | Level | Width | | | | |
1633 * |--------+--------+----------+------+--------+----------+---------|
1634 *
1635 * and 0x29 (Power Control Register)
1636 *
1637 * |----------------------------------|
1638 * | Power Control Register |
1639 * | |
1640 * | Description omitted, |
1641 * | since it has no analog in ESDHCI |
1642 * | |
1643 * |----------------------------------|
1644 *
1645 * Since offsets 0x2A and 0x2B should be compatible between
1646 * both IP specs we only need to reconcile least 16-bit of the
1647 * word we've been given.
1648 */
1649
1650 /*
1651 * First, save bits 7 6 and 0 since they are identical
1652 */
1653 hostctl1 = value & (SDHC_CTRL_LED |
1654 SDHC_CTRL_CDTEST_INS |
1655 SDHC_CTRL_CDTEST_EN);
1656 /*
1657 * Second, split "Data Transfer Width" from bits 2 and 1 in to
1658 * bits 5 and 1
1659 */
1660 if (value & ESDHC_CTRL_8BITBUS) {
1661 hostctl1 |= SDHC_CTRL_8BITBUS;
1662 }
1663
1664 if (value & ESDHC_CTRL_4BITBUS) {
1665 hostctl1 |= ESDHC_CTRL_4BITBUS;
1666 }
1667
1668 /*
1669 * Third, move DMA select from bits 9 and 8 to bits 4 and 3
1670 */
1671 hostctl1 |= SDHC_DMA_TYPE(value >> (8 - 3));
1672
1673 /*
1674 * Now place the corrected value into low 16-bit of the value
1675 * we are going to give standard SDHCI write function
1676 *
1677 * NOTE: This transformation should be the inverse of what can
1678 * be found in drivers/mmc/host/sdhci-esdhc-imx.c in Linux
1679 * kernel
1680 */
1681 value &= ~UINT16_MAX;
1682 value |= hostctl1;
1683 value |= (uint16_t)s->pwrcon << 8;
1684
1685 sdhci_write(opaque, offset, value, size);
1686 break;
1687
1688 case ESDHC_MIX_CTRL:
1689 /*
1690 * So, when SD/MMC stack in Linux tries to write to "Transfer
1691 * Mode Register", ESDHC i.MX quirk code will translate it
1692 * into a write to ESDHC_MIX_CTRL, so we do the opposite in
1693 * order to get where we started
1694 *
1695 * Note that Auto CMD23 Enable bit is located in a wrong place
1696 * on i.MX, but since it is not used by QEMU we do not care.
1697 *
1698 * We don't want to call sdhci_write(.., SDHC_TRNMOD, ...)
1699 * here becuase it will result in a call to
1700 * sdhci_send_command(s) which we don't want.
1701 *
1702 */
1703 s->trnmod = value & UINT16_MAX;
1704 break;
1705 case SDHC_TRNMOD:
1706 /*
1707 * Similar to above, but this time a write to "Command
1708 * Register" will be translated into a 4-byte write to
1709 * "Transfer Mode register" where lower 16-bit of value would
1710 * be set to zero. So what we do is fill those bits with
1711 * cached value from s->trnmod and let the SDHCI
1712 * infrastructure handle the rest
1713 */
1714 sdhci_write(opaque, offset, val | s->trnmod, size);
1715 break;
1716 case SDHC_BLKSIZE:
1717 /*
1718 * ESDHCI does not implement "Host SDMA Buffer Boundary", and
1719 * Linux driver will try to zero this field out which will
1720 * break the rest of SDHCI emulation.
1721 *
1722 * Linux defaults to maximum possible setting (512K boundary)
1723 * and it seems to be the only option that i.MX IP implements,
1724 * so we artificially set it to that value.
1725 */
1726 val |= 0x7 << 12;
1727 /* FALLTHROUGH */
1728 default:
1729 sdhci_write(opaque, offset, val, size);
1730 break;
1731 }
1732 }
1733
1734
1735 static const MemoryRegionOps usdhc_mmio_ops = {
1736 .read = usdhc_read,
1737 .write = usdhc_write,
1738 .valid = {
1739 .min_access_size = 1,
1740 .max_access_size = 4,
1741 .unaligned = false
1742 },
1743 .endianness = DEVICE_LITTLE_ENDIAN,
1744 };
1745
1746 static void imx_usdhc_init(Object *obj)
1747 {
1748 SDHCIState *s = SYSBUS_SDHCI(obj);
1749
1750 s->io_ops = &usdhc_mmio_ops;
1751 s->quirks = SDHCI_QUIRK_NO_BUSY_IRQ;
1752 }
1753
1754 static const TypeInfo imx_usdhc_info = {
1755 .name = TYPE_IMX_USDHC,
1756 .parent = TYPE_SYSBUS_SDHCI,
1757 .instance_init = imx_usdhc_init,
1758 };
1759
1760 static void sdhci_register_types(void)
1761 {
1762 type_register_static(&sdhci_sysbus_info);
1763 type_register_static(&sdhci_bus_info);
1764 type_register_static(&imx_usdhc_info);
1765 }
1766
1767 type_init(sdhci_register_types)