meson: convert hw/vfio
[qemu.git] / hw / sd / sdhci.c
1 /*
2 * SD Association Host Standard Specification v2.0 controller emulation
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * Mitsyanko Igor <i.mitsyanko@samsung.com>
6 * Peter A.G. Crosthwaite <peter.crosthwaite@petalogix.com>
7 *
8 * Based on MMC controller for Samsung S5PC1xx-based board emulation
9 * by Alexey Merkulov and Vladimir Monakhov.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
19 * See the GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, see <http://www.gnu.org/licenses/>.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "qemu/error-report.h"
28 #include "qapi/error.h"
29 #include "hw/irq.h"
30 #include "hw/qdev-properties.h"
31 #include "sysemu/dma.h"
32 #include "qemu/timer.h"
33 #include "qemu/bitops.h"
34 #include "hw/sd/sdhci.h"
35 #include "migration/vmstate.h"
36 #include "sdhci-internal.h"
37 #include "qemu/log.h"
38 #include "qemu/module.h"
39 #include "trace.h"
40
41 #define TYPE_SDHCI_BUS "sdhci-bus"
42 #define SDHCI_BUS(obj) OBJECT_CHECK(SDBus, (obj), TYPE_SDHCI_BUS)
43
44 #define MASKED_WRITE(reg, mask, val) (reg = (reg & (mask)) | (val))
45
46 static inline unsigned int sdhci_get_fifolen(SDHCIState *s)
47 {
48 return 1 << (9 + FIELD_EX32(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH));
49 }
50
51 /* return true on error */
52 static bool sdhci_check_capab_freq_range(SDHCIState *s, const char *desc,
53 uint8_t freq, Error **errp)
54 {
55 if (s->sd_spec_version >= 3) {
56 return false;
57 }
58 switch (freq) {
59 case 0:
60 case 10 ... 63:
61 break;
62 default:
63 error_setg(errp, "SD %s clock frequency can have value"
64 "in range 0-63 only", desc);
65 return true;
66 }
67 return false;
68 }
69
70 static void sdhci_check_capareg(SDHCIState *s, Error **errp)
71 {
72 uint64_t msk = s->capareg;
73 uint32_t val;
74 bool y;
75
76 switch (s->sd_spec_version) {
77 case 4:
78 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT_V4);
79 trace_sdhci_capareg("64-bit system bus (v4)", val);
80 msk = FIELD_DP64(msk, SDHC_CAPAB, BUS64BIT_V4, 0);
81
82 val = FIELD_EX64(s->capareg, SDHC_CAPAB, UHS_II);
83 trace_sdhci_capareg("UHS-II", val);
84 msk = FIELD_DP64(msk, SDHC_CAPAB, UHS_II, 0);
85
86 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA3);
87 trace_sdhci_capareg("ADMA3", val);
88 msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA3, 0);
89
90 /* fallthrough */
91 case 3:
92 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ASYNC_INT);
93 trace_sdhci_capareg("async interrupt", val);
94 msk = FIELD_DP64(msk, SDHC_CAPAB, ASYNC_INT, 0);
95
96 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SLOT_TYPE);
97 if (val) {
98 error_setg(errp, "slot-type not supported");
99 return;
100 }
101 trace_sdhci_capareg("slot type", val);
102 msk = FIELD_DP64(msk, SDHC_CAPAB, SLOT_TYPE, 0);
103
104 if (val != 2) {
105 val = FIELD_EX64(s->capareg, SDHC_CAPAB, EMBEDDED_8BIT);
106 trace_sdhci_capareg("8-bit bus", val);
107 }
108 msk = FIELD_DP64(msk, SDHC_CAPAB, EMBEDDED_8BIT, 0);
109
110 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS_SPEED);
111 trace_sdhci_capareg("bus speed mask", val);
112 msk = FIELD_DP64(msk, SDHC_CAPAB, BUS_SPEED, 0);
113
114 val = FIELD_EX64(s->capareg, SDHC_CAPAB, DRIVER_STRENGTH);
115 trace_sdhci_capareg("driver strength mask", val);
116 msk = FIELD_DP64(msk, SDHC_CAPAB, DRIVER_STRENGTH, 0);
117
118 val = FIELD_EX64(s->capareg, SDHC_CAPAB, TIMER_RETUNING);
119 trace_sdhci_capareg("timer re-tuning", val);
120 msk = FIELD_DP64(msk, SDHC_CAPAB, TIMER_RETUNING, 0);
121
122 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SDR50_TUNING);
123 trace_sdhci_capareg("use SDR50 tuning", val);
124 msk = FIELD_DP64(msk, SDHC_CAPAB, SDR50_TUNING, 0);
125
126 val = FIELD_EX64(s->capareg, SDHC_CAPAB, RETUNING_MODE);
127 trace_sdhci_capareg("re-tuning mode", val);
128 msk = FIELD_DP64(msk, SDHC_CAPAB, RETUNING_MODE, 0);
129
130 val = FIELD_EX64(s->capareg, SDHC_CAPAB, CLOCK_MULT);
131 trace_sdhci_capareg("clock multiplier", val);
132 msk = FIELD_DP64(msk, SDHC_CAPAB, CLOCK_MULT, 0);
133
134 /* fallthrough */
135 case 2: /* default version */
136 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA2);
137 trace_sdhci_capareg("ADMA2", val);
138 msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA2, 0);
139
140 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA1);
141 trace_sdhci_capareg("ADMA1", val);
142 msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA1, 0);
143
144 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT);
145 trace_sdhci_capareg("64-bit system bus (v3)", val);
146 msk = FIELD_DP64(msk, SDHC_CAPAB, BUS64BIT, 0);
147
148 /* fallthrough */
149 case 1:
150 y = FIELD_EX64(s->capareg, SDHC_CAPAB, TOUNIT);
151 msk = FIELD_DP64(msk, SDHC_CAPAB, TOUNIT, 0);
152
153 val = FIELD_EX64(s->capareg, SDHC_CAPAB, TOCLKFREQ);
154 trace_sdhci_capareg(y ? "timeout (MHz)" : "Timeout (KHz)", val);
155 if (sdhci_check_capab_freq_range(s, "timeout", val, errp)) {
156 return;
157 }
158 msk = FIELD_DP64(msk, SDHC_CAPAB, TOCLKFREQ, 0);
159
160 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BASECLKFREQ);
161 trace_sdhci_capareg(y ? "base (MHz)" : "Base (KHz)", val);
162 if (sdhci_check_capab_freq_range(s, "base", val, errp)) {
163 return;
164 }
165 msk = FIELD_DP64(msk, SDHC_CAPAB, BASECLKFREQ, 0);
166
167 val = FIELD_EX64(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH);
168 if (val >= 3) {
169 error_setg(errp, "block size can be 512, 1024 or 2048 only");
170 return;
171 }
172 trace_sdhci_capareg("max block length", sdhci_get_fifolen(s));
173 msk = FIELD_DP64(msk, SDHC_CAPAB, MAXBLOCKLENGTH, 0);
174
175 val = FIELD_EX64(s->capareg, SDHC_CAPAB, HIGHSPEED);
176 trace_sdhci_capareg("high speed", val);
177 msk = FIELD_DP64(msk, SDHC_CAPAB, HIGHSPEED, 0);
178
179 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SDMA);
180 trace_sdhci_capareg("SDMA", val);
181 msk = FIELD_DP64(msk, SDHC_CAPAB, SDMA, 0);
182
183 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SUSPRESUME);
184 trace_sdhci_capareg("suspend/resume", val);
185 msk = FIELD_DP64(msk, SDHC_CAPAB, SUSPRESUME, 0);
186
187 val = FIELD_EX64(s->capareg, SDHC_CAPAB, V33);
188 trace_sdhci_capareg("3.3v", val);
189 msk = FIELD_DP64(msk, SDHC_CAPAB, V33, 0);
190
191 val = FIELD_EX64(s->capareg, SDHC_CAPAB, V30);
192 trace_sdhci_capareg("3.0v", val);
193 msk = FIELD_DP64(msk, SDHC_CAPAB, V30, 0);
194
195 val = FIELD_EX64(s->capareg, SDHC_CAPAB, V18);
196 trace_sdhci_capareg("1.8v", val);
197 msk = FIELD_DP64(msk, SDHC_CAPAB, V18, 0);
198 break;
199
200 default:
201 error_setg(errp, "Unsupported spec version: %u", s->sd_spec_version);
202 }
203 if (msk) {
204 qemu_log_mask(LOG_UNIMP,
205 "SDHCI: unknown CAPAB mask: 0x%016" PRIx64 "\n", msk);
206 }
207 }
208
209 static uint8_t sdhci_slotint(SDHCIState *s)
210 {
211 return (s->norintsts & s->norintsigen) || (s->errintsts & s->errintsigen) ||
212 ((s->norintsts & SDHC_NIS_INSERT) && (s->wakcon & SDHC_WKUP_ON_INS)) ||
213 ((s->norintsts & SDHC_NIS_REMOVE) && (s->wakcon & SDHC_WKUP_ON_RMV));
214 }
215
216 static inline void sdhci_update_irq(SDHCIState *s)
217 {
218 qemu_set_irq(s->irq, sdhci_slotint(s));
219 }
220
221 static void sdhci_raise_insertion_irq(void *opaque)
222 {
223 SDHCIState *s = (SDHCIState *)opaque;
224
225 if (s->norintsts & SDHC_NIS_REMOVE) {
226 timer_mod(s->insert_timer,
227 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY);
228 } else {
229 s->prnsts = 0x1ff0000;
230 if (s->norintstsen & SDHC_NISEN_INSERT) {
231 s->norintsts |= SDHC_NIS_INSERT;
232 }
233 sdhci_update_irq(s);
234 }
235 }
236
237 static void sdhci_set_inserted(DeviceState *dev, bool level)
238 {
239 SDHCIState *s = (SDHCIState *)dev;
240
241 trace_sdhci_set_inserted(level ? "insert" : "eject");
242 if ((s->norintsts & SDHC_NIS_REMOVE) && level) {
243 /* Give target some time to notice card ejection */
244 timer_mod(s->insert_timer,
245 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY);
246 } else {
247 if (level) {
248 s->prnsts = 0x1ff0000;
249 if (s->norintstsen & SDHC_NISEN_INSERT) {
250 s->norintsts |= SDHC_NIS_INSERT;
251 }
252 } else {
253 s->prnsts = 0x1fa0000;
254 s->pwrcon &= ~SDHC_POWER_ON;
255 s->clkcon &= ~SDHC_CLOCK_SDCLK_EN;
256 if (s->norintstsen & SDHC_NISEN_REMOVE) {
257 s->norintsts |= SDHC_NIS_REMOVE;
258 }
259 }
260 sdhci_update_irq(s);
261 }
262 }
263
264 static void sdhci_set_readonly(DeviceState *dev, bool level)
265 {
266 SDHCIState *s = (SDHCIState *)dev;
267
268 if (level) {
269 s->prnsts &= ~SDHC_WRITE_PROTECT;
270 } else {
271 /* Write enabled */
272 s->prnsts |= SDHC_WRITE_PROTECT;
273 }
274 }
275
276 static void sdhci_reset(SDHCIState *s)
277 {
278 DeviceState *dev = DEVICE(s);
279
280 timer_del(s->insert_timer);
281 timer_del(s->transfer_timer);
282
283 /* Set all registers to 0. Capabilities/Version registers are not cleared
284 * and assumed to always preserve their value, given to them during
285 * initialization */
286 memset(&s->sdmasysad, 0, (uintptr_t)&s->capareg - (uintptr_t)&s->sdmasysad);
287
288 /* Reset other state based on current card insertion/readonly status */
289 sdhci_set_inserted(dev, sdbus_get_inserted(&s->sdbus));
290 sdhci_set_readonly(dev, sdbus_get_readonly(&s->sdbus));
291
292 s->data_count = 0;
293 s->stopped_state = sdhc_not_stopped;
294 s->pending_insert_state = false;
295 }
296
297 static void sdhci_poweron_reset(DeviceState *dev)
298 {
299 /* QOM (ie power-on) reset. This is identical to reset
300 * commanded via device register apart from handling of the
301 * 'pending insert on powerup' quirk.
302 */
303 SDHCIState *s = (SDHCIState *)dev;
304
305 sdhci_reset(s);
306
307 if (s->pending_insert_quirk) {
308 s->pending_insert_state = true;
309 }
310 }
311
312 static void sdhci_data_transfer(void *opaque);
313
314 static void sdhci_send_command(SDHCIState *s)
315 {
316 SDRequest request;
317 uint8_t response[16];
318 int rlen;
319
320 s->errintsts = 0;
321 s->acmd12errsts = 0;
322 request.cmd = s->cmdreg >> 8;
323 request.arg = s->argument;
324
325 trace_sdhci_send_command(request.cmd, request.arg);
326 rlen = sdbus_do_command(&s->sdbus, &request, response);
327
328 if (s->cmdreg & SDHC_CMD_RESPONSE) {
329 if (rlen == 4) {
330 s->rspreg[0] = ldl_be_p(response);
331 s->rspreg[1] = s->rspreg[2] = s->rspreg[3] = 0;
332 trace_sdhci_response4(s->rspreg[0]);
333 } else if (rlen == 16) {
334 s->rspreg[0] = ldl_be_p(&response[11]);
335 s->rspreg[1] = ldl_be_p(&response[7]);
336 s->rspreg[2] = ldl_be_p(&response[3]);
337 s->rspreg[3] = (response[0] << 16) | (response[1] << 8) |
338 response[2];
339 trace_sdhci_response16(s->rspreg[3], s->rspreg[2],
340 s->rspreg[1], s->rspreg[0]);
341 } else {
342 trace_sdhci_error("timeout waiting for command response");
343 if (s->errintstsen & SDHC_EISEN_CMDTIMEOUT) {
344 s->errintsts |= SDHC_EIS_CMDTIMEOUT;
345 s->norintsts |= SDHC_NIS_ERR;
346 }
347 }
348
349 if (!(s->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
350 (s->norintstsen & SDHC_NISEN_TRSCMP) &&
351 (s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY) {
352 s->norintsts |= SDHC_NIS_TRSCMP;
353 }
354 }
355
356 if (s->norintstsen & SDHC_NISEN_CMDCMP) {
357 s->norintsts |= SDHC_NIS_CMDCMP;
358 }
359
360 sdhci_update_irq(s);
361
362 if (s->blksize && (s->cmdreg & SDHC_CMD_DATA_PRESENT)) {
363 s->data_count = 0;
364 sdhci_data_transfer(s);
365 }
366 }
367
368 static void sdhci_end_transfer(SDHCIState *s)
369 {
370 /* Automatically send CMD12 to stop transfer if AutoCMD12 enabled */
371 if ((s->trnmod & SDHC_TRNS_ACMD12) != 0) {
372 SDRequest request;
373 uint8_t response[16];
374
375 request.cmd = 0x0C;
376 request.arg = 0;
377 trace_sdhci_end_transfer(request.cmd, request.arg);
378 sdbus_do_command(&s->sdbus, &request, response);
379 /* Auto CMD12 response goes to the upper Response register */
380 s->rspreg[3] = ldl_be_p(response);
381 }
382
383 s->prnsts &= ~(SDHC_DOING_READ | SDHC_DOING_WRITE |
384 SDHC_DAT_LINE_ACTIVE | SDHC_DATA_INHIBIT |
385 SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE);
386
387 if (s->norintstsen & SDHC_NISEN_TRSCMP) {
388 s->norintsts |= SDHC_NIS_TRSCMP;
389 }
390
391 sdhci_update_irq(s);
392 }
393
394 /*
395 * Programmed i/o data transfer
396 */
397 #define BLOCK_SIZE_MASK (4 * KiB - 1)
398
399 /* Fill host controller's read buffer with BLKSIZE bytes of data from card */
400 static void sdhci_read_block_from_card(SDHCIState *s)
401 {
402 int index = 0;
403 uint8_t data;
404 const uint16_t blk_size = s->blksize & BLOCK_SIZE_MASK;
405
406 if ((s->trnmod & SDHC_TRNS_MULTI) &&
407 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) {
408 return;
409 }
410
411 for (index = 0; index < blk_size; index++) {
412 data = sdbus_read_data(&s->sdbus);
413 if (!FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, EXECUTE_TUNING)) {
414 /* Device is not in tuning */
415 s->fifo_buffer[index] = data;
416 }
417 }
418
419 if (FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, EXECUTE_TUNING)) {
420 /* Device is in tuning */
421 s->hostctl2 &= ~R_SDHC_HOSTCTL2_EXECUTE_TUNING_MASK;
422 s->hostctl2 |= R_SDHC_HOSTCTL2_SAMPLING_CLKSEL_MASK;
423 s->prnsts &= ~(SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ |
424 SDHC_DATA_INHIBIT);
425 goto read_done;
426 }
427
428 /* New data now available for READ through Buffer Port Register */
429 s->prnsts |= SDHC_DATA_AVAILABLE;
430 if (s->norintstsen & SDHC_NISEN_RBUFRDY) {
431 s->norintsts |= SDHC_NIS_RBUFRDY;
432 }
433
434 /* Clear DAT line active status if that was the last block */
435 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 ||
436 ((s->trnmod & SDHC_TRNS_MULTI) && s->blkcnt == 1)) {
437 s->prnsts &= ~SDHC_DAT_LINE_ACTIVE;
438 }
439
440 /* If stop at block gap request was set and it's not the last block of
441 * data - generate Block Event interrupt */
442 if (s->stopped_state == sdhc_gap_read && (s->trnmod & SDHC_TRNS_MULTI) &&
443 s->blkcnt != 1) {
444 s->prnsts &= ~SDHC_DAT_LINE_ACTIVE;
445 if (s->norintstsen & SDHC_EISEN_BLKGAP) {
446 s->norintsts |= SDHC_EIS_BLKGAP;
447 }
448 }
449
450 read_done:
451 sdhci_update_irq(s);
452 }
453
454 /* Read @size byte of data from host controller @s BUFFER DATA PORT register */
455 static uint32_t sdhci_read_dataport(SDHCIState *s, unsigned size)
456 {
457 uint32_t value = 0;
458 int i;
459
460 /* first check that a valid data exists in host controller input buffer */
461 if ((s->prnsts & SDHC_DATA_AVAILABLE) == 0) {
462 trace_sdhci_error("read from empty buffer");
463 return 0;
464 }
465
466 for (i = 0; i < size; i++) {
467 value |= s->fifo_buffer[s->data_count] << i * 8;
468 s->data_count++;
469 /* check if we've read all valid data (blksize bytes) from buffer */
470 if ((s->data_count) >= (s->blksize & BLOCK_SIZE_MASK)) {
471 trace_sdhci_read_dataport(s->data_count);
472 s->prnsts &= ~SDHC_DATA_AVAILABLE; /* no more data in a buffer */
473 s->data_count = 0; /* next buff read must start at position [0] */
474
475 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
476 s->blkcnt--;
477 }
478
479 /* if that was the last block of data */
480 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 ||
481 ((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) ||
482 /* stop at gap request */
483 (s->stopped_state == sdhc_gap_read &&
484 !(s->prnsts & SDHC_DAT_LINE_ACTIVE))) {
485 sdhci_end_transfer(s);
486 } else { /* if there are more data, read next block from card */
487 sdhci_read_block_from_card(s);
488 }
489 break;
490 }
491 }
492
493 return value;
494 }
495
496 /* Write data from host controller FIFO to card */
497 static void sdhci_write_block_to_card(SDHCIState *s)
498 {
499 int index = 0;
500
501 if (s->prnsts & SDHC_SPACE_AVAILABLE) {
502 if (s->norintstsen & SDHC_NISEN_WBUFRDY) {
503 s->norintsts |= SDHC_NIS_WBUFRDY;
504 }
505 sdhci_update_irq(s);
506 return;
507 }
508
509 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
510 if (s->blkcnt == 0) {
511 return;
512 } else {
513 s->blkcnt--;
514 }
515 }
516
517 for (index = 0; index < (s->blksize & BLOCK_SIZE_MASK); index++) {
518 sdbus_write_data(&s->sdbus, s->fifo_buffer[index]);
519 }
520
521 /* Next data can be written through BUFFER DATORT register */
522 s->prnsts |= SDHC_SPACE_AVAILABLE;
523
524 /* Finish transfer if that was the last block of data */
525 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 ||
526 ((s->trnmod & SDHC_TRNS_MULTI) &&
527 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0))) {
528 sdhci_end_transfer(s);
529 } else if (s->norintstsen & SDHC_NISEN_WBUFRDY) {
530 s->norintsts |= SDHC_NIS_WBUFRDY;
531 }
532
533 /* Generate Block Gap Event if requested and if not the last block */
534 if (s->stopped_state == sdhc_gap_write && (s->trnmod & SDHC_TRNS_MULTI) &&
535 s->blkcnt > 0) {
536 s->prnsts &= ~SDHC_DOING_WRITE;
537 if (s->norintstsen & SDHC_EISEN_BLKGAP) {
538 s->norintsts |= SDHC_EIS_BLKGAP;
539 }
540 sdhci_end_transfer(s);
541 }
542
543 sdhci_update_irq(s);
544 }
545
546 /* Write @size bytes of @value data to host controller @s Buffer Data Port
547 * register */
548 static void sdhci_write_dataport(SDHCIState *s, uint32_t value, unsigned size)
549 {
550 unsigned i;
551
552 /* Check that there is free space left in a buffer */
553 if (!(s->prnsts & SDHC_SPACE_AVAILABLE)) {
554 trace_sdhci_error("Can't write to data buffer: buffer full");
555 return;
556 }
557
558 for (i = 0; i < size; i++) {
559 s->fifo_buffer[s->data_count] = value & 0xFF;
560 s->data_count++;
561 value >>= 8;
562 if (s->data_count >= (s->blksize & BLOCK_SIZE_MASK)) {
563 trace_sdhci_write_dataport(s->data_count);
564 s->data_count = 0;
565 s->prnsts &= ~SDHC_SPACE_AVAILABLE;
566 if (s->prnsts & SDHC_DOING_WRITE) {
567 sdhci_write_block_to_card(s);
568 }
569 }
570 }
571 }
572
573 /*
574 * Single DMA data transfer
575 */
576
577 /* Multi block SDMA transfer */
578 static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s)
579 {
580 bool page_aligned = false;
581 unsigned int n, begin;
582 const uint16_t block_size = s->blksize & BLOCK_SIZE_MASK;
583 uint32_t boundary_chk = 1 << (((s->blksize & ~BLOCK_SIZE_MASK) >> 12) + 12);
584 uint32_t boundary_count = boundary_chk - (s->sdmasysad % boundary_chk);
585
586 if (!(s->trnmod & SDHC_TRNS_BLK_CNT_EN) || !s->blkcnt) {
587 qemu_log_mask(LOG_UNIMP, "infinite transfer is not supported\n");
588 return;
589 }
590
591 /* XXX: Some sd/mmc drivers (for example, u-boot-slp) do not account for
592 * possible stop at page boundary if initial address is not page aligned,
593 * allow them to work properly */
594 if ((s->sdmasysad % boundary_chk) == 0) {
595 page_aligned = true;
596 }
597
598 if (s->trnmod & SDHC_TRNS_READ) {
599 s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT |
600 SDHC_DAT_LINE_ACTIVE;
601 while (s->blkcnt) {
602 if (s->data_count == 0) {
603 for (n = 0; n < block_size; n++) {
604 s->fifo_buffer[n] = sdbus_read_data(&s->sdbus);
605 }
606 }
607 begin = s->data_count;
608 if (((boundary_count + begin) < block_size) && page_aligned) {
609 s->data_count = boundary_count + begin;
610 boundary_count = 0;
611 } else {
612 s->data_count = block_size;
613 boundary_count -= block_size - begin;
614 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
615 s->blkcnt--;
616 }
617 }
618 dma_memory_write(s->dma_as, s->sdmasysad,
619 &s->fifo_buffer[begin], s->data_count - begin);
620 s->sdmasysad += s->data_count - begin;
621 if (s->data_count == block_size) {
622 s->data_count = 0;
623 }
624 if (page_aligned && boundary_count == 0) {
625 break;
626 }
627 }
628 } else {
629 s->prnsts |= SDHC_DOING_WRITE | SDHC_DATA_INHIBIT |
630 SDHC_DAT_LINE_ACTIVE;
631 while (s->blkcnt) {
632 begin = s->data_count;
633 if (((boundary_count + begin) < block_size) && page_aligned) {
634 s->data_count = boundary_count + begin;
635 boundary_count = 0;
636 } else {
637 s->data_count = block_size;
638 boundary_count -= block_size - begin;
639 }
640 dma_memory_read(s->dma_as, s->sdmasysad,
641 &s->fifo_buffer[begin], s->data_count - begin);
642 s->sdmasysad += s->data_count - begin;
643 if (s->data_count == block_size) {
644 for (n = 0; n < block_size; n++) {
645 sdbus_write_data(&s->sdbus, s->fifo_buffer[n]);
646 }
647 s->data_count = 0;
648 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
649 s->blkcnt--;
650 }
651 }
652 if (page_aligned && boundary_count == 0) {
653 break;
654 }
655 }
656 }
657
658 if (s->blkcnt == 0) {
659 sdhci_end_transfer(s);
660 } else {
661 if (s->norintstsen & SDHC_NISEN_DMA) {
662 s->norintsts |= SDHC_NIS_DMA;
663 }
664 sdhci_update_irq(s);
665 }
666 }
667
668 /* single block SDMA transfer */
669 static void sdhci_sdma_transfer_single_block(SDHCIState *s)
670 {
671 int n;
672 uint32_t datacnt = s->blksize & BLOCK_SIZE_MASK;
673
674 if (s->trnmod & SDHC_TRNS_READ) {
675 for (n = 0; n < datacnt; n++) {
676 s->fifo_buffer[n] = sdbus_read_data(&s->sdbus);
677 }
678 dma_memory_write(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt);
679 } else {
680 dma_memory_read(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt);
681 for (n = 0; n < datacnt; n++) {
682 sdbus_write_data(&s->sdbus, s->fifo_buffer[n]);
683 }
684 }
685 s->blkcnt--;
686
687 sdhci_end_transfer(s);
688 }
689
690 typedef struct ADMADescr {
691 hwaddr addr;
692 uint16_t length;
693 uint8_t attr;
694 uint8_t incr;
695 } ADMADescr;
696
697 static void get_adma_description(SDHCIState *s, ADMADescr *dscr)
698 {
699 uint32_t adma1 = 0;
700 uint64_t adma2 = 0;
701 hwaddr entry_addr = (hwaddr)s->admasysaddr;
702 switch (SDHC_DMA_TYPE(s->hostctl1)) {
703 case SDHC_CTRL_ADMA2_32:
704 dma_memory_read(s->dma_as, entry_addr, &adma2, sizeof(adma2));
705 adma2 = le64_to_cpu(adma2);
706 /* The spec does not specify endianness of descriptor table.
707 * We currently assume that it is LE.
708 */
709 dscr->addr = (hwaddr)extract64(adma2, 32, 32) & ~0x3ull;
710 dscr->length = (uint16_t)extract64(adma2, 16, 16);
711 dscr->attr = (uint8_t)extract64(adma2, 0, 7);
712 dscr->incr = 8;
713 break;
714 case SDHC_CTRL_ADMA1_32:
715 dma_memory_read(s->dma_as, entry_addr, &adma1, sizeof(adma1));
716 adma1 = le32_to_cpu(adma1);
717 dscr->addr = (hwaddr)(adma1 & 0xFFFFF000);
718 dscr->attr = (uint8_t)extract32(adma1, 0, 7);
719 dscr->incr = 4;
720 if ((dscr->attr & SDHC_ADMA_ATTR_ACT_MASK) == SDHC_ADMA_ATTR_SET_LEN) {
721 dscr->length = (uint16_t)extract32(adma1, 12, 16);
722 } else {
723 dscr->length = 4 * KiB;
724 }
725 break;
726 case SDHC_CTRL_ADMA2_64:
727 dma_memory_read(s->dma_as, entry_addr, &dscr->attr, 1);
728 dma_memory_read(s->dma_as, entry_addr + 2, &dscr->length, 2);
729 dscr->length = le16_to_cpu(dscr->length);
730 dma_memory_read(s->dma_as, entry_addr + 4, &dscr->addr, 8);
731 dscr->addr = le64_to_cpu(dscr->addr);
732 dscr->attr &= (uint8_t) ~0xC0;
733 dscr->incr = 12;
734 break;
735 }
736 }
737
738 /* Advanced DMA data transfer */
739
740 static void sdhci_do_adma(SDHCIState *s)
741 {
742 unsigned int n, begin, length;
743 const uint16_t block_size = s->blksize & BLOCK_SIZE_MASK;
744 ADMADescr dscr = {};
745 int i;
746
747 for (i = 0; i < SDHC_ADMA_DESCS_PER_DELAY; ++i) {
748 s->admaerr &= ~SDHC_ADMAERR_LENGTH_MISMATCH;
749
750 get_adma_description(s, &dscr);
751 trace_sdhci_adma_loop(dscr.addr, dscr.length, dscr.attr);
752
753 if ((dscr.attr & SDHC_ADMA_ATTR_VALID) == 0) {
754 /* Indicate that error occurred in ST_FDS state */
755 s->admaerr &= ~SDHC_ADMAERR_STATE_MASK;
756 s->admaerr |= SDHC_ADMAERR_STATE_ST_FDS;
757
758 /* Generate ADMA error interrupt */
759 if (s->errintstsen & SDHC_EISEN_ADMAERR) {
760 s->errintsts |= SDHC_EIS_ADMAERR;
761 s->norintsts |= SDHC_NIS_ERR;
762 }
763
764 sdhci_update_irq(s);
765 return;
766 }
767
768 length = dscr.length ? dscr.length : 64 * KiB;
769
770 switch (dscr.attr & SDHC_ADMA_ATTR_ACT_MASK) {
771 case SDHC_ADMA_ATTR_ACT_TRAN: /* data transfer */
772
773 if (s->trnmod & SDHC_TRNS_READ) {
774 while (length) {
775 if (s->data_count == 0) {
776 for (n = 0; n < block_size; n++) {
777 s->fifo_buffer[n] = sdbus_read_data(&s->sdbus);
778 }
779 }
780 begin = s->data_count;
781 if ((length + begin) < block_size) {
782 s->data_count = length + begin;
783 length = 0;
784 } else {
785 s->data_count = block_size;
786 length -= block_size - begin;
787 }
788 dma_memory_write(s->dma_as, dscr.addr,
789 &s->fifo_buffer[begin],
790 s->data_count - begin);
791 dscr.addr += s->data_count - begin;
792 if (s->data_count == block_size) {
793 s->data_count = 0;
794 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
795 s->blkcnt--;
796 if (s->blkcnt == 0) {
797 break;
798 }
799 }
800 }
801 }
802 } else {
803 while (length) {
804 begin = s->data_count;
805 if ((length + begin) < block_size) {
806 s->data_count = length + begin;
807 length = 0;
808 } else {
809 s->data_count = block_size;
810 length -= block_size - begin;
811 }
812 dma_memory_read(s->dma_as, dscr.addr,
813 &s->fifo_buffer[begin],
814 s->data_count - begin);
815 dscr.addr += s->data_count - begin;
816 if (s->data_count == block_size) {
817 for (n = 0; n < block_size; n++) {
818 sdbus_write_data(&s->sdbus, s->fifo_buffer[n]);
819 }
820 s->data_count = 0;
821 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
822 s->blkcnt--;
823 if (s->blkcnt == 0) {
824 break;
825 }
826 }
827 }
828 }
829 }
830 s->admasysaddr += dscr.incr;
831 break;
832 case SDHC_ADMA_ATTR_ACT_LINK: /* link to next descriptor table */
833 s->admasysaddr = dscr.addr;
834 trace_sdhci_adma("link", s->admasysaddr);
835 break;
836 default:
837 s->admasysaddr += dscr.incr;
838 break;
839 }
840
841 if (dscr.attr & SDHC_ADMA_ATTR_INT) {
842 trace_sdhci_adma("interrupt", s->admasysaddr);
843 if (s->norintstsen & SDHC_NISEN_DMA) {
844 s->norintsts |= SDHC_NIS_DMA;
845 }
846
847 sdhci_update_irq(s);
848 }
849
850 /* ADMA transfer terminates if blkcnt == 0 or by END attribute */
851 if (((s->trnmod & SDHC_TRNS_BLK_CNT_EN) &&
852 (s->blkcnt == 0)) || (dscr.attr & SDHC_ADMA_ATTR_END)) {
853 trace_sdhci_adma_transfer_completed();
854 if (length || ((dscr.attr & SDHC_ADMA_ATTR_END) &&
855 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) &&
856 s->blkcnt != 0)) {
857 trace_sdhci_error("SD/MMC host ADMA length mismatch");
858 s->admaerr |= SDHC_ADMAERR_LENGTH_MISMATCH |
859 SDHC_ADMAERR_STATE_ST_TFR;
860 if (s->errintstsen & SDHC_EISEN_ADMAERR) {
861 trace_sdhci_error("Set ADMA error flag");
862 s->errintsts |= SDHC_EIS_ADMAERR;
863 s->norintsts |= SDHC_NIS_ERR;
864 }
865
866 sdhci_update_irq(s);
867 }
868 sdhci_end_transfer(s);
869 return;
870 }
871
872 }
873
874 /* we have unfinished business - reschedule to continue ADMA */
875 timer_mod(s->transfer_timer,
876 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_TRANSFER_DELAY);
877 }
878
879 /* Perform data transfer according to controller configuration */
880
881 static void sdhci_data_transfer(void *opaque)
882 {
883 SDHCIState *s = (SDHCIState *)opaque;
884
885 if (s->trnmod & SDHC_TRNS_DMA) {
886 switch (SDHC_DMA_TYPE(s->hostctl1)) {
887 case SDHC_CTRL_SDMA:
888 if ((s->blkcnt == 1) || !(s->trnmod & SDHC_TRNS_MULTI)) {
889 sdhci_sdma_transfer_single_block(s);
890 } else {
891 sdhci_sdma_transfer_multi_blocks(s);
892 }
893
894 break;
895 case SDHC_CTRL_ADMA1_32:
896 if (!(s->capareg & R_SDHC_CAPAB_ADMA1_MASK)) {
897 trace_sdhci_error("ADMA1 not supported");
898 break;
899 }
900
901 sdhci_do_adma(s);
902 break;
903 case SDHC_CTRL_ADMA2_32:
904 if (!(s->capareg & R_SDHC_CAPAB_ADMA2_MASK)) {
905 trace_sdhci_error("ADMA2 not supported");
906 break;
907 }
908
909 sdhci_do_adma(s);
910 break;
911 case SDHC_CTRL_ADMA2_64:
912 if (!(s->capareg & R_SDHC_CAPAB_ADMA2_MASK) ||
913 !(s->capareg & R_SDHC_CAPAB_BUS64BIT_MASK)) {
914 trace_sdhci_error("64 bit ADMA not supported");
915 break;
916 }
917
918 sdhci_do_adma(s);
919 break;
920 default:
921 trace_sdhci_error("Unsupported DMA type");
922 break;
923 }
924 } else {
925 if ((s->trnmod & SDHC_TRNS_READ) && sdbus_data_ready(&s->sdbus)) {
926 s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT |
927 SDHC_DAT_LINE_ACTIVE;
928 sdhci_read_block_from_card(s);
929 } else {
930 s->prnsts |= SDHC_DOING_WRITE | SDHC_DAT_LINE_ACTIVE |
931 SDHC_SPACE_AVAILABLE | SDHC_DATA_INHIBIT;
932 sdhci_write_block_to_card(s);
933 }
934 }
935 }
936
937 static bool sdhci_can_issue_command(SDHCIState *s)
938 {
939 if (!SDHC_CLOCK_IS_ON(s->clkcon) ||
940 (((s->prnsts & SDHC_DATA_INHIBIT) || s->stopped_state) &&
941 ((s->cmdreg & SDHC_CMD_DATA_PRESENT) ||
942 ((s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY &&
943 !(SDHC_COMMAND_TYPE(s->cmdreg) == SDHC_CMD_ABORT))))) {
944 return false;
945 }
946
947 return true;
948 }
949
950 /* The Buffer Data Port register must be accessed in sequential and
951 * continuous manner */
952 static inline bool
953 sdhci_buff_access_is_sequential(SDHCIState *s, unsigned byte_num)
954 {
955 if ((s->data_count & 0x3) != byte_num) {
956 trace_sdhci_error("Non-sequential access to Buffer Data Port register"
957 "is prohibited\n");
958 return false;
959 }
960 return true;
961 }
962
963 static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size)
964 {
965 SDHCIState *s = (SDHCIState *)opaque;
966 uint32_t ret = 0;
967
968 switch (offset & ~0x3) {
969 case SDHC_SYSAD:
970 ret = s->sdmasysad;
971 break;
972 case SDHC_BLKSIZE:
973 ret = s->blksize | (s->blkcnt << 16);
974 break;
975 case SDHC_ARGUMENT:
976 ret = s->argument;
977 break;
978 case SDHC_TRNMOD:
979 ret = s->trnmod | (s->cmdreg << 16);
980 break;
981 case SDHC_RSPREG0 ... SDHC_RSPREG3:
982 ret = s->rspreg[((offset & ~0x3) - SDHC_RSPREG0) >> 2];
983 break;
984 case SDHC_BDATA:
985 if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) {
986 ret = sdhci_read_dataport(s, size);
987 trace_sdhci_access("rd", size << 3, offset, "->", ret, ret);
988 return ret;
989 }
990 break;
991 case SDHC_PRNSTS:
992 ret = s->prnsts;
993 ret = FIELD_DP32(ret, SDHC_PRNSTS, DAT_LVL,
994 sdbus_get_dat_lines(&s->sdbus));
995 ret = FIELD_DP32(ret, SDHC_PRNSTS, CMD_LVL,
996 sdbus_get_cmd_line(&s->sdbus));
997 break;
998 case SDHC_HOSTCTL:
999 ret = s->hostctl1 | (s->pwrcon << 8) | (s->blkgap << 16) |
1000 (s->wakcon << 24);
1001 break;
1002 case SDHC_CLKCON:
1003 ret = s->clkcon | (s->timeoutcon << 16);
1004 break;
1005 case SDHC_NORINTSTS:
1006 ret = s->norintsts | (s->errintsts << 16);
1007 break;
1008 case SDHC_NORINTSTSEN:
1009 ret = s->norintstsen | (s->errintstsen << 16);
1010 break;
1011 case SDHC_NORINTSIGEN:
1012 ret = s->norintsigen | (s->errintsigen << 16);
1013 break;
1014 case SDHC_ACMD12ERRSTS:
1015 ret = s->acmd12errsts | (s->hostctl2 << 16);
1016 break;
1017 case SDHC_CAPAB:
1018 ret = (uint32_t)s->capareg;
1019 break;
1020 case SDHC_CAPAB + 4:
1021 ret = (uint32_t)(s->capareg >> 32);
1022 break;
1023 case SDHC_MAXCURR:
1024 ret = (uint32_t)s->maxcurr;
1025 break;
1026 case SDHC_MAXCURR + 4:
1027 ret = (uint32_t)(s->maxcurr >> 32);
1028 break;
1029 case SDHC_ADMAERR:
1030 ret = s->admaerr;
1031 break;
1032 case SDHC_ADMASYSADDR:
1033 ret = (uint32_t)s->admasysaddr;
1034 break;
1035 case SDHC_ADMASYSADDR + 4:
1036 ret = (uint32_t)(s->admasysaddr >> 32);
1037 break;
1038 case SDHC_SLOT_INT_STATUS:
1039 ret = (s->version << 16) | sdhci_slotint(s);
1040 break;
1041 default:
1042 qemu_log_mask(LOG_UNIMP, "SDHC rd_%ub @0x%02" HWADDR_PRIx " "
1043 "not implemented\n", size, offset);
1044 break;
1045 }
1046
1047 ret >>= (offset & 0x3) * 8;
1048 ret &= (1ULL << (size * 8)) - 1;
1049 trace_sdhci_access("rd", size << 3, offset, "->", ret, ret);
1050 return ret;
1051 }
1052
1053 static inline void sdhci_blkgap_write(SDHCIState *s, uint8_t value)
1054 {
1055 if ((value & SDHC_STOP_AT_GAP_REQ) && (s->blkgap & SDHC_STOP_AT_GAP_REQ)) {
1056 return;
1057 }
1058 s->blkgap = value & SDHC_STOP_AT_GAP_REQ;
1059
1060 if ((value & SDHC_CONTINUE_REQ) && s->stopped_state &&
1061 (s->blkgap & SDHC_STOP_AT_GAP_REQ) == 0) {
1062 if (s->stopped_state == sdhc_gap_read) {
1063 s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ;
1064 sdhci_read_block_from_card(s);
1065 } else {
1066 s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_WRITE;
1067 sdhci_write_block_to_card(s);
1068 }
1069 s->stopped_state = sdhc_not_stopped;
1070 } else if (!s->stopped_state && (value & SDHC_STOP_AT_GAP_REQ)) {
1071 if (s->prnsts & SDHC_DOING_READ) {
1072 s->stopped_state = sdhc_gap_read;
1073 } else if (s->prnsts & SDHC_DOING_WRITE) {
1074 s->stopped_state = sdhc_gap_write;
1075 }
1076 }
1077 }
1078
1079 static inline void sdhci_reset_write(SDHCIState *s, uint8_t value)
1080 {
1081 switch (value) {
1082 case SDHC_RESET_ALL:
1083 sdhci_reset(s);
1084 break;
1085 case SDHC_RESET_CMD:
1086 s->prnsts &= ~SDHC_CMD_INHIBIT;
1087 s->norintsts &= ~SDHC_NIS_CMDCMP;
1088 break;
1089 case SDHC_RESET_DATA:
1090 s->data_count = 0;
1091 s->prnsts &= ~(SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE |
1092 SDHC_DOING_READ | SDHC_DOING_WRITE |
1093 SDHC_DATA_INHIBIT | SDHC_DAT_LINE_ACTIVE);
1094 s->blkgap &= ~(SDHC_STOP_AT_GAP_REQ | SDHC_CONTINUE_REQ);
1095 s->stopped_state = sdhc_not_stopped;
1096 s->norintsts &= ~(SDHC_NIS_WBUFRDY | SDHC_NIS_RBUFRDY |
1097 SDHC_NIS_DMA | SDHC_NIS_TRSCMP | SDHC_NIS_BLKGAP);
1098 break;
1099 }
1100 }
1101
1102 static void
1103 sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
1104 {
1105 SDHCIState *s = (SDHCIState *)opaque;
1106 unsigned shift = 8 * (offset & 0x3);
1107 uint32_t mask = ~(((1ULL << (size * 8)) - 1) << shift);
1108 uint32_t value = val;
1109 value <<= shift;
1110
1111 switch (offset & ~0x3) {
1112 case SDHC_SYSAD:
1113 s->sdmasysad = (s->sdmasysad & mask) | value;
1114 MASKED_WRITE(s->sdmasysad, mask, value);
1115 /* Writing to last byte of sdmasysad might trigger transfer */
1116 if (!(mask & 0xFF000000) && TRANSFERRING_DATA(s->prnsts) && s->blkcnt &&
1117 s->blksize && SDHC_DMA_TYPE(s->hostctl1) == SDHC_CTRL_SDMA) {
1118 if (s->trnmod & SDHC_TRNS_MULTI) {
1119 sdhci_sdma_transfer_multi_blocks(s);
1120 } else {
1121 sdhci_sdma_transfer_single_block(s);
1122 }
1123 }
1124 break;
1125 case SDHC_BLKSIZE:
1126 if (!TRANSFERRING_DATA(s->prnsts)) {
1127 MASKED_WRITE(s->blksize, mask, value);
1128 MASKED_WRITE(s->blkcnt, mask >> 16, value >> 16);
1129 }
1130
1131 /* Limit block size to the maximum buffer size */
1132 if (extract32(s->blksize, 0, 12) > s->buf_maxsz) {
1133 qemu_log_mask(LOG_GUEST_ERROR, "%s: Size 0x%x is larger than "
1134 "the maximum buffer 0x%x", __func__, s->blksize,
1135 s->buf_maxsz);
1136
1137 s->blksize = deposit32(s->blksize, 0, 12, s->buf_maxsz);
1138 }
1139
1140 break;
1141 case SDHC_ARGUMENT:
1142 MASKED_WRITE(s->argument, mask, value);
1143 break;
1144 case SDHC_TRNMOD:
1145 /* DMA can be enabled only if it is supported as indicated by
1146 * capabilities register */
1147 if (!(s->capareg & R_SDHC_CAPAB_SDMA_MASK)) {
1148 value &= ~SDHC_TRNS_DMA;
1149 }
1150 MASKED_WRITE(s->trnmod, mask, value & SDHC_TRNMOD_MASK);
1151 MASKED_WRITE(s->cmdreg, mask >> 16, value >> 16);
1152
1153 /* Writing to the upper byte of CMDREG triggers SD command generation */
1154 if ((mask & 0xFF000000) || !sdhci_can_issue_command(s)) {
1155 break;
1156 }
1157
1158 sdhci_send_command(s);
1159 break;
1160 case SDHC_BDATA:
1161 if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) {
1162 sdhci_write_dataport(s, value >> shift, size);
1163 }
1164 break;
1165 case SDHC_HOSTCTL:
1166 if (!(mask & 0xFF0000)) {
1167 sdhci_blkgap_write(s, value >> 16);
1168 }
1169 MASKED_WRITE(s->hostctl1, mask, value);
1170 MASKED_WRITE(s->pwrcon, mask >> 8, value >> 8);
1171 MASKED_WRITE(s->wakcon, mask >> 24, value >> 24);
1172 if (!(s->prnsts & SDHC_CARD_PRESENT) || ((s->pwrcon >> 1) & 0x7) < 5 ||
1173 !(s->capareg & (1 << (31 - ((s->pwrcon >> 1) & 0x7))))) {
1174 s->pwrcon &= ~SDHC_POWER_ON;
1175 }
1176 break;
1177 case SDHC_CLKCON:
1178 if (!(mask & 0xFF000000)) {
1179 sdhci_reset_write(s, value >> 24);
1180 }
1181 MASKED_WRITE(s->clkcon, mask, value);
1182 MASKED_WRITE(s->timeoutcon, mask >> 16, value >> 16);
1183 if (s->clkcon & SDHC_CLOCK_INT_EN) {
1184 s->clkcon |= SDHC_CLOCK_INT_STABLE;
1185 } else {
1186 s->clkcon &= ~SDHC_CLOCK_INT_STABLE;
1187 }
1188 break;
1189 case SDHC_NORINTSTS:
1190 if (s->norintstsen & SDHC_NISEN_CARDINT) {
1191 value &= ~SDHC_NIS_CARDINT;
1192 }
1193 s->norintsts &= mask | ~value;
1194 s->errintsts &= (mask >> 16) | ~(value >> 16);
1195 if (s->errintsts) {
1196 s->norintsts |= SDHC_NIS_ERR;
1197 } else {
1198 s->norintsts &= ~SDHC_NIS_ERR;
1199 }
1200 sdhci_update_irq(s);
1201 break;
1202 case SDHC_NORINTSTSEN:
1203 MASKED_WRITE(s->norintstsen, mask, value);
1204 MASKED_WRITE(s->errintstsen, mask >> 16, value >> 16);
1205 s->norintsts &= s->norintstsen;
1206 s->errintsts &= s->errintstsen;
1207 if (s->errintsts) {
1208 s->norintsts |= SDHC_NIS_ERR;
1209 } else {
1210 s->norintsts &= ~SDHC_NIS_ERR;
1211 }
1212 /* Quirk for Raspberry Pi: pending card insert interrupt
1213 * appears when first enabled after power on */
1214 if ((s->norintstsen & SDHC_NISEN_INSERT) && s->pending_insert_state) {
1215 assert(s->pending_insert_quirk);
1216 s->norintsts |= SDHC_NIS_INSERT;
1217 s->pending_insert_state = false;
1218 }
1219 sdhci_update_irq(s);
1220 break;
1221 case SDHC_NORINTSIGEN:
1222 MASKED_WRITE(s->norintsigen, mask, value);
1223 MASKED_WRITE(s->errintsigen, mask >> 16, value >> 16);
1224 sdhci_update_irq(s);
1225 break;
1226 case SDHC_ADMAERR:
1227 MASKED_WRITE(s->admaerr, mask, value);
1228 break;
1229 case SDHC_ADMASYSADDR:
1230 s->admasysaddr = (s->admasysaddr & (0xFFFFFFFF00000000ULL |
1231 (uint64_t)mask)) | (uint64_t)value;
1232 break;
1233 case SDHC_ADMASYSADDR + 4:
1234 s->admasysaddr = (s->admasysaddr & (0x00000000FFFFFFFFULL |
1235 ((uint64_t)mask << 32))) | ((uint64_t)value << 32);
1236 break;
1237 case SDHC_FEAER:
1238 s->acmd12errsts |= value;
1239 s->errintsts |= (value >> 16) & s->errintstsen;
1240 if (s->acmd12errsts) {
1241 s->errintsts |= SDHC_EIS_CMD12ERR;
1242 }
1243 if (s->errintsts) {
1244 s->norintsts |= SDHC_NIS_ERR;
1245 }
1246 sdhci_update_irq(s);
1247 break;
1248 case SDHC_ACMD12ERRSTS:
1249 MASKED_WRITE(s->acmd12errsts, mask, value & UINT16_MAX);
1250 if (s->uhs_mode >= UHS_I) {
1251 MASKED_WRITE(s->hostctl2, mask >> 16, value >> 16);
1252
1253 if (FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, V18_ENA)) {
1254 sdbus_set_voltage(&s->sdbus, SD_VOLTAGE_1_8V);
1255 } else {
1256 sdbus_set_voltage(&s->sdbus, SD_VOLTAGE_3_3V);
1257 }
1258 }
1259 break;
1260
1261 case SDHC_CAPAB:
1262 case SDHC_CAPAB + 4:
1263 case SDHC_MAXCURR:
1264 case SDHC_MAXCURR + 4:
1265 qemu_log_mask(LOG_GUEST_ERROR, "SDHC wr_%ub @0x%02" HWADDR_PRIx
1266 " <- 0x%08x read-only\n", size, offset, value >> shift);
1267 break;
1268
1269 default:
1270 qemu_log_mask(LOG_UNIMP, "SDHC wr_%ub @0x%02" HWADDR_PRIx " <- 0x%08x "
1271 "not implemented\n", size, offset, value >> shift);
1272 break;
1273 }
1274 trace_sdhci_access("wr", size << 3, offset, "<-",
1275 value >> shift, value >> shift);
1276 }
1277
1278 static const MemoryRegionOps sdhci_mmio_ops = {
1279 .read = sdhci_read,
1280 .write = sdhci_write,
1281 .valid = {
1282 .min_access_size = 1,
1283 .max_access_size = 4,
1284 .unaligned = false
1285 },
1286 .endianness = DEVICE_LITTLE_ENDIAN,
1287 };
1288
1289 static void sdhci_init_readonly_registers(SDHCIState *s, Error **errp)
1290 {
1291 ERRP_GUARD();
1292
1293 switch (s->sd_spec_version) {
1294 case 2 ... 3:
1295 break;
1296 default:
1297 error_setg(errp, "Only Spec v2/v3 are supported");
1298 return;
1299 }
1300 s->version = (SDHC_HCVER_VENDOR << 8) | (s->sd_spec_version - 1);
1301
1302 sdhci_check_capareg(s, errp);
1303 if (*errp) {
1304 return;
1305 }
1306 }
1307
1308 /* --- qdev common --- */
1309
1310 void sdhci_initfn(SDHCIState *s)
1311 {
1312 qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
1313 TYPE_SDHCI_BUS, DEVICE(s), "sd-bus");
1314
1315 s->insert_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_raise_insertion_irq, s);
1316 s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_data_transfer, s);
1317
1318 s->io_ops = &sdhci_mmio_ops;
1319 }
1320
1321 void sdhci_uninitfn(SDHCIState *s)
1322 {
1323 timer_del(s->insert_timer);
1324 timer_free(s->insert_timer);
1325 timer_del(s->transfer_timer);
1326 timer_free(s->transfer_timer);
1327
1328 g_free(s->fifo_buffer);
1329 s->fifo_buffer = NULL;
1330 }
1331
1332 void sdhci_common_realize(SDHCIState *s, Error **errp)
1333 {
1334 ERRP_GUARD();
1335
1336 sdhci_init_readonly_registers(s, errp);
1337 if (*errp) {
1338 return;
1339 }
1340 s->buf_maxsz = sdhci_get_fifolen(s);
1341 s->fifo_buffer = g_malloc0(s->buf_maxsz);
1342
1343 memory_region_init_io(&s->iomem, OBJECT(s), s->io_ops, s, "sdhci",
1344 SDHC_REGISTERS_MAP_SIZE);
1345 }
1346
1347 void sdhci_common_unrealize(SDHCIState *s)
1348 {
1349 /* This function is expected to be called only once for each class:
1350 * - SysBus: via DeviceClass->unrealize(),
1351 * - PCI: via PCIDeviceClass->exit().
1352 * However to avoid double-free and/or use-after-free we still nullify
1353 * this variable (better safe than sorry!). */
1354 g_free(s->fifo_buffer);
1355 s->fifo_buffer = NULL;
1356 }
1357
1358 static bool sdhci_pending_insert_vmstate_needed(void *opaque)
1359 {
1360 SDHCIState *s = opaque;
1361
1362 return s->pending_insert_state;
1363 }
1364
1365 static const VMStateDescription sdhci_pending_insert_vmstate = {
1366 .name = "sdhci/pending-insert",
1367 .version_id = 1,
1368 .minimum_version_id = 1,
1369 .needed = sdhci_pending_insert_vmstate_needed,
1370 .fields = (VMStateField[]) {
1371 VMSTATE_BOOL(pending_insert_state, SDHCIState),
1372 VMSTATE_END_OF_LIST()
1373 },
1374 };
1375
1376 const VMStateDescription sdhci_vmstate = {
1377 .name = "sdhci",
1378 .version_id = 1,
1379 .minimum_version_id = 1,
1380 .fields = (VMStateField[]) {
1381 VMSTATE_UINT32(sdmasysad, SDHCIState),
1382 VMSTATE_UINT16(blksize, SDHCIState),
1383 VMSTATE_UINT16(blkcnt, SDHCIState),
1384 VMSTATE_UINT32(argument, SDHCIState),
1385 VMSTATE_UINT16(trnmod, SDHCIState),
1386 VMSTATE_UINT16(cmdreg, SDHCIState),
1387 VMSTATE_UINT32_ARRAY(rspreg, SDHCIState, 4),
1388 VMSTATE_UINT32(prnsts, SDHCIState),
1389 VMSTATE_UINT8(hostctl1, SDHCIState),
1390 VMSTATE_UINT8(pwrcon, SDHCIState),
1391 VMSTATE_UINT8(blkgap, SDHCIState),
1392 VMSTATE_UINT8(wakcon, SDHCIState),
1393 VMSTATE_UINT16(clkcon, SDHCIState),
1394 VMSTATE_UINT8(timeoutcon, SDHCIState),
1395 VMSTATE_UINT8(admaerr, SDHCIState),
1396 VMSTATE_UINT16(norintsts, SDHCIState),
1397 VMSTATE_UINT16(errintsts, SDHCIState),
1398 VMSTATE_UINT16(norintstsen, SDHCIState),
1399 VMSTATE_UINT16(errintstsen, SDHCIState),
1400 VMSTATE_UINT16(norintsigen, SDHCIState),
1401 VMSTATE_UINT16(errintsigen, SDHCIState),
1402 VMSTATE_UINT16(acmd12errsts, SDHCIState),
1403 VMSTATE_UINT16(data_count, SDHCIState),
1404 VMSTATE_UINT64(admasysaddr, SDHCIState),
1405 VMSTATE_UINT8(stopped_state, SDHCIState),
1406 VMSTATE_VBUFFER_UINT32(fifo_buffer, SDHCIState, 1, NULL, buf_maxsz),
1407 VMSTATE_TIMER_PTR(insert_timer, SDHCIState),
1408 VMSTATE_TIMER_PTR(transfer_timer, SDHCIState),
1409 VMSTATE_END_OF_LIST()
1410 },
1411 .subsections = (const VMStateDescription*[]) {
1412 &sdhci_pending_insert_vmstate,
1413 NULL
1414 },
1415 };
1416
1417 void sdhci_common_class_init(ObjectClass *klass, void *data)
1418 {
1419 DeviceClass *dc = DEVICE_CLASS(klass);
1420
1421 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
1422 dc->vmsd = &sdhci_vmstate;
1423 dc->reset = sdhci_poweron_reset;
1424 }
1425
1426 /* --- qdev SysBus --- */
1427
1428 static Property sdhci_sysbus_properties[] = {
1429 DEFINE_SDHCI_COMMON_PROPERTIES(SDHCIState),
1430 DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, pending_insert_quirk,
1431 false),
1432 DEFINE_PROP_LINK("dma", SDHCIState,
1433 dma_mr, TYPE_MEMORY_REGION, MemoryRegion *),
1434 DEFINE_PROP_END_OF_LIST(),
1435 };
1436
1437 static void sdhci_sysbus_init(Object *obj)
1438 {
1439 SDHCIState *s = SYSBUS_SDHCI(obj);
1440
1441 sdhci_initfn(s);
1442 }
1443
1444 static void sdhci_sysbus_finalize(Object *obj)
1445 {
1446 SDHCIState *s = SYSBUS_SDHCI(obj);
1447
1448 if (s->dma_mr) {
1449 object_unparent(OBJECT(s->dma_mr));
1450 }
1451
1452 sdhci_uninitfn(s);
1453 }
1454
1455 static void sdhci_sysbus_realize(DeviceState *dev, Error **errp)
1456 {
1457 ERRP_GUARD();
1458 SDHCIState *s = SYSBUS_SDHCI(dev);
1459 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1460
1461 sdhci_common_realize(s, errp);
1462 if (*errp) {
1463 return;
1464 }
1465
1466 if (s->dma_mr) {
1467 s->dma_as = &s->sysbus_dma_as;
1468 address_space_init(s->dma_as, s->dma_mr, "sdhci-dma");
1469 } else {
1470 /* use system_memory() if property "dma" not set */
1471 s->dma_as = &address_space_memory;
1472 }
1473
1474 sysbus_init_irq(sbd, &s->irq);
1475
1476 sysbus_init_mmio(sbd, &s->iomem);
1477 }
1478
1479 static void sdhci_sysbus_unrealize(DeviceState *dev)
1480 {
1481 SDHCIState *s = SYSBUS_SDHCI(dev);
1482
1483 sdhci_common_unrealize(s);
1484
1485 if (s->dma_mr) {
1486 address_space_destroy(s->dma_as);
1487 }
1488 }
1489
1490 static void sdhci_sysbus_class_init(ObjectClass *klass, void *data)
1491 {
1492 DeviceClass *dc = DEVICE_CLASS(klass);
1493
1494 device_class_set_props(dc, sdhci_sysbus_properties);
1495 dc->realize = sdhci_sysbus_realize;
1496 dc->unrealize = sdhci_sysbus_unrealize;
1497
1498 sdhci_common_class_init(klass, data);
1499 }
1500
1501 static const TypeInfo sdhci_sysbus_info = {
1502 .name = TYPE_SYSBUS_SDHCI,
1503 .parent = TYPE_SYS_BUS_DEVICE,
1504 .instance_size = sizeof(SDHCIState),
1505 .instance_init = sdhci_sysbus_init,
1506 .instance_finalize = sdhci_sysbus_finalize,
1507 .class_init = sdhci_sysbus_class_init,
1508 };
1509
1510 /* --- qdev bus master --- */
1511
1512 static void sdhci_bus_class_init(ObjectClass *klass, void *data)
1513 {
1514 SDBusClass *sbc = SD_BUS_CLASS(klass);
1515
1516 sbc->set_inserted = sdhci_set_inserted;
1517 sbc->set_readonly = sdhci_set_readonly;
1518 }
1519
1520 static const TypeInfo sdhci_bus_info = {
1521 .name = TYPE_SDHCI_BUS,
1522 .parent = TYPE_SD_BUS,
1523 .instance_size = sizeof(SDBus),
1524 .class_init = sdhci_bus_class_init,
1525 };
1526
1527 /* --- qdev i.MX eSDHC --- */
1528
1529 static uint64_t usdhc_read(void *opaque, hwaddr offset, unsigned size)
1530 {
1531 SDHCIState *s = SYSBUS_SDHCI(opaque);
1532 uint32_t ret;
1533 uint16_t hostctl1;
1534
1535 switch (offset) {
1536 default:
1537 return sdhci_read(opaque, offset, size);
1538
1539 case SDHC_HOSTCTL:
1540 /*
1541 * For a detailed explanation on the following bit
1542 * manipulation code see comments in a similar part of
1543 * usdhc_write()
1544 */
1545 hostctl1 = SDHC_DMA_TYPE(s->hostctl1) << (8 - 3);
1546
1547 if (s->hostctl1 & SDHC_CTRL_8BITBUS) {
1548 hostctl1 |= ESDHC_CTRL_8BITBUS;
1549 }
1550
1551 if (s->hostctl1 & SDHC_CTRL_4BITBUS) {
1552 hostctl1 |= ESDHC_CTRL_4BITBUS;
1553 }
1554
1555 ret = hostctl1;
1556 ret |= (uint32_t)s->blkgap << 16;
1557 ret |= (uint32_t)s->wakcon << 24;
1558
1559 break;
1560
1561 case SDHC_PRNSTS:
1562 /* Add SDSTB (SD Clock Stable) bit to PRNSTS */
1563 ret = sdhci_read(opaque, offset, size) & ~ESDHC_PRNSTS_SDSTB;
1564 if (s->clkcon & SDHC_CLOCK_INT_STABLE) {
1565 ret |= ESDHC_PRNSTS_SDSTB;
1566 }
1567 break;
1568
1569 case ESDHC_VENDOR_SPEC:
1570 ret = s->vendor_spec;
1571 break;
1572 case ESDHC_DLL_CTRL:
1573 case ESDHC_TUNE_CTRL_STATUS:
1574 case ESDHC_UNDOCUMENTED_REG27:
1575 case ESDHC_TUNING_CTRL:
1576 case ESDHC_MIX_CTRL:
1577 case ESDHC_WTMK_LVL:
1578 ret = 0;
1579 break;
1580 }
1581
1582 return ret;
1583 }
1584
1585 static void
1586 usdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
1587 {
1588 SDHCIState *s = SYSBUS_SDHCI(opaque);
1589 uint8_t hostctl1;
1590 uint32_t value = (uint32_t)val;
1591
1592 switch (offset) {
1593 case ESDHC_DLL_CTRL:
1594 case ESDHC_TUNE_CTRL_STATUS:
1595 case ESDHC_UNDOCUMENTED_REG27:
1596 case ESDHC_TUNING_CTRL:
1597 case ESDHC_WTMK_LVL:
1598 break;
1599
1600 case ESDHC_VENDOR_SPEC:
1601 s->vendor_spec = value;
1602 switch (s->vendor) {
1603 case SDHCI_VENDOR_IMX:
1604 if (value & ESDHC_IMX_FRC_SDCLK_ON) {
1605 s->prnsts &= ~SDHC_IMX_CLOCK_GATE_OFF;
1606 } else {
1607 s->prnsts |= SDHC_IMX_CLOCK_GATE_OFF;
1608 }
1609 break;
1610 default:
1611 break;
1612 }
1613 break;
1614
1615 case SDHC_HOSTCTL:
1616 /*
1617 * Here's What ESDHCI has at offset 0x28 (SDHC_HOSTCTL)
1618 *
1619 * 7 6 5 4 3 2 1 0
1620 * |-----------+--------+--------+-----------+----------+---------|
1621 * | Card | Card | Endian | DATA3 | Data | Led |
1622 * | Detect | Detect | Mode | as Card | Transfer | Control |
1623 * | Signal | Test | | Detection | Width | |
1624 * | Selection | Level | | Pin | | |
1625 * |-----------+--------+--------+-----------+----------+---------|
1626 *
1627 * and 0x29
1628 *
1629 * 15 10 9 8
1630 * |----------+------|
1631 * | Reserved | DMA |
1632 * | | Sel. |
1633 * | | |
1634 * |----------+------|
1635 *
1636 * and here's what SDCHI spec expects those offsets to be:
1637 *
1638 * 0x28 (Host Control Register)
1639 *
1640 * 7 6 5 4 3 2 1 0
1641 * |--------+--------+----------+------+--------+----------+---------|
1642 * | Card | Card | Extended | DMA | High | Data | LED |
1643 * | Detect | Detect | Data | Sel. | Speed | Transfer | Control |
1644 * | Signal | Test | Transfer | | Enable | Width | |
1645 * | Sel. | Level | Width | | | | |
1646 * |--------+--------+----------+------+--------+----------+---------|
1647 *
1648 * and 0x29 (Power Control Register)
1649 *
1650 * |----------------------------------|
1651 * | Power Control Register |
1652 * | |
1653 * | Description omitted, |
1654 * | since it has no analog in ESDHCI |
1655 * | |
1656 * |----------------------------------|
1657 *
1658 * Since offsets 0x2A and 0x2B should be compatible between
1659 * both IP specs we only need to reconcile least 16-bit of the
1660 * word we've been given.
1661 */
1662
1663 /*
1664 * First, save bits 7 6 and 0 since they are identical
1665 */
1666 hostctl1 = value & (SDHC_CTRL_LED |
1667 SDHC_CTRL_CDTEST_INS |
1668 SDHC_CTRL_CDTEST_EN);
1669 /*
1670 * Second, split "Data Transfer Width" from bits 2 and 1 in to
1671 * bits 5 and 1
1672 */
1673 if (value & ESDHC_CTRL_8BITBUS) {
1674 hostctl1 |= SDHC_CTRL_8BITBUS;
1675 }
1676
1677 if (value & ESDHC_CTRL_4BITBUS) {
1678 hostctl1 |= ESDHC_CTRL_4BITBUS;
1679 }
1680
1681 /*
1682 * Third, move DMA select from bits 9 and 8 to bits 4 and 3
1683 */
1684 hostctl1 |= SDHC_DMA_TYPE(value >> (8 - 3));
1685
1686 /*
1687 * Now place the corrected value into low 16-bit of the value
1688 * we are going to give standard SDHCI write function
1689 *
1690 * NOTE: This transformation should be the inverse of what can
1691 * be found in drivers/mmc/host/sdhci-esdhc-imx.c in Linux
1692 * kernel
1693 */
1694 value &= ~UINT16_MAX;
1695 value |= hostctl1;
1696 value |= (uint16_t)s->pwrcon << 8;
1697
1698 sdhci_write(opaque, offset, value, size);
1699 break;
1700
1701 case ESDHC_MIX_CTRL:
1702 /*
1703 * So, when SD/MMC stack in Linux tries to write to "Transfer
1704 * Mode Register", ESDHC i.MX quirk code will translate it
1705 * into a write to ESDHC_MIX_CTRL, so we do the opposite in
1706 * order to get where we started
1707 *
1708 * Note that Auto CMD23 Enable bit is located in a wrong place
1709 * on i.MX, but since it is not used by QEMU we do not care.
1710 *
1711 * We don't want to call sdhci_write(.., SDHC_TRNMOD, ...)
1712 * here becuase it will result in a call to
1713 * sdhci_send_command(s) which we don't want.
1714 *
1715 */
1716 s->trnmod = value & UINT16_MAX;
1717 break;
1718 case SDHC_TRNMOD:
1719 /*
1720 * Similar to above, but this time a write to "Command
1721 * Register" will be translated into a 4-byte write to
1722 * "Transfer Mode register" where lower 16-bit of value would
1723 * be set to zero. So what we do is fill those bits with
1724 * cached value from s->trnmod and let the SDHCI
1725 * infrastructure handle the rest
1726 */
1727 sdhci_write(opaque, offset, val | s->trnmod, size);
1728 break;
1729 case SDHC_BLKSIZE:
1730 /*
1731 * ESDHCI does not implement "Host SDMA Buffer Boundary", and
1732 * Linux driver will try to zero this field out which will
1733 * break the rest of SDHCI emulation.
1734 *
1735 * Linux defaults to maximum possible setting (512K boundary)
1736 * and it seems to be the only option that i.MX IP implements,
1737 * so we artificially set it to that value.
1738 */
1739 val |= 0x7 << 12;
1740 /* FALLTHROUGH */
1741 default:
1742 sdhci_write(opaque, offset, val, size);
1743 break;
1744 }
1745 }
1746
1747 static const MemoryRegionOps usdhc_mmio_ops = {
1748 .read = usdhc_read,
1749 .write = usdhc_write,
1750 .valid = {
1751 .min_access_size = 1,
1752 .max_access_size = 4,
1753 .unaligned = false
1754 },
1755 .endianness = DEVICE_LITTLE_ENDIAN,
1756 };
1757
1758 static void imx_usdhc_init(Object *obj)
1759 {
1760 SDHCIState *s = SYSBUS_SDHCI(obj);
1761
1762 s->io_ops = &usdhc_mmio_ops;
1763 s->quirks = SDHCI_QUIRK_NO_BUSY_IRQ;
1764 }
1765
1766 static const TypeInfo imx_usdhc_info = {
1767 .name = TYPE_IMX_USDHC,
1768 .parent = TYPE_SYSBUS_SDHCI,
1769 .instance_init = imx_usdhc_init,
1770 };
1771
1772 /* --- qdev Samsung s3c --- */
1773
1774 #define S3C_SDHCI_CONTROL2 0x80
1775 #define S3C_SDHCI_CONTROL3 0x84
1776 #define S3C_SDHCI_CONTROL4 0x8c
1777
1778 static uint64_t sdhci_s3c_read(void *opaque, hwaddr offset, unsigned size)
1779 {
1780 uint64_t ret;
1781
1782 switch (offset) {
1783 case S3C_SDHCI_CONTROL2:
1784 case S3C_SDHCI_CONTROL3:
1785 case S3C_SDHCI_CONTROL4:
1786 /* ignore */
1787 ret = 0;
1788 break;
1789 default:
1790 ret = sdhci_read(opaque, offset, size);
1791 break;
1792 }
1793
1794 return ret;
1795 }
1796
1797 static void sdhci_s3c_write(void *opaque, hwaddr offset, uint64_t val,
1798 unsigned size)
1799 {
1800 switch (offset) {
1801 case S3C_SDHCI_CONTROL2:
1802 case S3C_SDHCI_CONTROL3:
1803 case S3C_SDHCI_CONTROL4:
1804 /* ignore */
1805 break;
1806 default:
1807 sdhci_write(opaque, offset, val, size);
1808 break;
1809 }
1810 }
1811
1812 static const MemoryRegionOps sdhci_s3c_mmio_ops = {
1813 .read = sdhci_s3c_read,
1814 .write = sdhci_s3c_write,
1815 .valid = {
1816 .min_access_size = 1,
1817 .max_access_size = 4,
1818 .unaligned = false
1819 },
1820 .endianness = DEVICE_LITTLE_ENDIAN,
1821 };
1822
1823 static void sdhci_s3c_init(Object *obj)
1824 {
1825 SDHCIState *s = SYSBUS_SDHCI(obj);
1826
1827 s->io_ops = &sdhci_s3c_mmio_ops;
1828 }
1829
1830 static const TypeInfo sdhci_s3c_info = {
1831 .name = TYPE_S3C_SDHCI ,
1832 .parent = TYPE_SYSBUS_SDHCI,
1833 .instance_init = sdhci_s3c_init,
1834 };
1835
1836 static void sdhci_register_types(void)
1837 {
1838 type_register_static(&sdhci_sysbus_info);
1839 type_register_static(&sdhci_bus_info);
1840 type_register_static(&imx_usdhc_info);
1841 type_register_static(&sdhci_s3c_info);
1842 }
1843
1844 type_init(sdhci_register_types)