Add access control support to qemu bridge helper
[qemu.git] / hw / sh_intc.c
1 /*
2 * SuperH interrupt controller module
3 *
4 * Copyright (c) 2007 Magnus Damm
5 * Based on sh_timer.c and arm_timer.c by Paul Brook
6 * Copyright (c) 2005-2006 CodeSourcery.
7 *
8 * This code is licensed under the GPL.
9 */
10
11 #include "sh_intc.h"
12 #include "hw.h"
13 #include "sh.h"
14
15 //#define DEBUG_INTC
16 //#define DEBUG_INTC_SOURCES
17
18 #define INTC_A7(x) ((x) & 0x1fffffff)
19
20 void sh_intc_toggle_source(struct intc_source *source,
21 int enable_adj, int assert_adj)
22 {
23 int enable_changed = 0;
24 int pending_changed = 0;
25 int old_pending;
26
27 if ((source->enable_count == source->enable_max) && (enable_adj == -1))
28 enable_changed = -1;
29
30 source->enable_count += enable_adj;
31
32 if (source->enable_count == source->enable_max)
33 enable_changed = 1;
34
35 source->asserted += assert_adj;
36
37 old_pending = source->pending;
38 source->pending = source->asserted &&
39 (source->enable_count == source->enable_max);
40
41 if (old_pending != source->pending)
42 pending_changed = 1;
43
44 if (pending_changed) {
45 if (source->pending) {
46 source->parent->pending++;
47 if (source->parent->pending == 1)
48 cpu_interrupt(first_cpu, CPU_INTERRUPT_HARD);
49 }
50 else {
51 source->parent->pending--;
52 if (source->parent->pending == 0)
53 cpu_reset_interrupt(first_cpu, CPU_INTERRUPT_HARD);
54 }
55 }
56
57 if (enable_changed || assert_adj || pending_changed) {
58 #ifdef DEBUG_INTC_SOURCES
59 printf("sh_intc: (%d/%d/%d/%d) interrupt source 0x%x %s%s%s\n",
60 source->parent->pending,
61 source->asserted,
62 source->enable_count,
63 source->enable_max,
64 source->vect,
65 source->asserted ? "asserted " :
66 assert_adj ? "deasserted" : "",
67 enable_changed == 1 ? "enabled " :
68 enable_changed == -1 ? "disabled " : "",
69 source->pending ? "pending" : "");
70 #endif
71 }
72 }
73
74 static void sh_intc_set_irq (void *opaque, int n, int level)
75 {
76 struct intc_desc *desc = opaque;
77 struct intc_source *source = &(desc->sources[n]);
78
79 if (level && !source->asserted)
80 sh_intc_toggle_source(source, 0, 1);
81 else if (!level && source->asserted)
82 sh_intc_toggle_source(source, 0, -1);
83 }
84
85 int sh_intc_get_pending_vector(struct intc_desc *desc, int imask)
86 {
87 unsigned int i;
88
89 /* slow: use a linked lists of pending sources instead */
90 /* wrong: take interrupt priority into account (one list per priority) */
91
92 if (imask == 0x0f) {
93 return -1; /* FIXME, update code to include priority per source */
94 }
95
96 for (i = 0; i < desc->nr_sources; i++) {
97 struct intc_source *source = desc->sources + i;
98
99 if (source->pending) {
100 #ifdef DEBUG_INTC_SOURCES
101 printf("sh_intc: (%d) returning interrupt source 0x%x\n",
102 desc->pending, source->vect);
103 #endif
104 return source->vect;
105 }
106 }
107
108 abort();
109 }
110
111 #define INTC_MODE_NONE 0
112 #define INTC_MODE_DUAL_SET 1
113 #define INTC_MODE_DUAL_CLR 2
114 #define INTC_MODE_ENABLE_REG 3
115 #define INTC_MODE_MASK_REG 4
116 #define INTC_MODE_IS_PRIO 8
117
118 static unsigned int sh_intc_mode(unsigned long address,
119 unsigned long set_reg, unsigned long clr_reg)
120 {
121 if ((address != INTC_A7(set_reg)) &&
122 (address != INTC_A7(clr_reg)))
123 return INTC_MODE_NONE;
124
125 if (set_reg && clr_reg) {
126 if (address == INTC_A7(set_reg))
127 return INTC_MODE_DUAL_SET;
128 else
129 return INTC_MODE_DUAL_CLR;
130 }
131
132 if (set_reg)
133 return INTC_MODE_ENABLE_REG;
134 else
135 return INTC_MODE_MASK_REG;
136 }
137
138 static void sh_intc_locate(struct intc_desc *desc,
139 unsigned long address,
140 unsigned long **datap,
141 intc_enum **enums,
142 unsigned int *first,
143 unsigned int *width,
144 unsigned int *modep)
145 {
146 unsigned int i, mode;
147
148 /* this is slow but works for now */
149
150 if (desc->mask_regs) {
151 for (i = 0; i < desc->nr_mask_regs; i++) {
152 struct intc_mask_reg *mr = desc->mask_regs + i;
153
154 mode = sh_intc_mode(address, mr->set_reg, mr->clr_reg);
155 if (mode == INTC_MODE_NONE)
156 continue;
157
158 *modep = mode;
159 *datap = &mr->value;
160 *enums = mr->enum_ids;
161 *first = mr->reg_width - 1;
162 *width = 1;
163 return;
164 }
165 }
166
167 if (desc->prio_regs) {
168 for (i = 0; i < desc->nr_prio_regs; i++) {
169 struct intc_prio_reg *pr = desc->prio_regs + i;
170
171 mode = sh_intc_mode(address, pr->set_reg, pr->clr_reg);
172 if (mode == INTC_MODE_NONE)
173 continue;
174
175 *modep = mode | INTC_MODE_IS_PRIO;
176 *datap = &pr->value;
177 *enums = pr->enum_ids;
178 *first = (pr->reg_width / pr->field_width) - 1;
179 *width = pr->field_width;
180 return;
181 }
182 }
183
184 abort();
185 }
186
187 static void sh_intc_toggle_mask(struct intc_desc *desc, intc_enum id,
188 int enable, int is_group)
189 {
190 struct intc_source *source = desc->sources + id;
191
192 if (!id)
193 return;
194
195 if (!source->next_enum_id && (!source->enable_max || !source->vect)) {
196 #ifdef DEBUG_INTC_SOURCES
197 printf("sh_intc: reserved interrupt source %d modified\n", id);
198 #endif
199 return;
200 }
201
202 if (source->vect)
203 sh_intc_toggle_source(source, enable ? 1 : -1, 0);
204
205 #ifdef DEBUG_INTC
206 else {
207 printf("setting interrupt group %d to %d\n", id, !!enable);
208 }
209 #endif
210
211 if ((is_group || !source->vect) && source->next_enum_id) {
212 sh_intc_toggle_mask(desc, source->next_enum_id, enable, 1);
213 }
214
215 #ifdef DEBUG_INTC
216 if (!source->vect) {
217 printf("setting interrupt group %d to %d - done\n", id, !!enable);
218 }
219 #endif
220 }
221
222 static uint64_t sh_intc_read(void *opaque, target_phys_addr_t offset,
223 unsigned size)
224 {
225 struct intc_desc *desc = opaque;
226 intc_enum *enum_ids = NULL;
227 unsigned int first = 0;
228 unsigned int width = 0;
229 unsigned int mode = 0;
230 unsigned long *valuep;
231
232 #ifdef DEBUG_INTC
233 printf("sh_intc_read 0x%lx\n", (unsigned long) offset);
234 #endif
235
236 sh_intc_locate(desc, (unsigned long)offset, &valuep,
237 &enum_ids, &first, &width, &mode);
238 return *valuep;
239 }
240
241 static void sh_intc_write(void *opaque, target_phys_addr_t offset,
242 uint64_t value, unsigned size)
243 {
244 struct intc_desc *desc = opaque;
245 intc_enum *enum_ids = NULL;
246 unsigned int first = 0;
247 unsigned int width = 0;
248 unsigned int mode = 0;
249 unsigned int k;
250 unsigned long *valuep;
251 unsigned long mask;
252
253 #ifdef DEBUG_INTC
254 printf("sh_intc_write 0x%lx 0x%08x\n", (unsigned long) offset, value);
255 #endif
256
257 sh_intc_locate(desc, (unsigned long)offset, &valuep,
258 &enum_ids, &first, &width, &mode);
259
260 switch (mode) {
261 case INTC_MODE_ENABLE_REG | INTC_MODE_IS_PRIO: break;
262 case INTC_MODE_DUAL_SET: value |= *valuep; break;
263 case INTC_MODE_DUAL_CLR: value = *valuep & ~value; break;
264 default: abort();
265 }
266
267 for (k = 0; k <= first; k++) {
268 mask = ((1 << width) - 1) << ((first - k) * width);
269
270 if ((*valuep & mask) == (value & mask))
271 continue;
272 #if 0
273 printf("k = %d, first = %d, enum = %d, mask = 0x%08x\n",
274 k, first, enum_ids[k], (unsigned int)mask);
275 #endif
276 sh_intc_toggle_mask(desc, enum_ids[k], value & mask, 0);
277 }
278
279 *valuep = value;
280
281 #ifdef DEBUG_INTC
282 printf("sh_intc_write 0x%lx -> 0x%08x\n", (unsigned long) offset, value);
283 #endif
284 }
285
286 static const struct MemoryRegionOps sh_intc_ops = {
287 .read = sh_intc_read,
288 .write = sh_intc_write,
289 .endianness = DEVICE_NATIVE_ENDIAN,
290 };
291
292 struct intc_source *sh_intc_source(struct intc_desc *desc, intc_enum id)
293 {
294 if (id)
295 return desc->sources + id;
296
297 return NULL;
298 }
299
300 static unsigned int sh_intc_register(MemoryRegion *sysmem,
301 struct intc_desc *desc,
302 const unsigned long address,
303 const char *type,
304 const char *action,
305 const unsigned int index)
306 {
307 char name[60];
308 MemoryRegion *iomem, *iomem_p4, *iomem_a7;
309
310 if (!address) {
311 return 0;
312 }
313
314 iomem = &desc->iomem;
315 iomem_p4 = desc->iomem_aliases + index;
316 iomem_a7 = iomem_p4 + 1;
317
318 #define SH_INTC_IOMEM_FORMAT "interrupt-controller-%s-%s-%s"
319 snprintf(name, sizeof(name), SH_INTC_IOMEM_FORMAT, type, action, "p4");
320 memory_region_init_alias(iomem_p4, name, iomem, INTC_A7(address), 4);
321 memory_region_add_subregion(sysmem, P4ADDR(address), iomem_p4);
322
323 snprintf(name, sizeof(name), SH_INTC_IOMEM_FORMAT, type, action, "a7");
324 memory_region_init_alias(iomem_a7, name, iomem, INTC_A7(address), 4);
325 memory_region_add_subregion(sysmem, A7ADDR(address), iomem_a7);
326 #undef SH_INTC_IOMEM_FORMAT
327
328 /* used to increment aliases index */
329 return 2;
330 }
331
332 static void sh_intc_register_source(struct intc_desc *desc,
333 intc_enum source,
334 struct intc_group *groups,
335 int nr_groups)
336 {
337 unsigned int i, k;
338 struct intc_source *s;
339
340 if (desc->mask_regs) {
341 for (i = 0; i < desc->nr_mask_regs; i++) {
342 struct intc_mask_reg *mr = desc->mask_regs + i;
343
344 for (k = 0; k < ARRAY_SIZE(mr->enum_ids); k++) {
345 if (mr->enum_ids[k] != source)
346 continue;
347
348 s = sh_intc_source(desc, mr->enum_ids[k]);
349 if (s)
350 s->enable_max++;
351 }
352 }
353 }
354
355 if (desc->prio_regs) {
356 for (i = 0; i < desc->nr_prio_regs; i++) {
357 struct intc_prio_reg *pr = desc->prio_regs + i;
358
359 for (k = 0; k < ARRAY_SIZE(pr->enum_ids); k++) {
360 if (pr->enum_ids[k] != source)
361 continue;
362
363 s = sh_intc_source(desc, pr->enum_ids[k]);
364 if (s)
365 s->enable_max++;
366 }
367 }
368 }
369
370 if (groups) {
371 for (i = 0; i < nr_groups; i++) {
372 struct intc_group *gr = groups + i;
373
374 for (k = 0; k < ARRAY_SIZE(gr->enum_ids); k++) {
375 if (gr->enum_ids[k] != source)
376 continue;
377
378 s = sh_intc_source(desc, gr->enum_ids[k]);
379 if (s)
380 s->enable_max++;
381 }
382 }
383 }
384
385 }
386
387 void sh_intc_register_sources(struct intc_desc *desc,
388 struct intc_vect *vectors,
389 int nr_vectors,
390 struct intc_group *groups,
391 int nr_groups)
392 {
393 unsigned int i, k;
394 struct intc_source *s;
395
396 for (i = 0; i < nr_vectors; i++) {
397 struct intc_vect *vect = vectors + i;
398
399 sh_intc_register_source(desc, vect->enum_id, groups, nr_groups);
400 s = sh_intc_source(desc, vect->enum_id);
401 if (s) {
402 s->vect = vect->vect;
403
404 #ifdef DEBUG_INTC_SOURCES
405 printf("sh_intc: registered source %d -> 0x%04x (%d/%d)\n",
406 vect->enum_id, s->vect, s->enable_count, s->enable_max);
407 #endif
408 }
409 }
410
411 if (groups) {
412 for (i = 0; i < nr_groups; i++) {
413 struct intc_group *gr = groups + i;
414
415 s = sh_intc_source(desc, gr->enum_id);
416 s->next_enum_id = gr->enum_ids[0];
417
418 for (k = 1; k < ARRAY_SIZE(gr->enum_ids); k++) {
419 if (!gr->enum_ids[k])
420 continue;
421
422 s = sh_intc_source(desc, gr->enum_ids[k - 1]);
423 s->next_enum_id = gr->enum_ids[k];
424 }
425
426 #ifdef DEBUG_INTC_SOURCES
427 printf("sh_intc: registered group %d (%d/%d)\n",
428 gr->enum_id, s->enable_count, s->enable_max);
429 #endif
430 }
431 }
432 }
433
434 int sh_intc_init(MemoryRegion *sysmem,
435 struct intc_desc *desc,
436 int nr_sources,
437 struct intc_mask_reg *mask_regs,
438 int nr_mask_regs,
439 struct intc_prio_reg *prio_regs,
440 int nr_prio_regs)
441 {
442 unsigned int i, j;
443
444 desc->pending = 0;
445 desc->nr_sources = nr_sources;
446 desc->mask_regs = mask_regs;
447 desc->nr_mask_regs = nr_mask_regs;
448 desc->prio_regs = prio_regs;
449 desc->nr_prio_regs = nr_prio_regs;
450 /* Allocate 4 MemoryRegions per register (2 actions * 2 aliases).
451 **/
452 desc->iomem_aliases = g_new0(MemoryRegion,
453 (nr_mask_regs + nr_prio_regs) * 4);
454
455 j = 0;
456 i = sizeof(struct intc_source) * nr_sources;
457 desc->sources = g_malloc0(i);
458
459 for (i = 0; i < desc->nr_sources; i++) {
460 struct intc_source *source = desc->sources + i;
461
462 source->parent = desc;
463 }
464
465 desc->irqs = qemu_allocate_irqs(sh_intc_set_irq, desc, nr_sources);
466
467 memory_region_init_io(&desc->iomem, &sh_intc_ops, desc,
468 "interrupt-controller", 0x100000000ULL);
469
470 #define INT_REG_PARAMS(reg_struct, type, action, j) \
471 reg_struct->action##_reg, #type, #action, j
472 if (desc->mask_regs) {
473 for (i = 0; i < desc->nr_mask_regs; i++) {
474 struct intc_mask_reg *mr = desc->mask_regs + i;
475
476 j += sh_intc_register(sysmem, desc,
477 INT_REG_PARAMS(mr, mask, set, j));
478 j += sh_intc_register(sysmem, desc,
479 INT_REG_PARAMS(mr, mask, clr, j));
480 }
481 }
482
483 if (desc->prio_regs) {
484 for (i = 0; i < desc->nr_prio_regs; i++) {
485 struct intc_prio_reg *pr = desc->prio_regs + i;
486
487 j += sh_intc_register(sysmem, desc,
488 INT_REG_PARAMS(pr, prio, set, j));
489 j += sh_intc_register(sysmem, desc,
490 INT_REG_PARAMS(pr, prio, clr, j));
491 }
492 }
493 #undef INT_REG_PARAMS
494
495 return 0;
496 }
497
498 /* Assert level <n> IRL interrupt.
499 0:deassert. 1:lowest priority,... 15:highest priority. */
500 void sh_intc_set_irl(void *opaque, int n, int level)
501 {
502 struct intc_source *s = opaque;
503 int i, irl = level ^ 15;
504 for (i = 0; (s = sh_intc_source(s->parent, s->next_enum_id)); i++) {
505 if (i == irl)
506 sh_intc_toggle_source(s, s->enable_count?0:1, s->asserted?0:1);
507 else
508 if (s->asserted)
509 sh_intc_toggle_source(s, 0, -1);
510 }
511 }