linux-user: stack_base is now mandatory on all targets
[qemu.git] / hw / slavio_intctl.c
1 /*
2 * QEMU Sparc SLAVIO interrupt controller emulation
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "sun4m.h"
26 #include "monitor.h"
27 #include "sysbus.h"
28 #include "trace.h"
29
30 //#define DEBUG_IRQ_COUNT
31
32 /*
33 * Registers of interrupt controller in sun4m.
34 *
35 * This is the interrupt controller part of chip STP2001 (Slave I/O), also
36 * produced as NCR89C105. See
37 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
38 *
39 * There is a system master controller and one for each cpu.
40 *
41 */
42
43 #define MAX_CPUS 16
44 #define MAX_PILS 16
45
46 struct SLAVIO_INTCTLState;
47
48 typedef struct SLAVIO_CPUINTCTLState {
49 MemoryRegion iomem;
50 struct SLAVIO_INTCTLState *master;
51 uint32_t intreg_pending;
52 uint32_t cpu;
53 uint32_t irl_out;
54 } SLAVIO_CPUINTCTLState;
55
56 typedef struct SLAVIO_INTCTLState {
57 SysBusDevice busdev;
58 MemoryRegion iomem;
59 #ifdef DEBUG_IRQ_COUNT
60 uint64_t irq_count[32];
61 #endif
62 qemu_irq cpu_irqs[MAX_CPUS][MAX_PILS];
63 SLAVIO_CPUINTCTLState slaves[MAX_CPUS];
64 uint32_t intregm_pending;
65 uint32_t intregm_disabled;
66 uint32_t target_cpu;
67 } SLAVIO_INTCTLState;
68
69 #define INTCTL_MAXADDR 0xf
70 #define INTCTL_SIZE (INTCTL_MAXADDR + 1)
71 #define INTCTLM_SIZE 0x14
72 #define MASTER_IRQ_MASK ~0x0fa2007f
73 #define MASTER_DISABLE 0x80000000
74 #define CPU_SOFTIRQ_MASK 0xfffe0000
75 #define CPU_IRQ_INT15_IN (1 << 15)
76 #define CPU_IRQ_TIMER_IN (1 << 14)
77
78 static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs);
79
80 // per-cpu interrupt controller
81 static uint64_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr,
82 unsigned size)
83 {
84 SLAVIO_CPUINTCTLState *s = opaque;
85 uint32_t saddr, ret;
86
87 saddr = addr >> 2;
88 switch (saddr) {
89 case 0:
90 ret = s->intreg_pending;
91 break;
92 default:
93 ret = 0;
94 break;
95 }
96 trace_slavio_intctl_mem_readl(s->cpu, addr, ret);
97
98 return ret;
99 }
100
101 static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr,
102 uint64_t val, unsigned size)
103 {
104 SLAVIO_CPUINTCTLState *s = opaque;
105 uint32_t saddr;
106
107 saddr = addr >> 2;
108 trace_slavio_intctl_mem_writel(s->cpu, addr, val);
109 switch (saddr) {
110 case 1: // clear pending softints
111 val &= CPU_SOFTIRQ_MASK | CPU_IRQ_INT15_IN;
112 s->intreg_pending &= ~val;
113 slavio_check_interrupts(s->master, 1);
114 trace_slavio_intctl_mem_writel_clear(s->cpu, val, s->intreg_pending);
115 break;
116 case 2: // set softint
117 val &= CPU_SOFTIRQ_MASK;
118 s->intreg_pending |= val;
119 slavio_check_interrupts(s->master, 1);
120 trace_slavio_intctl_mem_writel_set(s->cpu, val, s->intreg_pending);
121 break;
122 default:
123 break;
124 }
125 }
126
127 static const MemoryRegionOps slavio_intctl_mem_ops = {
128 .read = slavio_intctl_mem_readl,
129 .write = slavio_intctl_mem_writel,
130 .endianness = DEVICE_NATIVE_ENDIAN,
131 .valid = {
132 .min_access_size = 4,
133 .max_access_size = 4,
134 },
135 };
136
137 // master system interrupt controller
138 static uint64_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr,
139 unsigned size)
140 {
141 SLAVIO_INTCTLState *s = opaque;
142 uint32_t saddr, ret;
143
144 saddr = addr >> 2;
145 switch (saddr) {
146 case 0:
147 ret = s->intregm_pending & ~MASTER_DISABLE;
148 break;
149 case 1:
150 ret = s->intregm_disabled & MASTER_IRQ_MASK;
151 break;
152 case 4:
153 ret = s->target_cpu;
154 break;
155 default:
156 ret = 0;
157 break;
158 }
159 trace_slavio_intctlm_mem_readl(addr, ret);
160
161 return ret;
162 }
163
164 static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr,
165 uint64_t val, unsigned size)
166 {
167 SLAVIO_INTCTLState *s = opaque;
168 uint32_t saddr;
169
170 saddr = addr >> 2;
171 trace_slavio_intctlm_mem_writel(addr, val);
172 switch (saddr) {
173 case 2: // clear (enable)
174 // Force clear unused bits
175 val &= MASTER_IRQ_MASK;
176 s->intregm_disabled &= ~val;
177 trace_slavio_intctlm_mem_writel_enable(val, s->intregm_disabled);
178 slavio_check_interrupts(s, 1);
179 break;
180 case 3: // set (disable; doesn't affect pending)
181 // Force clear unused bits
182 val &= MASTER_IRQ_MASK;
183 s->intregm_disabled |= val;
184 slavio_check_interrupts(s, 1);
185 trace_slavio_intctlm_mem_writel_disable(val, s->intregm_disabled);
186 break;
187 case 4:
188 s->target_cpu = val & (MAX_CPUS - 1);
189 slavio_check_interrupts(s, 1);
190 trace_slavio_intctlm_mem_writel_target(s->target_cpu);
191 break;
192 default:
193 break;
194 }
195 }
196
197 static const MemoryRegionOps slavio_intctlm_mem_ops = {
198 .read = slavio_intctlm_mem_readl,
199 .write = slavio_intctlm_mem_writel,
200 .endianness = DEVICE_NATIVE_ENDIAN,
201 .valid = {
202 .min_access_size = 4,
203 .max_access_size = 4,
204 },
205 };
206
207 void slavio_pic_info(Monitor *mon, DeviceState *dev)
208 {
209 SysBusDevice *sd;
210 SLAVIO_INTCTLState *s;
211 int i;
212
213 sd = sysbus_from_qdev(dev);
214 s = FROM_SYSBUS(SLAVIO_INTCTLState, sd);
215 for (i = 0; i < MAX_CPUS; i++) {
216 monitor_printf(mon, "per-cpu %d: pending 0x%08x\n", i,
217 s->slaves[i].intreg_pending);
218 }
219 monitor_printf(mon, "master: pending 0x%08x, disabled 0x%08x\n",
220 s->intregm_pending, s->intregm_disabled);
221 }
222
223 void slavio_irq_info(Monitor *mon, DeviceState *dev)
224 {
225 #ifndef DEBUG_IRQ_COUNT
226 monitor_printf(mon, "irq statistic code not compiled.\n");
227 #else
228 SysBusDevice *sd;
229 SLAVIO_INTCTLState *s;
230 int i;
231 int64_t count;
232
233 sd = sysbus_from_qdev(dev);
234 s = FROM_SYSBUS(SLAVIO_INTCTLState, sd);
235 monitor_printf(mon, "IRQ statistics:\n");
236 for (i = 0; i < 32; i++) {
237 count = s->irq_count[i];
238 if (count > 0)
239 monitor_printf(mon, "%2d: %" PRId64 "\n", i, count);
240 }
241 #endif
242 }
243
244 static const uint32_t intbit_to_level[] = {
245 2, 3, 5, 7, 9, 11, 13, 2, 3, 5, 7, 9, 11, 13, 12, 12,
246 6, 13, 4, 10, 8, 9, 11, 0, 0, 0, 0, 15, 15, 15, 15, 0,
247 };
248
249 static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs)
250 {
251 uint32_t pending = s->intregm_pending, pil_pending;
252 unsigned int i, j;
253
254 pending &= ~s->intregm_disabled;
255
256 trace_slavio_check_interrupts(pending, s->intregm_disabled);
257 for (i = 0; i < MAX_CPUS; i++) {
258 pil_pending = 0;
259
260 /* If we are the current interrupt target, get hard interrupts */
261 if (pending && !(s->intregm_disabled & MASTER_DISABLE) &&
262 (i == s->target_cpu)) {
263 for (j = 0; j < 32; j++) {
264 if ((pending & (1 << j)) && intbit_to_level[j]) {
265 pil_pending |= 1 << intbit_to_level[j];
266 }
267 }
268 }
269
270 /* Calculate current pending hard interrupts for display */
271 s->slaves[i].intreg_pending &= CPU_SOFTIRQ_MASK | CPU_IRQ_INT15_IN |
272 CPU_IRQ_TIMER_IN;
273 if (i == s->target_cpu) {
274 for (j = 0; j < 32; j++) {
275 if ((s->intregm_pending & (1 << j)) && intbit_to_level[j]) {
276 s->slaves[i].intreg_pending |= 1 << intbit_to_level[j];
277 }
278 }
279 }
280
281 /* Level 15 and CPU timer interrupts are only masked when
282 the MASTER_DISABLE bit is set */
283 if (!(s->intregm_disabled & MASTER_DISABLE)) {
284 pil_pending |= s->slaves[i].intreg_pending &
285 (CPU_IRQ_INT15_IN | CPU_IRQ_TIMER_IN);
286 }
287
288 /* Add soft interrupts */
289 pil_pending |= (s->slaves[i].intreg_pending & CPU_SOFTIRQ_MASK) >> 16;
290
291 if (set_irqs) {
292 /* Since there is not really an interrupt 0 (and pil_pending
293 * and irl_out bit zero are thus always zero) there is no need
294 * to do anything with cpu_irqs[i][0] and it is OK not to do
295 * the j=0 iteration of this loop.
296 */
297 for (j = MAX_PILS-1; j > 0; j--) {
298 if (pil_pending & (1 << j)) {
299 if (!(s->slaves[i].irl_out & (1 << j))) {
300 qemu_irq_raise(s->cpu_irqs[i][j]);
301 }
302 } else {
303 if (s->slaves[i].irl_out & (1 << j)) {
304 qemu_irq_lower(s->cpu_irqs[i][j]);
305 }
306 }
307 }
308 }
309 s->slaves[i].irl_out = pil_pending;
310 }
311 }
312
313 /*
314 * "irq" here is the bit number in the system interrupt register to
315 * separate serial and keyboard interrupts sharing a level.
316 */
317 static void slavio_set_irq(void *opaque, int irq, int level)
318 {
319 SLAVIO_INTCTLState *s = opaque;
320 uint32_t mask = 1 << irq;
321 uint32_t pil = intbit_to_level[irq];
322 unsigned int i;
323
324 trace_slavio_set_irq(s->target_cpu, irq, pil, level);
325 if (pil > 0) {
326 if (level) {
327 #ifdef DEBUG_IRQ_COUNT
328 s->irq_count[pil]++;
329 #endif
330 s->intregm_pending |= mask;
331 if (pil == 15) {
332 for (i = 0; i < MAX_CPUS; i++) {
333 s->slaves[i].intreg_pending |= 1 << pil;
334 }
335 }
336 } else {
337 s->intregm_pending &= ~mask;
338 if (pil == 15) {
339 for (i = 0; i < MAX_CPUS; i++) {
340 s->slaves[i].intreg_pending &= ~(1 << pil);
341 }
342 }
343 }
344 slavio_check_interrupts(s, 1);
345 }
346 }
347
348 static void slavio_set_timer_irq_cpu(void *opaque, int cpu, int level)
349 {
350 SLAVIO_INTCTLState *s = opaque;
351
352 trace_slavio_set_timer_irq_cpu(cpu, level);
353
354 if (level) {
355 s->slaves[cpu].intreg_pending |= CPU_IRQ_TIMER_IN;
356 } else {
357 s->slaves[cpu].intreg_pending &= ~CPU_IRQ_TIMER_IN;
358 }
359
360 slavio_check_interrupts(s, 1);
361 }
362
363 static void slavio_set_irq_all(void *opaque, int irq, int level)
364 {
365 if (irq < 32) {
366 slavio_set_irq(opaque, irq, level);
367 } else {
368 slavio_set_timer_irq_cpu(opaque, irq - 32, level);
369 }
370 }
371
372 static int vmstate_intctl_post_load(void *opaque, int version_id)
373 {
374 SLAVIO_INTCTLState *s = opaque;
375
376 slavio_check_interrupts(s, 0);
377 return 0;
378 }
379
380 static const VMStateDescription vmstate_intctl_cpu = {
381 .name ="slavio_intctl_cpu",
382 .version_id = 1,
383 .minimum_version_id = 1,
384 .minimum_version_id_old = 1,
385 .fields = (VMStateField []) {
386 VMSTATE_UINT32(intreg_pending, SLAVIO_CPUINTCTLState),
387 VMSTATE_END_OF_LIST()
388 }
389 };
390
391 static const VMStateDescription vmstate_intctl = {
392 .name ="slavio_intctl",
393 .version_id = 1,
394 .minimum_version_id = 1,
395 .minimum_version_id_old = 1,
396 .post_load = vmstate_intctl_post_load,
397 .fields = (VMStateField []) {
398 VMSTATE_STRUCT_ARRAY(slaves, SLAVIO_INTCTLState, MAX_CPUS, 1,
399 vmstate_intctl_cpu, SLAVIO_CPUINTCTLState),
400 VMSTATE_UINT32(intregm_pending, SLAVIO_INTCTLState),
401 VMSTATE_UINT32(intregm_disabled, SLAVIO_INTCTLState),
402 VMSTATE_UINT32(target_cpu, SLAVIO_INTCTLState),
403 VMSTATE_END_OF_LIST()
404 }
405 };
406
407 static void slavio_intctl_reset(DeviceState *d)
408 {
409 SLAVIO_INTCTLState *s = container_of(d, SLAVIO_INTCTLState, busdev.qdev);
410 int i;
411
412 for (i = 0; i < MAX_CPUS; i++) {
413 s->slaves[i].intreg_pending = 0;
414 s->slaves[i].irl_out = 0;
415 }
416 s->intregm_disabled = ~MASTER_IRQ_MASK;
417 s->intregm_pending = 0;
418 s->target_cpu = 0;
419 slavio_check_interrupts(s, 0);
420 }
421
422 static int slavio_intctl_init1(SysBusDevice *dev)
423 {
424 SLAVIO_INTCTLState *s = FROM_SYSBUS(SLAVIO_INTCTLState, dev);
425 unsigned int i, j;
426 char slave_name[45];
427
428 qdev_init_gpio_in(&dev->qdev, slavio_set_irq_all, 32 + MAX_CPUS);
429 memory_region_init_io(&s->iomem, &slavio_intctlm_mem_ops, s,
430 "master-interrupt-controller", INTCTLM_SIZE);
431 sysbus_init_mmio(dev, &s->iomem);
432
433 for (i = 0; i < MAX_CPUS; i++) {
434 snprintf(slave_name, sizeof(slave_name),
435 "slave-interrupt-controller-%i", i);
436 for (j = 0; j < MAX_PILS; j++) {
437 sysbus_init_irq(dev, &s->cpu_irqs[i][j]);
438 }
439 memory_region_init_io(&s->slaves[i].iomem, &slavio_intctl_mem_ops,
440 &s->slaves[i], slave_name, INTCTL_SIZE);
441 sysbus_init_mmio(dev, &s->slaves[i].iomem);
442 s->slaves[i].cpu = i;
443 s->slaves[i].master = s;
444 }
445
446 return 0;
447 }
448
449 static void slavio_intctl_class_init(ObjectClass *klass, void *data)
450 {
451 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
452
453 k->init = slavio_intctl_init1;
454 }
455
456 static DeviceInfo slavio_intctl_info = {
457 .name = "slavio_intctl",
458 .size = sizeof(SLAVIO_INTCTLState),
459 .vmsd = &vmstate_intctl,
460 .reset = slavio_intctl_reset,
461 .class_init = slavio_intctl_class_init,
462 };
463
464 static void slavio_intctl_register_devices(void)
465 {
466 sysbus_register_withprop(&slavio_intctl_info);
467 }
468
469 device_init(slavio_intctl_register_devices)