Add access control support to qemu bridge helper
[qemu.git] / hw / slavio_timer.c
1 /*
2 * QEMU Sparc SLAVIO timer controller emulation
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "sun4m.h"
26 #include "qemu-timer.h"
27 #include "ptimer.h"
28 #include "sysbus.h"
29 #include "trace.h"
30
31 /*
32 * Registers of hardware timer in sun4m.
33 *
34 * This is the timer/counter part of chip STP2001 (Slave I/O), also
35 * produced as NCR89C105. See
36 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
37 *
38 * The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0
39 * are zero. Bit 31 is 1 when count has been reached.
40 *
41 * Per-CPU timers interrupt local CPU, system timer uses normal
42 * interrupt routing.
43 *
44 */
45
46 #define MAX_CPUS 16
47
48 typedef struct CPUTimerState {
49 qemu_irq irq;
50 ptimer_state *timer;
51 uint32_t count, counthigh, reached;
52 /* processor only */
53 uint32_t running;
54 uint64_t limit;
55 } CPUTimerState;
56
57 typedef struct SLAVIO_TIMERState {
58 SysBusDevice busdev;
59 uint32_t num_cpus;
60 uint32_t cputimer_mode;
61 CPUTimerState cputimer[MAX_CPUS + 1];
62 } SLAVIO_TIMERState;
63
64 typedef struct TimerContext {
65 MemoryRegion iomem;
66 SLAVIO_TIMERState *s;
67 unsigned int timer_index; /* 0 for system, 1 ... MAX_CPUS for CPU timers */
68 } TimerContext;
69
70 #define SYS_TIMER_SIZE 0x14
71 #define CPU_TIMER_SIZE 0x10
72
73 #define TIMER_LIMIT 0
74 #define TIMER_COUNTER 1
75 #define TIMER_COUNTER_NORST 2
76 #define TIMER_STATUS 3
77 #define TIMER_MODE 4
78
79 #define TIMER_COUNT_MASK32 0xfffffe00
80 #define TIMER_LIMIT_MASK32 0x7fffffff
81 #define TIMER_MAX_COUNT64 0x7ffffffffffffe00ULL
82 #define TIMER_MAX_COUNT32 0x7ffffe00ULL
83 #define TIMER_REACHED 0x80000000
84 #define TIMER_PERIOD 500ULL // 500ns
85 #define LIMIT_TO_PERIODS(l) (((l) >> 9) - 1)
86 #define PERIODS_TO_LIMIT(l) (((l) + 1) << 9)
87
88 static int slavio_timer_is_user(TimerContext *tc)
89 {
90 SLAVIO_TIMERState *s = tc->s;
91 unsigned int timer_index = tc->timer_index;
92
93 return timer_index != 0 && (s->cputimer_mode & (1 << (timer_index - 1)));
94 }
95
96 // Update count, set irq, update expire_time
97 // Convert from ptimer countdown units
98 static void slavio_timer_get_out(CPUTimerState *t)
99 {
100 uint64_t count, limit;
101
102 if (t->limit == 0) { /* free-run system or processor counter */
103 limit = TIMER_MAX_COUNT32;
104 } else {
105 limit = t->limit;
106 }
107 count = limit - PERIODS_TO_LIMIT(ptimer_get_count(t->timer));
108
109 trace_slavio_timer_get_out(t->limit, t->counthigh, t->count);
110 t->count = count & TIMER_COUNT_MASK32;
111 t->counthigh = count >> 32;
112 }
113
114 // timer callback
115 static void slavio_timer_irq(void *opaque)
116 {
117 TimerContext *tc = opaque;
118 SLAVIO_TIMERState *s = tc->s;
119 CPUTimerState *t = &s->cputimer[tc->timer_index];
120
121 slavio_timer_get_out(t);
122 trace_slavio_timer_irq(t->counthigh, t->count);
123 /* if limit is 0 (free-run), there will be no match */
124 if (t->limit != 0) {
125 t->reached = TIMER_REACHED;
126 }
127 /* there is no interrupt if user timer or free-run */
128 if (!slavio_timer_is_user(tc) && t->limit != 0) {
129 qemu_irq_raise(t->irq);
130 }
131 }
132
133 static uint64_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr,
134 unsigned size)
135 {
136 TimerContext *tc = opaque;
137 SLAVIO_TIMERState *s = tc->s;
138 uint32_t saddr, ret;
139 unsigned int timer_index = tc->timer_index;
140 CPUTimerState *t = &s->cputimer[timer_index];
141
142 saddr = addr >> 2;
143 switch (saddr) {
144 case TIMER_LIMIT:
145 // read limit (system counter mode) or read most signifying
146 // part of counter (user mode)
147 if (slavio_timer_is_user(tc)) {
148 // read user timer MSW
149 slavio_timer_get_out(t);
150 ret = t->counthigh | t->reached;
151 } else {
152 // read limit
153 // clear irq
154 qemu_irq_lower(t->irq);
155 t->reached = 0;
156 ret = t->limit & TIMER_LIMIT_MASK32;
157 }
158 break;
159 case TIMER_COUNTER:
160 // read counter and reached bit (system mode) or read lsbits
161 // of counter (user mode)
162 slavio_timer_get_out(t);
163 if (slavio_timer_is_user(tc)) { // read user timer LSW
164 ret = t->count & TIMER_MAX_COUNT64;
165 } else { // read limit
166 ret = (t->count & TIMER_MAX_COUNT32) |
167 t->reached;
168 }
169 break;
170 case TIMER_STATUS:
171 // only available in processor counter/timer
172 // read start/stop status
173 if (timer_index > 0) {
174 ret = t->running;
175 } else {
176 ret = 0;
177 }
178 break;
179 case TIMER_MODE:
180 // only available in system counter
181 // read user/system mode
182 ret = s->cputimer_mode;
183 break;
184 default:
185 trace_slavio_timer_mem_readl_invalid(addr);
186 ret = 0;
187 break;
188 }
189 trace_slavio_timer_mem_readl(addr, ret);
190 return ret;
191 }
192
193 static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr,
194 uint64_t val, unsigned size)
195 {
196 TimerContext *tc = opaque;
197 SLAVIO_TIMERState *s = tc->s;
198 uint32_t saddr;
199 unsigned int timer_index = tc->timer_index;
200 CPUTimerState *t = &s->cputimer[timer_index];
201
202 trace_slavio_timer_mem_writel(addr, val);
203 saddr = addr >> 2;
204 switch (saddr) {
205 case TIMER_LIMIT:
206 if (slavio_timer_is_user(tc)) {
207 uint64_t count;
208
209 // set user counter MSW, reset counter
210 t->limit = TIMER_MAX_COUNT64;
211 t->counthigh = val & (TIMER_MAX_COUNT64 >> 32);
212 t->reached = 0;
213 count = ((uint64_t)t->counthigh << 32) | t->count;
214 trace_slavio_timer_mem_writel_limit(timer_index, count);
215 ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count));
216 } else {
217 // set limit, reset counter
218 qemu_irq_lower(t->irq);
219 t->limit = val & TIMER_MAX_COUNT32;
220 if (t->timer) {
221 if (t->limit == 0) { /* free-run */
222 ptimer_set_limit(t->timer,
223 LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1);
224 } else {
225 ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 1);
226 }
227 }
228 }
229 break;
230 case TIMER_COUNTER:
231 if (slavio_timer_is_user(tc)) {
232 uint64_t count;
233
234 // set user counter LSW, reset counter
235 t->limit = TIMER_MAX_COUNT64;
236 t->count = val & TIMER_MAX_COUNT64;
237 t->reached = 0;
238 count = ((uint64_t)t->counthigh) << 32 | t->count;
239 trace_slavio_timer_mem_writel_limit(timer_index, count);
240 ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count));
241 } else {
242 trace_slavio_timer_mem_writel_counter_invalid();
243 }
244 break;
245 case TIMER_COUNTER_NORST:
246 // set limit without resetting counter
247 t->limit = val & TIMER_MAX_COUNT32;
248 if (t->limit == 0) { /* free-run */
249 ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 0);
250 } else {
251 ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 0);
252 }
253 break;
254 case TIMER_STATUS:
255 if (slavio_timer_is_user(tc)) {
256 // start/stop user counter
257 if ((val & 1) && !t->running) {
258 trace_slavio_timer_mem_writel_status_start(timer_index);
259 ptimer_run(t->timer, 0);
260 t->running = 1;
261 } else if (!(val & 1) && t->running) {
262 trace_slavio_timer_mem_writel_status_stop(timer_index);
263 ptimer_stop(t->timer);
264 t->running = 0;
265 }
266 }
267 break;
268 case TIMER_MODE:
269 if (timer_index == 0) {
270 unsigned int i;
271
272 for (i = 0; i < s->num_cpus; i++) {
273 unsigned int processor = 1 << i;
274 CPUTimerState *curr_timer = &s->cputimer[i + 1];
275
276 // check for a change in timer mode for this processor
277 if ((val & processor) != (s->cputimer_mode & processor)) {
278 if (val & processor) { // counter -> user timer
279 qemu_irq_lower(curr_timer->irq);
280 // counters are always running
281 ptimer_stop(curr_timer->timer);
282 curr_timer->running = 0;
283 // user timer limit is always the same
284 curr_timer->limit = TIMER_MAX_COUNT64;
285 ptimer_set_limit(curr_timer->timer,
286 LIMIT_TO_PERIODS(curr_timer->limit),
287 1);
288 // set this processors user timer bit in config
289 // register
290 s->cputimer_mode |= processor;
291 trace_slavio_timer_mem_writel_mode_user(timer_index);
292 } else { // user timer -> counter
293 // stop the user timer if it is running
294 if (curr_timer->running) {
295 ptimer_stop(curr_timer->timer);
296 }
297 // start the counter
298 ptimer_run(curr_timer->timer, 0);
299 curr_timer->running = 1;
300 // clear this processors user timer bit in config
301 // register
302 s->cputimer_mode &= ~processor;
303 trace_slavio_timer_mem_writel_mode_counter(timer_index);
304 }
305 }
306 }
307 } else {
308 trace_slavio_timer_mem_writel_mode_invalid();
309 }
310 break;
311 default:
312 trace_slavio_timer_mem_writel_invalid(addr);
313 break;
314 }
315 }
316
317 static const MemoryRegionOps slavio_timer_mem_ops = {
318 .read = slavio_timer_mem_readl,
319 .write = slavio_timer_mem_writel,
320 .endianness = DEVICE_NATIVE_ENDIAN,
321 .valid = {
322 .min_access_size = 4,
323 .max_access_size = 4,
324 },
325 };
326
327 static const VMStateDescription vmstate_timer = {
328 .name ="timer",
329 .version_id = 3,
330 .minimum_version_id = 3,
331 .minimum_version_id_old = 3,
332 .fields = (VMStateField []) {
333 VMSTATE_UINT64(limit, CPUTimerState),
334 VMSTATE_UINT32(count, CPUTimerState),
335 VMSTATE_UINT32(counthigh, CPUTimerState),
336 VMSTATE_UINT32(reached, CPUTimerState),
337 VMSTATE_UINT32(running, CPUTimerState),
338 VMSTATE_PTIMER(timer, CPUTimerState),
339 VMSTATE_END_OF_LIST()
340 }
341 };
342
343 static const VMStateDescription vmstate_slavio_timer = {
344 .name ="slavio_timer",
345 .version_id = 3,
346 .minimum_version_id = 3,
347 .minimum_version_id_old = 3,
348 .fields = (VMStateField []) {
349 VMSTATE_STRUCT_ARRAY(cputimer, SLAVIO_TIMERState, MAX_CPUS + 1, 3,
350 vmstate_timer, CPUTimerState),
351 VMSTATE_END_OF_LIST()
352 }
353 };
354
355 static void slavio_timer_reset(DeviceState *d)
356 {
357 SLAVIO_TIMERState *s = container_of(d, SLAVIO_TIMERState, busdev.qdev);
358 unsigned int i;
359 CPUTimerState *curr_timer;
360
361 for (i = 0; i <= MAX_CPUS; i++) {
362 curr_timer = &s->cputimer[i];
363 curr_timer->limit = 0;
364 curr_timer->count = 0;
365 curr_timer->reached = 0;
366 if (i <= s->num_cpus) {
367 ptimer_set_limit(curr_timer->timer,
368 LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1);
369 ptimer_run(curr_timer->timer, 0);
370 curr_timer->running = 1;
371 }
372 }
373 s->cputimer_mode = 0;
374 }
375
376 static int slavio_timer_init1(SysBusDevice *dev)
377 {
378 SLAVIO_TIMERState *s = FROM_SYSBUS(SLAVIO_TIMERState, dev);
379 QEMUBH *bh;
380 unsigned int i;
381 TimerContext *tc;
382
383 for (i = 0; i <= MAX_CPUS; i++) {
384 uint64_t size;
385 char timer_name[20];
386
387 tc = g_malloc0(sizeof(TimerContext));
388 tc->s = s;
389 tc->timer_index = i;
390
391 bh = qemu_bh_new(slavio_timer_irq, tc);
392 s->cputimer[i].timer = ptimer_init(bh);
393 ptimer_set_period(s->cputimer[i].timer, TIMER_PERIOD);
394
395 size = i == 0 ? SYS_TIMER_SIZE : CPU_TIMER_SIZE;
396 snprintf(timer_name, sizeof(timer_name), "timer-%i", i);
397 memory_region_init_io(&tc->iomem, &slavio_timer_mem_ops, tc,
398 timer_name, size);
399 sysbus_init_mmio(dev, &tc->iomem);
400
401 sysbus_init_irq(dev, &s->cputimer[i].irq);
402 }
403
404 return 0;
405 }
406
407 static Property slavio_timer_properties[] = {
408 DEFINE_PROP_UINT32("num_cpus", SLAVIO_TIMERState, num_cpus, 0),
409 DEFINE_PROP_END_OF_LIST(),
410 };
411
412 static void slavio_timer_class_init(ObjectClass *klass, void *data)
413 {
414 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
415
416 k->init = slavio_timer_init1;
417 }
418
419 static DeviceInfo slavio_timer_info = {
420 .name = "slavio_timer",
421 .size = sizeof(SLAVIO_TIMERState),
422 .vmsd = &vmstate_slavio_timer,
423 .reset = slavio_timer_reset,
424 .props = slavio_timer_properties,
425 .class_init = slavio_timer_class_init,
426 };
427
428 static void slavio_timer_register_devices(void)
429 {
430 sysbus_register_withprop(&slavio_timer_info);
431 }
432
433 device_init(slavio_timer_register_devices)