linux-user: stack_base is now mandatory on all targets
[qemu.git] / hw / spapr.c
1 /*
2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
3 *
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 *
26 */
27 #include "sysemu.h"
28 #include "hw.h"
29 #include "elf.h"
30 #include "net.h"
31 #include "blockdev.h"
32 #include "cpus.h"
33 #include "kvm.h"
34 #include "kvm_ppc.h"
35
36 #include "hw/boards.h"
37 #include "hw/ppc.h"
38 #include "hw/loader.h"
39
40 #include "hw/spapr.h"
41 #include "hw/spapr_vio.h"
42 #include "hw/spapr_pci.h"
43 #include "hw/xics.h"
44
45 #include "kvm.h"
46 #include "kvm_ppc.h"
47 #include "pci.h"
48
49 #include "exec-memory.h"
50
51 #include <libfdt.h>
52
53 /* SLOF memory layout:
54 *
55 * SLOF raw image loaded at 0, copies its romfs right below the flat
56 * device-tree, then position SLOF itself 31M below that
57 *
58 * So we set FW_OVERHEAD to 40MB which should account for all of that
59 * and more
60 *
61 * We load our kernel at 4M, leaving space for SLOF initial image
62 */
63 #define FDT_MAX_SIZE 0x10000
64 #define RTAS_MAX_SIZE 0x10000
65 #define FW_MAX_SIZE 0x400000
66 #define FW_FILE_NAME "slof.bin"
67 #define FW_OVERHEAD 0x2800000
68 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
69
70 #define MIN_RMA_SLOF 128UL
71
72 #define TIMEBASE_FREQ 512000000ULL
73
74 #define MAX_CPUS 256
75 #define XICS_IRQS 1024
76
77 #define SPAPR_PCI_BUID 0x800000020000001ULL
78 #define SPAPR_PCI_MEM_WIN_ADDR (0x10000000000ULL + 0xA0000000)
79 #define SPAPR_PCI_MEM_WIN_SIZE 0x20000000
80 #define SPAPR_PCI_IO_WIN_ADDR (0x10000000000ULL + 0x80000000)
81
82 #define PHANDLE_XICP 0x00001111
83
84 sPAPREnvironment *spapr;
85
86 qemu_irq spapr_allocate_irq(uint32_t hint, uint32_t *irq_num)
87 {
88 uint32_t irq;
89 qemu_irq qirq;
90
91 if (hint) {
92 irq = hint;
93 /* FIXME: we should probably check for collisions somehow */
94 } else {
95 irq = spapr->next_irq++;
96 }
97
98 qirq = xics_find_qirq(spapr->icp, irq);
99 if (!qirq) {
100 return NULL;
101 }
102
103 if (irq_num) {
104 *irq_num = irq;
105 }
106
107 return qirq;
108 }
109
110 static int spapr_set_associativity(void *fdt, sPAPREnvironment *spapr)
111 {
112 int ret = 0, offset;
113 CPUState *env;
114 char cpu_model[32];
115 int smt = kvmppc_smt_threads();
116
117 assert(spapr->cpu_model);
118
119 for (env = first_cpu; env != NULL; env = env->next_cpu) {
120 uint32_t associativity[] = {cpu_to_be32(0x5),
121 cpu_to_be32(0x0),
122 cpu_to_be32(0x0),
123 cpu_to_be32(0x0),
124 cpu_to_be32(env->numa_node),
125 cpu_to_be32(env->cpu_index)};
126
127 if ((env->cpu_index % smt) != 0) {
128 continue;
129 }
130
131 snprintf(cpu_model, 32, "/cpus/%s@%x", spapr->cpu_model,
132 env->cpu_index);
133
134 offset = fdt_path_offset(fdt, cpu_model);
135 if (offset < 0) {
136 return offset;
137 }
138
139 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity,
140 sizeof(associativity));
141 if (ret < 0) {
142 return ret;
143 }
144 }
145 return ret;
146 }
147
148 static void *spapr_create_fdt_skel(const char *cpu_model,
149 target_phys_addr_t rma_size,
150 target_phys_addr_t initrd_base,
151 target_phys_addr_t initrd_size,
152 target_phys_addr_t kernel_size,
153 const char *boot_device,
154 const char *kernel_cmdline,
155 long hash_shift)
156 {
157 void *fdt;
158 CPUState *env;
159 uint64_t mem_reg_property[2];
160 uint32_t start_prop = cpu_to_be32(initrd_base);
161 uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size);
162 uint32_t pft_size_prop[] = {0, cpu_to_be32(hash_shift)};
163 char hypertas_prop[] = "hcall-pft\0hcall-term\0hcall-dabr\0hcall-interrupt"
164 "\0hcall-tce\0hcall-vio\0hcall-splpar\0hcall-bulk";
165 uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(smp_cpus)};
166 int i;
167 char *modelname;
168 int smt = kvmppc_smt_threads();
169 unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80};
170 uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)};
171 uint32_t associativity[] = {cpu_to_be32(0x4), cpu_to_be32(0x0),
172 cpu_to_be32(0x0), cpu_to_be32(0x0),
173 cpu_to_be32(0x0)};
174 char mem_name[32];
175 target_phys_addr_t node0_size, mem_start;
176
177 #define _FDT(exp) \
178 do { \
179 int ret = (exp); \
180 if (ret < 0) { \
181 fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \
182 #exp, fdt_strerror(ret)); \
183 exit(1); \
184 } \
185 } while (0)
186
187 fdt = g_malloc0(FDT_MAX_SIZE);
188 _FDT((fdt_create(fdt, FDT_MAX_SIZE)));
189
190 if (kernel_size) {
191 _FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size)));
192 }
193 if (initrd_size) {
194 _FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size)));
195 }
196 _FDT((fdt_finish_reservemap(fdt)));
197
198 /* Root node */
199 _FDT((fdt_begin_node(fdt, "")));
200 _FDT((fdt_property_string(fdt, "device_type", "chrp")));
201 _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)")));
202
203 _FDT((fdt_property_cell(fdt, "#address-cells", 0x2)));
204 _FDT((fdt_property_cell(fdt, "#size-cells", 0x2)));
205
206 /* /chosen */
207 _FDT((fdt_begin_node(fdt, "chosen")));
208
209 /* Set Form1_affinity */
210 _FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5))));
211
212 _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline)));
213 _FDT((fdt_property(fdt, "linux,initrd-start",
214 &start_prop, sizeof(start_prop))));
215 _FDT((fdt_property(fdt, "linux,initrd-end",
216 &end_prop, sizeof(end_prop))));
217 if (kernel_size) {
218 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR),
219 cpu_to_be64(kernel_size) };
220
221 _FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop))));
222 }
223 _FDT((fdt_property_string(fdt, "qemu,boot-device", boot_device)));
224
225 _FDT((fdt_end_node(fdt)));
226
227 /* memory node(s) */
228 node0_size = (nb_numa_nodes > 1) ? node_mem[0] : ram_size;
229 if (rma_size > node0_size) {
230 rma_size = node0_size;
231 }
232
233 /* RMA */
234 mem_reg_property[0] = 0;
235 mem_reg_property[1] = cpu_to_be64(rma_size);
236 _FDT((fdt_begin_node(fdt, "memory@0")));
237 _FDT((fdt_property_string(fdt, "device_type", "memory")));
238 _FDT((fdt_property(fdt, "reg", mem_reg_property,
239 sizeof(mem_reg_property))));
240 _FDT((fdt_property(fdt, "ibm,associativity", associativity,
241 sizeof(associativity))));
242 _FDT((fdt_end_node(fdt)));
243
244 /* RAM: Node 0 */
245 if (node0_size > rma_size) {
246 mem_reg_property[0] = cpu_to_be64(rma_size);
247 mem_reg_property[1] = cpu_to_be64(node0_size - rma_size);
248
249 sprintf(mem_name, "memory@" TARGET_FMT_lx, rma_size);
250 _FDT((fdt_begin_node(fdt, mem_name)));
251 _FDT((fdt_property_string(fdt, "device_type", "memory")));
252 _FDT((fdt_property(fdt, "reg", mem_reg_property,
253 sizeof(mem_reg_property))));
254 _FDT((fdt_property(fdt, "ibm,associativity", associativity,
255 sizeof(associativity))));
256 _FDT((fdt_end_node(fdt)));
257 }
258
259 /* RAM: Node 1 and beyond */
260 mem_start = node0_size;
261 for (i = 1; i < nb_numa_nodes; i++) {
262 mem_reg_property[0] = cpu_to_be64(mem_start);
263 mem_reg_property[1] = cpu_to_be64(node_mem[i]);
264 associativity[3] = associativity[4] = cpu_to_be32(i);
265 sprintf(mem_name, "memory@" TARGET_FMT_lx, mem_start);
266 _FDT((fdt_begin_node(fdt, mem_name)));
267 _FDT((fdt_property_string(fdt, "device_type", "memory")));
268 _FDT((fdt_property(fdt, "reg", mem_reg_property,
269 sizeof(mem_reg_property))));
270 _FDT((fdt_property(fdt, "ibm,associativity", associativity,
271 sizeof(associativity))));
272 _FDT((fdt_end_node(fdt)));
273 mem_start += node_mem[i];
274 }
275
276 /* cpus */
277 _FDT((fdt_begin_node(fdt, "cpus")));
278
279 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1)));
280 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0)));
281
282 modelname = g_strdup(cpu_model);
283
284 for (i = 0; i < strlen(modelname); i++) {
285 modelname[i] = toupper(modelname[i]);
286 }
287
288 /* This is needed during FDT finalization */
289 spapr->cpu_model = g_strdup(modelname);
290
291 for (env = first_cpu; env != NULL; env = env->next_cpu) {
292 int index = env->cpu_index;
293 uint32_t servers_prop[smp_threads];
294 uint32_t gservers_prop[smp_threads * 2];
295 char *nodename;
296 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
297 0xffffffff, 0xffffffff};
298 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ;
299 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
300
301 if ((index % smt) != 0) {
302 continue;
303 }
304
305 if (asprintf(&nodename, "%s@%x", modelname, index) < 0) {
306 fprintf(stderr, "Allocation failure\n");
307 exit(1);
308 }
309
310 _FDT((fdt_begin_node(fdt, nodename)));
311
312 free(nodename);
313
314 _FDT((fdt_property_cell(fdt, "reg", index)));
315 _FDT((fdt_property_string(fdt, "device_type", "cpu")));
316
317 _FDT((fdt_property_cell(fdt, "cpu-version", env->spr[SPR_PVR])));
318 _FDT((fdt_property_cell(fdt, "dcache-block-size",
319 env->dcache_line_size)));
320 _FDT((fdt_property_cell(fdt, "icache-block-size",
321 env->icache_line_size)));
322 _FDT((fdt_property_cell(fdt, "timebase-frequency", tbfreq)));
323 _FDT((fdt_property_cell(fdt, "clock-frequency", cpufreq)));
324 _FDT((fdt_property_cell(fdt, "ibm,slb-size", env->slb_nr)));
325 _FDT((fdt_property(fdt, "ibm,pft-size",
326 pft_size_prop, sizeof(pft_size_prop))));
327 _FDT((fdt_property_string(fdt, "status", "okay")));
328 _FDT((fdt_property(fdt, "64-bit", NULL, 0)));
329
330 /* Build interrupt servers and gservers properties */
331 for (i = 0; i < smp_threads; i++) {
332 servers_prop[i] = cpu_to_be32(index + i);
333 /* Hack, direct the group queues back to cpu 0 */
334 gservers_prop[i*2] = cpu_to_be32(index + i);
335 gservers_prop[i*2 + 1] = 0;
336 }
337 _FDT((fdt_property(fdt, "ibm,ppc-interrupt-server#s",
338 servers_prop, sizeof(servers_prop))));
339 _FDT((fdt_property(fdt, "ibm,ppc-interrupt-gserver#s",
340 gservers_prop, sizeof(gservers_prop))));
341
342 if (env->mmu_model & POWERPC_MMU_1TSEG) {
343 _FDT((fdt_property(fdt, "ibm,processor-segment-sizes",
344 segs, sizeof(segs))));
345 }
346
347 /* Advertise VMX/VSX (vector extensions) if available
348 * 0 / no property == no vector extensions
349 * 1 == VMX / Altivec available
350 * 2 == VSX available */
351 if (env->insns_flags & PPC_ALTIVEC) {
352 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
353
354 _FDT((fdt_property_cell(fdt, "ibm,vmx", vmx)));
355 }
356
357 /* Advertise DFP (Decimal Floating Point) if available
358 * 0 / no property == no DFP
359 * 1 == DFP available */
360 if (env->insns_flags2 & PPC2_DFP) {
361 _FDT((fdt_property_cell(fdt, "ibm,dfp", 1)));
362 }
363
364 _FDT((fdt_end_node(fdt)));
365 }
366
367 g_free(modelname);
368
369 _FDT((fdt_end_node(fdt)));
370
371 /* RTAS */
372 _FDT((fdt_begin_node(fdt, "rtas")));
373
374 _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas_prop,
375 sizeof(hypertas_prop))));
376
377 _FDT((fdt_property(fdt, "ibm,associativity-reference-points",
378 refpoints, sizeof(refpoints))));
379
380 _FDT((fdt_end_node(fdt)));
381
382 /* interrupt controller */
383 _FDT((fdt_begin_node(fdt, "interrupt-controller")));
384
385 _FDT((fdt_property_string(fdt, "device_type",
386 "PowerPC-External-Interrupt-Presentation")));
387 _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp")));
388 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
389 _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges",
390 interrupt_server_ranges_prop,
391 sizeof(interrupt_server_ranges_prop))));
392 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2)));
393 _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP)));
394 _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP)));
395
396 _FDT((fdt_end_node(fdt)));
397
398 /* vdevice */
399 _FDT((fdt_begin_node(fdt, "vdevice")));
400
401 _FDT((fdt_property_string(fdt, "device_type", "vdevice")));
402 _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice")));
403 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1)));
404 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0)));
405 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2)));
406 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
407
408 _FDT((fdt_end_node(fdt)));
409
410 _FDT((fdt_end_node(fdt))); /* close root node */
411 _FDT((fdt_finish(fdt)));
412
413 return fdt;
414 }
415
416 static void spapr_finalize_fdt(sPAPREnvironment *spapr,
417 target_phys_addr_t fdt_addr,
418 target_phys_addr_t rtas_addr,
419 target_phys_addr_t rtas_size)
420 {
421 int ret;
422 void *fdt;
423 sPAPRPHBState *phb;
424
425 fdt = g_malloc(FDT_MAX_SIZE);
426
427 /* open out the base tree into a temp buffer for the final tweaks */
428 _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE)));
429
430 ret = spapr_populate_vdevice(spapr->vio_bus, fdt);
431 if (ret < 0) {
432 fprintf(stderr, "couldn't setup vio devices in fdt\n");
433 exit(1);
434 }
435
436 QLIST_FOREACH(phb, &spapr->phbs, list) {
437 ret = spapr_populate_pci_devices(phb, PHANDLE_XICP, fdt);
438 }
439
440 if (ret < 0) {
441 fprintf(stderr, "couldn't setup PCI devices in fdt\n");
442 exit(1);
443 }
444
445 /* RTAS */
446 ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size);
447 if (ret < 0) {
448 fprintf(stderr, "Couldn't set up RTAS device tree properties\n");
449 }
450
451 /* Advertise NUMA via ibm,associativity */
452 if (nb_numa_nodes > 1) {
453 ret = spapr_set_associativity(fdt, spapr);
454 if (ret < 0) {
455 fprintf(stderr, "Couldn't set up NUMA device tree properties\n");
456 }
457 }
458
459 spapr_populate_chosen_stdout(fdt, spapr->vio_bus);
460
461 _FDT((fdt_pack(fdt)));
462
463 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) {
464 hw_error("FDT too big ! 0x%x bytes (max is 0x%x)\n",
465 fdt_totalsize(fdt), FDT_MAX_SIZE);
466 exit(1);
467 }
468
469 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
470
471 g_free(fdt);
472 }
473
474 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
475 {
476 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
477 }
478
479 static void emulate_spapr_hypercall(CPUState *env)
480 {
481 env->gpr[3] = spapr_hypercall(env, env->gpr[3], &env->gpr[4]);
482 }
483
484 static void spapr_reset(void *opaque)
485 {
486 sPAPREnvironment *spapr = (sPAPREnvironment *)opaque;
487
488 fprintf(stderr, "sPAPR reset\n");
489
490 /* flush out the hash table */
491 memset(spapr->htab, 0, spapr->htab_size);
492
493 /* Load the fdt */
494 spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr,
495 spapr->rtas_size);
496
497 /* Set up the entry state */
498 first_cpu->gpr[3] = spapr->fdt_addr;
499 first_cpu->gpr[5] = 0;
500 first_cpu->halted = 0;
501 first_cpu->nip = spapr->entry_point;
502
503 }
504
505 /* pSeries LPAR / sPAPR hardware init */
506 static void ppc_spapr_init(ram_addr_t ram_size,
507 const char *boot_device,
508 const char *kernel_filename,
509 const char *kernel_cmdline,
510 const char *initrd_filename,
511 const char *cpu_model)
512 {
513 CPUState *env;
514 int i;
515 MemoryRegion *sysmem = get_system_memory();
516 MemoryRegion *ram = g_new(MemoryRegion, 1);
517 target_phys_addr_t rma_alloc_size, rma_size;
518 uint32_t initrd_base = 0;
519 long kernel_size = 0, initrd_size = 0;
520 long load_limit, rtas_limit, fw_size;
521 long pteg_shift = 17;
522 char *filename;
523
524 spapr = g_malloc0(sizeof(*spapr));
525 QLIST_INIT(&spapr->phbs);
526
527 cpu_ppc_hypercall = emulate_spapr_hypercall;
528
529 /* Allocate RMA if necessary */
530 rma_alloc_size = kvmppc_alloc_rma("ppc_spapr.rma", sysmem);
531
532 if (rma_alloc_size == -1) {
533 hw_error("qemu: Unable to create RMA\n");
534 exit(1);
535 }
536 if (rma_alloc_size && (rma_alloc_size < ram_size)) {
537 rma_size = rma_alloc_size;
538 } else {
539 rma_size = ram_size;
540 }
541
542 /* We place the device tree and RTAS just below either the top of the RMA,
543 * or just below 2GB, whichever is lowere, so that it can be
544 * processed with 32-bit real mode code if necessary */
545 rtas_limit = MIN(rma_size, 0x80000000);
546 spapr->rtas_addr = rtas_limit - RTAS_MAX_SIZE;
547 spapr->fdt_addr = spapr->rtas_addr - FDT_MAX_SIZE;
548 load_limit = spapr->fdt_addr - FW_OVERHEAD;
549
550 /* init CPUs */
551 if (cpu_model == NULL) {
552 cpu_model = kvm_enabled() ? "host" : "POWER7";
553 }
554 for (i = 0; i < smp_cpus; i++) {
555 env = cpu_init(cpu_model);
556
557 if (!env) {
558 fprintf(stderr, "Unable to find PowerPC CPU definition\n");
559 exit(1);
560 }
561 /* Set time-base frequency to 512 MHz */
562 cpu_ppc_tb_init(env, TIMEBASE_FREQ);
563 qemu_register_reset((QEMUResetHandler *)&cpu_reset, env);
564
565 env->hreset_vector = 0x60;
566 env->hreset_excp_prefix = 0;
567 env->gpr[3] = env->cpu_index;
568 }
569
570 /* allocate RAM */
571 spapr->ram_limit = ram_size;
572 if (spapr->ram_limit > rma_alloc_size) {
573 ram_addr_t nonrma_base = rma_alloc_size;
574 ram_addr_t nonrma_size = spapr->ram_limit - rma_alloc_size;
575
576 memory_region_init_ram(ram, "ppc_spapr.ram", nonrma_size);
577 vmstate_register_ram_global(ram);
578 memory_region_add_subregion(sysmem, nonrma_base, ram);
579 }
580
581 /* allocate hash page table. For now we always make this 16mb,
582 * later we should probably make it scale to the size of guest
583 * RAM */
584 spapr->htab_size = 1ULL << (pteg_shift + 7);
585 spapr->htab = qemu_memalign(spapr->htab_size, spapr->htab_size);
586
587 for (env = first_cpu; env != NULL; env = env->next_cpu) {
588 env->external_htab = spapr->htab;
589 env->htab_base = -1;
590 env->htab_mask = spapr->htab_size - 1;
591
592 /* Tell KVM that we're in PAPR mode */
593 env->spr[SPR_SDR1] = (unsigned long)spapr->htab |
594 ((pteg_shift + 7) - 18);
595 env->spr[SPR_HIOR] = 0;
596
597 if (kvm_enabled()) {
598 kvmppc_set_papr(env);
599 }
600 }
601
602 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
603 spapr->rtas_size = load_image_targphys(filename, spapr->rtas_addr,
604 rtas_limit - spapr->rtas_addr);
605 if (spapr->rtas_size < 0) {
606 hw_error("qemu: could not load LPAR rtas '%s'\n", filename);
607 exit(1);
608 }
609 if (spapr->rtas_size > RTAS_MAX_SIZE) {
610 hw_error("RTAS too big ! 0x%lx bytes (max is 0x%x)\n",
611 spapr->rtas_size, RTAS_MAX_SIZE);
612 exit(1);
613 }
614 g_free(filename);
615
616
617 /* Set up Interrupt Controller */
618 spapr->icp = xics_system_init(XICS_IRQS);
619 spapr->next_irq = 16;
620
621 /* Set up VIO bus */
622 spapr->vio_bus = spapr_vio_bus_init();
623
624 for (i = 0; i < MAX_SERIAL_PORTS; i++) {
625 if (serial_hds[i]) {
626 spapr_vty_create(spapr->vio_bus, SPAPR_VTY_BASE_ADDRESS + i,
627 serial_hds[i]);
628 }
629 }
630
631 /* Set up PCI */
632 spapr_create_phb(spapr, "pci", SPAPR_PCI_BUID,
633 SPAPR_PCI_MEM_WIN_ADDR,
634 SPAPR_PCI_MEM_WIN_SIZE,
635 SPAPR_PCI_IO_WIN_ADDR);
636
637 for (i = 0; i < nb_nics; i++) {
638 NICInfo *nd = &nd_table[i];
639
640 if (!nd->model) {
641 nd->model = g_strdup("ibmveth");
642 }
643
644 if (strcmp(nd->model, "ibmveth") == 0) {
645 spapr_vlan_create(spapr->vio_bus, 0x1000 + i, nd);
646 } else {
647 pci_nic_init_nofail(&nd_table[i], nd->model, NULL);
648 }
649 }
650
651 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
652 spapr_vscsi_create(spapr->vio_bus, 0x2000 + i);
653 }
654
655 if (rma_size < (MIN_RMA_SLOF << 20)) {
656 fprintf(stderr, "qemu: pSeries SLOF firmware requires >= "
657 "%ldM guest RMA (Real Mode Area memory)\n", MIN_RMA_SLOF);
658 exit(1);
659 }
660
661 fprintf(stderr, "sPAPR memory map:\n");
662 fprintf(stderr, "RTAS : 0x%08lx..%08lx\n",
663 (unsigned long)spapr->rtas_addr,
664 (unsigned long)(spapr->rtas_addr + spapr->rtas_size - 1));
665 fprintf(stderr, "FDT : 0x%08lx..%08lx\n",
666 (unsigned long)spapr->fdt_addr,
667 (unsigned long)(spapr->fdt_addr + FDT_MAX_SIZE - 1));
668
669 if (kernel_filename) {
670 uint64_t lowaddr = 0;
671
672 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
673 NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0);
674 if (kernel_size < 0) {
675 kernel_size = load_image_targphys(kernel_filename,
676 KERNEL_LOAD_ADDR,
677 load_limit - KERNEL_LOAD_ADDR);
678 }
679 if (kernel_size < 0) {
680 fprintf(stderr, "qemu: could not load kernel '%s'\n",
681 kernel_filename);
682 exit(1);
683 }
684 fprintf(stderr, "Kernel : 0x%08x..%08lx\n",
685 KERNEL_LOAD_ADDR, KERNEL_LOAD_ADDR + kernel_size - 1);
686
687 /* load initrd */
688 if (initrd_filename) {
689 /* Try to locate the initrd in the gap between the kernel
690 * and the firmware. Add a bit of space just in case
691 */
692 initrd_base = (KERNEL_LOAD_ADDR + kernel_size + 0x1ffff) & ~0xffff;
693 initrd_size = load_image_targphys(initrd_filename, initrd_base,
694 load_limit - initrd_base);
695 if (initrd_size < 0) {
696 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
697 initrd_filename);
698 exit(1);
699 }
700 fprintf(stderr, "Ramdisk : 0x%08lx..%08lx\n",
701 (long)initrd_base, (long)(initrd_base + initrd_size - 1));
702 } else {
703 initrd_base = 0;
704 initrd_size = 0;
705 }
706 }
707
708 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, FW_FILE_NAME);
709 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
710 if (fw_size < 0) {
711 hw_error("qemu: could not load LPAR rtas '%s'\n", filename);
712 exit(1);
713 }
714 g_free(filename);
715 fprintf(stderr, "Firmware load : 0x%08x..%08lx\n",
716 0, fw_size);
717 fprintf(stderr, "Firmware runtime : 0x%08lx..%08lx\n",
718 load_limit, (unsigned long)spapr->fdt_addr);
719
720 spapr->entry_point = 0x100;
721
722 /* SLOF will startup the secondary CPUs using RTAS */
723 for (env = first_cpu; env != NULL; env = env->next_cpu) {
724 env->halted = 1;
725 }
726
727 /* Prepare the device tree */
728 spapr->fdt_skel = spapr_create_fdt_skel(cpu_model, rma_size,
729 initrd_base, initrd_size,
730 kernel_size,
731 boot_device, kernel_cmdline,
732 pteg_shift + 7);
733 assert(spapr->fdt_skel != NULL);
734
735 qemu_register_reset(spapr_reset, spapr);
736 }
737
738 static QEMUMachine spapr_machine = {
739 .name = "pseries",
740 .desc = "pSeries Logical Partition (PAPR compliant)",
741 .init = ppc_spapr_init,
742 .max_cpus = MAX_CPUS,
743 .no_parallel = 1,
744 .use_scsi = 1,
745 };
746
747 static void spapr_machine_init(void)
748 {
749 qemu_register_machine(&spapr_machine);
750 }
751
752 machine_init(spapr_machine_init);