Fix version for v6.2.0-rc2 release
[qemu.git] / hw / sparc / sun4m.c
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "qapi/error.h"
28 #include "qemu/datadir.h"
29 #include "qemu-common.h"
30 #include "cpu.h"
31 #include "hw/sysbus.h"
32 #include "qemu/error-report.h"
33 #include "qemu/timer.h"
34 #include "hw/sparc/sun4m_iommu.h"
35 #include "hw/rtc/m48t59.h"
36 #include "migration/vmstate.h"
37 #include "hw/sparc/sparc32_dma.h"
38 #include "hw/block/fdc.h"
39 #include "sysemu/reset.h"
40 #include "sysemu/runstate.h"
41 #include "sysemu/sysemu.h"
42 #include "net/net.h"
43 #include "hw/boards.h"
44 #include "hw/scsi/esp.h"
45 #include "hw/nvram/sun_nvram.h"
46 #include "hw/qdev-properties.h"
47 #include "hw/nvram/chrp_nvram.h"
48 #include "hw/nvram/fw_cfg.h"
49 #include "hw/char/escc.h"
50 #include "hw/misc/empty_slot.h"
51 #include "hw/misc/unimp.h"
52 #include "hw/irq.h"
53 #include "hw/or-irq.h"
54 #include "hw/loader.h"
55 #include "elf.h"
56 #include "trace.h"
57 #include "qom/object.h"
58
59 /*
60 * Sun4m architecture was used in the following machines:
61 *
62 * SPARCserver 6xxMP/xx
63 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
64 * SPARCclassic X (4/10)
65 * SPARCstation LX/ZX (4/30)
66 * SPARCstation Voyager
67 * SPARCstation 10/xx, SPARCserver 10/xx
68 * SPARCstation 5, SPARCserver 5
69 * SPARCstation 20/xx, SPARCserver 20
70 * SPARCstation 4
71 *
72 * See for example: http://www.sunhelp.org/faq/sunref1.html
73 */
74
75 #define KERNEL_LOAD_ADDR 0x00004000
76 #define CMDLINE_ADDR 0x007ff000
77 #define INITRD_LOAD_ADDR 0x00800000
78 #define PROM_SIZE_MAX (1 * MiB)
79 #define PROM_VADDR 0xffd00000
80 #define PROM_FILENAME "openbios-sparc32"
81 #define CFG_ADDR 0xd00000510ULL
82 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
83 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01)
84 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02)
85
86 #define MAX_CPUS 16
87 #define MAX_PILS 16
88 #define MAX_VSIMMS 4
89
90 #define ESCC_CLOCK 4915200
91
92 struct sun4m_hwdef {
93 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
94 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base;
95 hwaddr serial_base, fd_base;
96 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base;
97 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base;
98 hwaddr bpp_base, dbri_base, sx_base;
99 struct {
100 hwaddr reg_base, vram_base;
101 } vsimm[MAX_VSIMMS];
102 hwaddr ecc_base;
103 uint64_t max_mem;
104 uint32_t ecc_version;
105 uint32_t iommu_version;
106 uint16_t machine_id;
107 uint8_t nvram_machine_id;
108 };
109
110 struct Sun4mMachineClass {
111 /*< private >*/
112 MachineClass parent_obj;
113 /*< public >*/
114 const struct sun4m_hwdef *hwdef;
115 };
116 typedef struct Sun4mMachineClass Sun4mMachineClass;
117
118 #define TYPE_SUN4M_MACHINE MACHINE_TYPE_NAME("sun4m-common")
119 DECLARE_CLASS_CHECKERS(Sun4mMachineClass, SUN4M_MACHINE, TYPE_SUN4M_MACHINE)
120
121 const char *fw_cfg_arch_key_name(uint16_t key)
122 {
123 static const struct {
124 uint16_t key;
125 const char *name;
126 } fw_cfg_arch_wellknown_keys[] = {
127 {FW_CFG_SUN4M_DEPTH, "depth"},
128 {FW_CFG_SUN4M_WIDTH, "width"},
129 {FW_CFG_SUN4M_HEIGHT, "height"},
130 };
131
132 for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) {
133 if (fw_cfg_arch_wellknown_keys[i].key == key) {
134 return fw_cfg_arch_wellknown_keys[i].name;
135 }
136 }
137 return NULL;
138 }
139
140 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
141 Error **errp)
142 {
143 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
144 }
145
146 static void nvram_init(Nvram *nvram, uint8_t *macaddr,
147 const char *cmdline, const char *boot_devices,
148 ram_addr_t RAM_size, uint32_t kernel_size,
149 int width, int height, int depth,
150 int nvram_machine_id, const char *arch)
151 {
152 unsigned int i;
153 int sysp_end;
154 uint8_t image[0x1ff0];
155 NvramClass *k = NVRAM_GET_CLASS(nvram);
156
157 memset(image, '\0', sizeof(image));
158
159 /* OpenBIOS nvram variables partition */
160 sysp_end = chrp_nvram_create_system_partition(image, 0, 0x1fd0);
161
162 /* Free space partition */
163 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end);
164
165 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
166 nvram_machine_id);
167
168 for (i = 0; i < sizeof(image); i++) {
169 (k->write)(nvram, i, image[i]);
170 }
171 }
172
173 static void cpu_kick_irq(SPARCCPU *cpu)
174 {
175 CPUSPARCState *env = &cpu->env;
176 CPUState *cs = CPU(cpu);
177
178 cs->halted = 0;
179 cpu_check_irqs(env);
180 qemu_cpu_kick(cs);
181 }
182
183 static void cpu_set_irq(void *opaque, int irq, int level)
184 {
185 SPARCCPU *cpu = opaque;
186 CPUSPARCState *env = &cpu->env;
187
188 if (level) {
189 trace_sun4m_cpu_set_irq_raise(irq);
190 env->pil_in |= 1 << irq;
191 cpu_kick_irq(cpu);
192 } else {
193 trace_sun4m_cpu_set_irq_lower(irq);
194 env->pil_in &= ~(1 << irq);
195 cpu_check_irqs(env);
196 }
197 }
198
199 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
200 {
201 }
202
203 static void sun4m_cpu_reset(void *opaque)
204 {
205 SPARCCPU *cpu = opaque;
206 CPUState *cs = CPU(cpu);
207
208 cpu_reset(cs);
209 }
210
211 static void cpu_halt_signal(void *opaque, int irq, int level)
212 {
213 if (level && current_cpu) {
214 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT);
215 }
216 }
217
218 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
219 {
220 return addr - 0xf0000000ULL;
221 }
222
223 static unsigned long sun4m_load_kernel(const char *kernel_filename,
224 const char *initrd_filename,
225 ram_addr_t RAM_size,
226 uint32_t *initrd_size)
227 {
228 int linux_boot;
229 unsigned int i;
230 long kernel_size;
231 uint8_t *ptr;
232
233 linux_boot = (kernel_filename != NULL);
234
235 kernel_size = 0;
236 if (linux_boot) {
237 int bswap_needed;
238
239 #ifdef BSWAP_NEEDED
240 bswap_needed = 1;
241 #else
242 bswap_needed = 0;
243 #endif
244 kernel_size = load_elf(kernel_filename, NULL,
245 translate_kernel_address, NULL,
246 NULL, NULL, NULL, NULL, 1, EM_SPARC, 0, 0);
247 if (kernel_size < 0)
248 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
249 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
250 TARGET_PAGE_SIZE);
251 if (kernel_size < 0)
252 kernel_size = load_image_targphys(kernel_filename,
253 KERNEL_LOAD_ADDR,
254 RAM_size - KERNEL_LOAD_ADDR);
255 if (kernel_size < 0) {
256 error_report("could not load kernel '%s'", kernel_filename);
257 exit(1);
258 }
259
260 /* load initrd */
261 *initrd_size = 0;
262 if (initrd_filename) {
263 *initrd_size = load_image_targphys(initrd_filename,
264 INITRD_LOAD_ADDR,
265 RAM_size - INITRD_LOAD_ADDR);
266 if ((int)*initrd_size < 0) {
267 error_report("could not load initial ram disk '%s'",
268 initrd_filename);
269 exit(1);
270 }
271 }
272 if (*initrd_size > 0) {
273 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
274 ptr = rom_ptr(KERNEL_LOAD_ADDR + i, 24);
275 if (ptr && ldl_p(ptr) == 0x48647253) { /* HdrS */
276 stl_p(ptr + 16, INITRD_LOAD_ADDR);
277 stl_p(ptr + 20, *initrd_size);
278 break;
279 }
280 }
281 }
282 }
283 return kernel_size;
284 }
285
286 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq)
287 {
288 DeviceState *dev;
289 SysBusDevice *s;
290
291 dev = qdev_new(TYPE_SUN4M_IOMMU);
292 qdev_prop_set_uint32(dev, "version", version);
293 s = SYS_BUS_DEVICE(dev);
294 sysbus_realize_and_unref(s, &error_fatal);
295 sysbus_connect_irq(s, 0, irq);
296 sysbus_mmio_map(s, 0, addr);
297
298 return s;
299 }
300
301 static void *sparc32_dma_init(hwaddr dma_base,
302 hwaddr esp_base, qemu_irq espdma_irq,
303 hwaddr le_base, qemu_irq ledma_irq, NICInfo *nd)
304 {
305 DeviceState *dma;
306 ESPDMADeviceState *espdma;
307 LEDMADeviceState *ledma;
308 SysBusESPState *esp;
309 SysBusPCNetState *lance;
310
311 dma = qdev_new(TYPE_SPARC32_DMA);
312 espdma = SPARC32_ESPDMA_DEVICE(object_resolve_path_component(
313 OBJECT(dma), "espdma"));
314 sysbus_connect_irq(SYS_BUS_DEVICE(espdma), 0, espdma_irq);
315
316 esp = SYSBUS_ESP(object_resolve_path_component(OBJECT(espdma), "esp"));
317
318 ledma = SPARC32_LEDMA_DEVICE(object_resolve_path_component(
319 OBJECT(dma), "ledma"));
320 sysbus_connect_irq(SYS_BUS_DEVICE(ledma), 0, ledma_irq);
321
322 lance = SYSBUS_PCNET(object_resolve_path_component(
323 OBJECT(ledma), "lance"));
324 qdev_set_nic_properties(DEVICE(lance), nd);
325
326 sysbus_realize_and_unref(SYS_BUS_DEVICE(dma), &error_fatal);
327 sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, dma_base);
328
329 sysbus_mmio_map(SYS_BUS_DEVICE(esp), 0, esp_base);
330 scsi_bus_legacy_handle_cmdline(&esp->esp.bus);
331
332 sysbus_mmio_map(SYS_BUS_DEVICE(lance), 0, le_base);
333
334 return dma;
335 }
336
337 static DeviceState *slavio_intctl_init(hwaddr addr,
338 hwaddr addrg,
339 qemu_irq **parent_irq)
340 {
341 DeviceState *dev;
342 SysBusDevice *s;
343 unsigned int i, j;
344
345 dev = qdev_new("slavio_intctl");
346
347 s = SYS_BUS_DEVICE(dev);
348 sysbus_realize_and_unref(s, &error_fatal);
349
350 for (i = 0; i < MAX_CPUS; i++) {
351 for (j = 0; j < MAX_PILS; j++) {
352 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
353 }
354 }
355 sysbus_mmio_map(s, 0, addrg);
356 for (i = 0; i < MAX_CPUS; i++) {
357 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
358 }
359
360 return dev;
361 }
362
363 #define SYS_TIMER_OFFSET 0x10000ULL
364 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
365
366 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq,
367 qemu_irq *cpu_irqs, unsigned int num_cpus)
368 {
369 DeviceState *dev;
370 SysBusDevice *s;
371 unsigned int i;
372
373 dev = qdev_new("slavio_timer");
374 qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
375 s = SYS_BUS_DEVICE(dev);
376 sysbus_realize_and_unref(s, &error_fatal);
377 sysbus_connect_irq(s, 0, master_irq);
378 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
379
380 for (i = 0; i < MAX_CPUS; i++) {
381 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i));
382 sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
383 }
384 }
385
386 static qemu_irq slavio_system_powerdown;
387
388 static void slavio_powerdown_req(Notifier *n, void *opaque)
389 {
390 qemu_irq_raise(slavio_system_powerdown);
391 }
392
393 static Notifier slavio_system_powerdown_notifier = {
394 .notify = slavio_powerdown_req
395 };
396
397 #define MISC_LEDS 0x01600000
398 #define MISC_CFG 0x01800000
399 #define MISC_DIAG 0x01a00000
400 #define MISC_MDM 0x01b00000
401 #define MISC_SYS 0x01f00000
402
403 static void slavio_misc_init(hwaddr base,
404 hwaddr aux1_base,
405 hwaddr aux2_base, qemu_irq irq,
406 qemu_irq fdc_tc)
407 {
408 DeviceState *dev;
409 SysBusDevice *s;
410
411 dev = qdev_new("slavio_misc");
412 s = SYS_BUS_DEVICE(dev);
413 sysbus_realize_and_unref(s, &error_fatal);
414 if (base) {
415 /* 8 bit registers */
416 /* Slavio control */
417 sysbus_mmio_map(s, 0, base + MISC_CFG);
418 /* Diagnostics */
419 sysbus_mmio_map(s, 1, base + MISC_DIAG);
420 /* Modem control */
421 sysbus_mmio_map(s, 2, base + MISC_MDM);
422 /* 16 bit registers */
423 /* ss600mp diag LEDs */
424 sysbus_mmio_map(s, 3, base + MISC_LEDS);
425 /* 32 bit registers */
426 /* System control */
427 sysbus_mmio_map(s, 4, base + MISC_SYS);
428 }
429 if (aux1_base) {
430 /* AUX 1 (Misc System Functions) */
431 sysbus_mmio_map(s, 5, aux1_base);
432 }
433 if (aux2_base) {
434 /* AUX 2 (Software Powerdown Control) */
435 sysbus_mmio_map(s, 6, aux2_base);
436 }
437 sysbus_connect_irq(s, 0, irq);
438 sysbus_connect_irq(s, 1, fdc_tc);
439 slavio_system_powerdown = qdev_get_gpio_in(dev, 0);
440 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier);
441 }
442
443 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version)
444 {
445 DeviceState *dev;
446 SysBusDevice *s;
447
448 dev = qdev_new("eccmemctl");
449 qdev_prop_set_uint32(dev, "version", version);
450 s = SYS_BUS_DEVICE(dev);
451 sysbus_realize_and_unref(s, &error_fatal);
452 sysbus_connect_irq(s, 0, irq);
453 sysbus_mmio_map(s, 0, base);
454 if (version == 0) { // SS-600MP only
455 sysbus_mmio_map(s, 1, base + 0x1000);
456 }
457 }
458
459 static void apc_init(hwaddr power_base, qemu_irq cpu_halt)
460 {
461 DeviceState *dev;
462 SysBusDevice *s;
463
464 dev = qdev_new("apc");
465 s = SYS_BUS_DEVICE(dev);
466 sysbus_realize_and_unref(s, &error_fatal);
467 /* Power management (APC) XXX: not a Slavio device */
468 sysbus_mmio_map(s, 0, power_base);
469 sysbus_connect_irq(s, 0, cpu_halt);
470 }
471
472 static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
473 int height, int depth)
474 {
475 DeviceState *dev;
476 SysBusDevice *s;
477
478 dev = qdev_new("sun-tcx");
479 qdev_prop_set_uint32(dev, "vram_size", vram_size);
480 qdev_prop_set_uint16(dev, "width", width);
481 qdev_prop_set_uint16(dev, "height", height);
482 qdev_prop_set_uint16(dev, "depth", depth);
483 s = SYS_BUS_DEVICE(dev);
484 sysbus_realize_and_unref(s, &error_fatal);
485
486 /* 10/ROM : FCode ROM */
487 sysbus_mmio_map(s, 0, addr);
488 /* 2/STIP : Stipple */
489 sysbus_mmio_map(s, 1, addr + 0x04000000ULL);
490 /* 3/BLIT : Blitter */
491 sysbus_mmio_map(s, 2, addr + 0x06000000ULL);
492 /* 5/RSTIP : Raw Stipple */
493 sysbus_mmio_map(s, 3, addr + 0x0c000000ULL);
494 /* 6/RBLIT : Raw Blitter */
495 sysbus_mmio_map(s, 4, addr + 0x0e000000ULL);
496 /* 7/TEC : Transform Engine */
497 sysbus_mmio_map(s, 5, addr + 0x00700000ULL);
498 /* 8/CMAP : DAC */
499 sysbus_mmio_map(s, 6, addr + 0x00200000ULL);
500 /* 9/THC : */
501 if (depth == 8) {
502 sysbus_mmio_map(s, 7, addr + 0x00300000ULL);
503 } else {
504 sysbus_mmio_map(s, 7, addr + 0x00301000ULL);
505 }
506 /* 11/DHC : */
507 sysbus_mmio_map(s, 8, addr + 0x00240000ULL);
508 /* 12/ALT : */
509 sysbus_mmio_map(s, 9, addr + 0x00280000ULL);
510 /* 0/DFB8 : 8-bit plane */
511 sysbus_mmio_map(s, 10, addr + 0x00800000ULL);
512 /* 1/DFB24 : 24bit plane */
513 sysbus_mmio_map(s, 11, addr + 0x02000000ULL);
514 /* 4/RDFB32: Raw framebuffer. Control plane */
515 sysbus_mmio_map(s, 12, addr + 0x0a000000ULL);
516 /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */
517 if (depth == 8) {
518 sysbus_mmio_map(s, 13, addr + 0x00301000ULL);
519 }
520
521 sysbus_connect_irq(s, 0, irq);
522 }
523
524 static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
525 int height, int depth)
526 {
527 DeviceState *dev;
528 SysBusDevice *s;
529
530 dev = qdev_new("cgthree");
531 qdev_prop_set_uint32(dev, "vram-size", vram_size);
532 qdev_prop_set_uint16(dev, "width", width);
533 qdev_prop_set_uint16(dev, "height", height);
534 qdev_prop_set_uint16(dev, "depth", depth);
535 s = SYS_BUS_DEVICE(dev);
536 sysbus_realize_and_unref(s, &error_fatal);
537
538 /* FCode ROM */
539 sysbus_mmio_map(s, 0, addr);
540 /* DAC */
541 sysbus_mmio_map(s, 1, addr + 0x400000ULL);
542 /* 8-bit plane */
543 sysbus_mmio_map(s, 2, addr + 0x800000ULL);
544
545 sysbus_connect_irq(s, 0, irq);
546 }
547
548 /* NCR89C100/MACIO Internal ID register */
549
550 #define TYPE_MACIO_ID_REGISTER "macio_idreg"
551
552 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
553
554 static void idreg_init(hwaddr addr)
555 {
556 DeviceState *dev;
557 SysBusDevice *s;
558
559 dev = qdev_new(TYPE_MACIO_ID_REGISTER);
560 s = SYS_BUS_DEVICE(dev);
561 sysbus_realize_and_unref(s, &error_fatal);
562
563 sysbus_mmio_map(s, 0, addr);
564 address_space_write_rom(&address_space_memory, addr,
565 MEMTXATTRS_UNSPECIFIED,
566 idreg_data, sizeof(idreg_data));
567 }
568
569 OBJECT_DECLARE_SIMPLE_TYPE(IDRegState, MACIO_ID_REGISTER)
570
571 struct IDRegState {
572 SysBusDevice parent_obj;
573
574 MemoryRegion mem;
575 };
576
577 static void idreg_realize(DeviceState *ds, Error **errp)
578 {
579 IDRegState *s = MACIO_ID_REGISTER(ds);
580 SysBusDevice *dev = SYS_BUS_DEVICE(ds);
581 Error *local_err = NULL;
582
583 memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.idreg",
584 sizeof(idreg_data), &local_err);
585 if (local_err) {
586 error_propagate(errp, local_err);
587 return;
588 }
589
590 vmstate_register_ram_global(&s->mem);
591 memory_region_set_readonly(&s->mem, true);
592 sysbus_init_mmio(dev, &s->mem);
593 }
594
595 static void idreg_class_init(ObjectClass *oc, void *data)
596 {
597 DeviceClass *dc = DEVICE_CLASS(oc);
598
599 dc->realize = idreg_realize;
600 }
601
602 static const TypeInfo idreg_info = {
603 .name = TYPE_MACIO_ID_REGISTER,
604 .parent = TYPE_SYS_BUS_DEVICE,
605 .instance_size = sizeof(IDRegState),
606 .class_init = idreg_class_init,
607 };
608
609 #define TYPE_TCX_AFX "tcx_afx"
610 OBJECT_DECLARE_SIMPLE_TYPE(AFXState, TCX_AFX)
611
612 struct AFXState {
613 SysBusDevice parent_obj;
614
615 MemoryRegion mem;
616 };
617
618 /* SS-5 TCX AFX register */
619 static void afx_init(hwaddr addr)
620 {
621 DeviceState *dev;
622 SysBusDevice *s;
623
624 dev = qdev_new(TYPE_TCX_AFX);
625 s = SYS_BUS_DEVICE(dev);
626 sysbus_realize_and_unref(s, &error_fatal);
627
628 sysbus_mmio_map(s, 0, addr);
629 }
630
631 static void afx_realize(DeviceState *ds, Error **errp)
632 {
633 AFXState *s = TCX_AFX(ds);
634 SysBusDevice *dev = SYS_BUS_DEVICE(ds);
635 Error *local_err = NULL;
636
637 memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.afx", 4,
638 &local_err);
639 if (local_err) {
640 error_propagate(errp, local_err);
641 return;
642 }
643
644 vmstate_register_ram_global(&s->mem);
645 sysbus_init_mmio(dev, &s->mem);
646 }
647
648 static void afx_class_init(ObjectClass *oc, void *data)
649 {
650 DeviceClass *dc = DEVICE_CLASS(oc);
651
652 dc->realize = afx_realize;
653 }
654
655 static const TypeInfo afx_info = {
656 .name = TYPE_TCX_AFX,
657 .parent = TYPE_SYS_BUS_DEVICE,
658 .instance_size = sizeof(AFXState),
659 .class_init = afx_class_init,
660 };
661
662 #define TYPE_OPENPROM "openprom"
663 typedef struct PROMState PROMState;
664 DECLARE_INSTANCE_CHECKER(PROMState, OPENPROM,
665 TYPE_OPENPROM)
666
667 struct PROMState {
668 SysBusDevice parent_obj;
669
670 MemoryRegion prom;
671 };
672
673 /* Boot PROM (OpenBIOS) */
674 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
675 {
676 hwaddr *base_addr = (hwaddr *)opaque;
677 return addr + *base_addr - PROM_VADDR;
678 }
679
680 static void prom_init(hwaddr addr, const char *bios_name)
681 {
682 DeviceState *dev;
683 SysBusDevice *s;
684 char *filename;
685 int ret;
686
687 dev = qdev_new(TYPE_OPENPROM);
688 s = SYS_BUS_DEVICE(dev);
689 sysbus_realize_and_unref(s, &error_fatal);
690
691 sysbus_mmio_map(s, 0, addr);
692
693 /* load boot prom */
694 if (bios_name == NULL) {
695 bios_name = PROM_FILENAME;
696 }
697 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
698 if (filename) {
699 ret = load_elf(filename, NULL,
700 translate_prom_address, &addr, NULL,
701 NULL, NULL, NULL, 1, EM_SPARC, 0, 0);
702 if (ret < 0 || ret > PROM_SIZE_MAX) {
703 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
704 }
705 g_free(filename);
706 } else {
707 ret = -1;
708 }
709 if (ret < 0 || ret > PROM_SIZE_MAX) {
710 error_report("could not load prom '%s'", bios_name);
711 exit(1);
712 }
713 }
714
715 static void prom_realize(DeviceState *ds, Error **errp)
716 {
717 PROMState *s = OPENPROM(ds);
718 SysBusDevice *dev = SYS_BUS_DEVICE(ds);
719 Error *local_err = NULL;
720
721 memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4m.prom",
722 PROM_SIZE_MAX, &local_err);
723 if (local_err) {
724 error_propagate(errp, local_err);
725 return;
726 }
727
728 vmstate_register_ram_global(&s->prom);
729 memory_region_set_readonly(&s->prom, true);
730 sysbus_init_mmio(dev, &s->prom);
731 }
732
733 static Property prom_properties[] = {
734 {/* end of property list */},
735 };
736
737 static void prom_class_init(ObjectClass *klass, void *data)
738 {
739 DeviceClass *dc = DEVICE_CLASS(klass);
740
741 device_class_set_props(dc, prom_properties);
742 dc->realize = prom_realize;
743 }
744
745 static const TypeInfo prom_info = {
746 .name = TYPE_OPENPROM,
747 .parent = TYPE_SYS_BUS_DEVICE,
748 .instance_size = sizeof(PROMState),
749 .class_init = prom_class_init,
750 };
751
752 #define TYPE_SUN4M_MEMORY "memory"
753 typedef struct RamDevice RamDevice;
754 DECLARE_INSTANCE_CHECKER(RamDevice, SUN4M_RAM,
755 TYPE_SUN4M_MEMORY)
756
757 struct RamDevice {
758 SysBusDevice parent_obj;
759 HostMemoryBackend *memdev;
760 };
761
762 /* System RAM */
763 static void ram_realize(DeviceState *dev, Error **errp)
764 {
765 RamDevice *d = SUN4M_RAM(dev);
766 MemoryRegion *ram = host_memory_backend_get_memory(d->memdev);
767
768 sysbus_init_mmio(SYS_BUS_DEVICE(dev), ram);
769 }
770
771 static void ram_initfn(Object *obj)
772 {
773 RamDevice *d = SUN4M_RAM(obj);
774 object_property_add_link(obj, "memdev", TYPE_MEMORY_BACKEND,
775 (Object **)&d->memdev,
776 object_property_allow_set_link,
777 OBJ_PROP_LINK_STRONG);
778 object_property_set_description(obj, "memdev", "Set RAM backend"
779 "Valid value is ID of a hostmem backend");
780 }
781
782 static void ram_class_init(ObjectClass *klass, void *data)
783 {
784 DeviceClass *dc = DEVICE_CLASS(klass);
785
786 dc->realize = ram_realize;
787 }
788
789 static const TypeInfo ram_info = {
790 .name = TYPE_SUN4M_MEMORY,
791 .parent = TYPE_SYS_BUS_DEVICE,
792 .instance_size = sizeof(RamDevice),
793 .instance_init = ram_initfn,
794 .class_init = ram_class_init,
795 };
796
797 static void cpu_devinit(const char *cpu_type, unsigned int id,
798 uint64_t prom_addr, qemu_irq **cpu_irqs)
799 {
800 SPARCCPU *cpu;
801 CPUSPARCState *env;
802
803 cpu = SPARC_CPU(object_new(cpu_type));
804 env = &cpu->env;
805
806 cpu_sparc_set_id(env, id);
807 qemu_register_reset(sun4m_cpu_reset, cpu);
808 object_property_set_bool(OBJECT(cpu), "start-powered-off", id != 0,
809 &error_fatal);
810 qdev_realize_and_unref(DEVICE(cpu), NULL, &error_fatal);
811 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS);
812 env->prom_addr = prom_addr;
813 }
814
815 static void dummy_fdc_tc(void *opaque, int irq, int level)
816 {
817 }
818
819 static void sun4m_hw_init(MachineState *machine)
820 {
821 const struct sun4m_hwdef *hwdef = SUN4M_MACHINE_GET_CLASS(machine)->hwdef;
822 DeviceState *slavio_intctl;
823 unsigned int i;
824 Nvram *nvram;
825 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS];
826 qemu_irq fdc_tc;
827 unsigned long kernel_size;
828 uint32_t initrd_size;
829 DriveInfo *fd[MAX_FD];
830 FWCfgState *fw_cfg;
831 DeviceState *dev, *ms_kb_orgate, *serial_orgate;
832 SysBusDevice *s;
833 unsigned int smp_cpus = machine->smp.cpus;
834 unsigned int max_cpus = machine->smp.max_cpus;
835 Object *ram_memdev = object_resolve_path_type(machine->ram_memdev_id,
836 TYPE_MEMORY_BACKEND, NULL);
837 NICInfo *nd = &nd_table[0];
838
839 if (machine->ram_size > hwdef->max_mem) {
840 error_report("Too much memory for this machine: %" PRId64 ","
841 " maximum %" PRId64,
842 machine->ram_size / MiB, hwdef->max_mem / MiB);
843 exit(1);
844 }
845
846 /* init CPUs */
847 for(i = 0; i < smp_cpus; i++) {
848 cpu_devinit(machine->cpu_type, i, hwdef->slavio_base, &cpu_irqs[i]);
849 }
850
851 for (i = smp_cpus; i < MAX_CPUS; i++)
852 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
853
854 /* Create and map RAM frontend */
855 dev = qdev_new("memory");
856 object_property_set_link(OBJECT(dev), "memdev", ram_memdev, &error_fatal);
857 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
858 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0);
859
860 /* models without ECC don't trap when missing ram is accessed */
861 if (!hwdef->ecc_base) {
862 empty_slot_init("ecc", machine->ram_size,
863 hwdef->max_mem - machine->ram_size);
864 }
865
866 prom_init(hwdef->slavio_base, machine->firmware);
867
868 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
869 hwdef->intctl_base + 0x10000ULL,
870 cpu_irqs);
871
872 for (i = 0; i < 32; i++) {
873 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
874 }
875 for (i = 0; i < MAX_CPUS; i++) {
876 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
877 }
878
879 if (hwdef->idreg_base) {
880 idreg_init(hwdef->idreg_base);
881 }
882
883 if (hwdef->afx_base) {
884 afx_init(hwdef->afx_base);
885 }
886
887 iommu_init(hwdef->iommu_base, hwdef->iommu_version, slavio_irq[30]);
888
889 if (hwdef->iommu_pad_base) {
890 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
891 Software shouldn't use aliased addresses, neither should it crash
892 when does. Using empty_slot instead of aliasing can help with
893 debugging such accesses */
894 empty_slot_init("iommu.alias",
895 hwdef->iommu_pad_base, hwdef->iommu_pad_len);
896 }
897
898 qemu_check_nic_model(nd, TYPE_LANCE);
899 sparc32_dma_init(hwdef->dma_base,
900 hwdef->esp_base, slavio_irq[18],
901 hwdef->le_base, slavio_irq[16], nd);
902
903 if (graphic_depth != 8 && graphic_depth != 24) {
904 error_report("Unsupported depth: %d", graphic_depth);
905 exit (1);
906 }
907 if (vga_interface_type != VGA_NONE) {
908 if (vga_interface_type == VGA_CG3) {
909 if (graphic_depth != 8) {
910 error_report("Unsupported depth: %d", graphic_depth);
911 exit(1);
912 }
913
914 if (!(graphic_width == 1024 && graphic_height == 768) &&
915 !(graphic_width == 1152 && graphic_height == 900)) {
916 error_report("Unsupported resolution: %d x %d", graphic_width,
917 graphic_height);
918 exit(1);
919 }
920
921 /* sbus irq 5 */
922 cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
923 graphic_width, graphic_height, graphic_depth);
924 } else {
925 /* If no display specified, default to TCX */
926 if (graphic_depth != 8 && graphic_depth != 24) {
927 error_report("Unsupported depth: %d", graphic_depth);
928 exit(1);
929 }
930
931 if (!(graphic_width == 1024 && graphic_height == 768)) {
932 error_report("Unsupported resolution: %d x %d",
933 graphic_width, graphic_height);
934 exit(1);
935 }
936
937 tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
938 graphic_width, graphic_height, graphic_depth);
939 }
940 }
941
942 for (i = 0; i < MAX_VSIMMS; i++) {
943 /* vsimm registers probed by OBP */
944 if (hwdef->vsimm[i].reg_base) {
945 char *name = g_strdup_printf("vsimm[%d]", i);
946 empty_slot_init(name, hwdef->vsimm[i].reg_base, 0x2000);
947 g_free(name);
948 }
949 }
950
951 if (hwdef->sx_base) {
952 create_unimplemented_device("sun-sx", hwdef->sx_base, 0x2000);
953 }
954
955 dev = qdev_new("sysbus-m48t08");
956 qdev_prop_set_int32(dev, "base-year", 1968);
957 s = SYS_BUS_DEVICE(dev);
958 sysbus_realize_and_unref(s, &error_fatal);
959 sysbus_connect_irq(s, 0, slavio_irq[0]);
960 sysbus_mmio_map(s, 0, hwdef->nvram_base);
961 nvram = NVRAM(dev);
962
963 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
964
965 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
966 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
967 dev = qdev_new(TYPE_ESCC);
968 qdev_prop_set_uint32(dev, "disabled", !machine->enable_graphics);
969 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK);
970 qdev_prop_set_uint32(dev, "it_shift", 1);
971 qdev_prop_set_chr(dev, "chrB", NULL);
972 qdev_prop_set_chr(dev, "chrA", NULL);
973 qdev_prop_set_uint32(dev, "chnBtype", escc_mouse);
974 qdev_prop_set_uint32(dev, "chnAtype", escc_kbd);
975 s = SYS_BUS_DEVICE(dev);
976 sysbus_realize_and_unref(s, &error_fatal);
977 sysbus_mmio_map(s, 0, hwdef->ms_kb_base);
978
979 /* Logically OR both its IRQs together */
980 ms_kb_orgate = DEVICE(object_new(TYPE_OR_IRQ));
981 object_property_set_int(OBJECT(ms_kb_orgate), "num-lines", 2, &error_fatal);
982 qdev_realize_and_unref(ms_kb_orgate, NULL, &error_fatal);
983 sysbus_connect_irq(s, 0, qdev_get_gpio_in(ms_kb_orgate, 0));
984 sysbus_connect_irq(s, 1, qdev_get_gpio_in(ms_kb_orgate, 1));
985 qdev_connect_gpio_out(DEVICE(ms_kb_orgate), 0, slavio_irq[14]);
986
987 dev = qdev_new(TYPE_ESCC);
988 qdev_prop_set_uint32(dev, "disabled", 0);
989 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK);
990 qdev_prop_set_uint32(dev, "it_shift", 1);
991 qdev_prop_set_chr(dev, "chrB", serial_hd(1));
992 qdev_prop_set_chr(dev, "chrA", serial_hd(0));
993 qdev_prop_set_uint32(dev, "chnBtype", escc_serial);
994 qdev_prop_set_uint32(dev, "chnAtype", escc_serial);
995
996 s = SYS_BUS_DEVICE(dev);
997 sysbus_realize_and_unref(s, &error_fatal);
998 sysbus_mmio_map(s, 0, hwdef->serial_base);
999
1000 /* Logically OR both its IRQs together */
1001 serial_orgate = DEVICE(object_new(TYPE_OR_IRQ));
1002 object_property_set_int(OBJECT(serial_orgate), "num-lines", 2,
1003 &error_fatal);
1004 qdev_realize_and_unref(serial_orgate, NULL, &error_fatal);
1005 sysbus_connect_irq(s, 0, qdev_get_gpio_in(serial_orgate, 0));
1006 sysbus_connect_irq(s, 1, qdev_get_gpio_in(serial_orgate, 1));
1007 qdev_connect_gpio_out(DEVICE(serial_orgate), 0, slavio_irq[15]);
1008
1009 if (hwdef->apc_base) {
1010 apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0));
1011 }
1012
1013 if (hwdef->fd_base) {
1014 /* there is zero or one floppy drive */
1015 memset(fd, 0, sizeof(fd));
1016 fd[0] = drive_get(IF_FLOPPY, 0, 0);
1017 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
1018 &fdc_tc);
1019 } else {
1020 fdc_tc = qemu_allocate_irq(dummy_fdc_tc, NULL, 0);
1021 }
1022
1023 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
1024 slavio_irq[30], fdc_tc);
1025
1026 if (hwdef->cs_base) {
1027 sysbus_create_simple("sun-CS4231", hwdef->cs_base,
1028 slavio_irq[5]);
1029 }
1030
1031 if (hwdef->dbri_base) {
1032 /* ISDN chip with attached CS4215 audio codec */
1033 /* prom space */
1034 create_unimplemented_device("sun-DBRI.prom",
1035 hwdef->dbri_base + 0x1000, 0x30);
1036 /* reg space */
1037 create_unimplemented_device("sun-DBRI",
1038 hwdef->dbri_base + 0x10000, 0x100);
1039 }
1040
1041 if (hwdef->bpp_base) {
1042 /* parallel port */
1043 create_unimplemented_device("sun-bpp", hwdef->bpp_base, 0x20);
1044 }
1045
1046 initrd_size = 0;
1047 kernel_size = sun4m_load_kernel(machine->kernel_filename,
1048 machine->initrd_filename,
1049 machine->ram_size, &initrd_size);
1050
1051 nvram_init(nvram, (uint8_t *)&nd->macaddr, machine->kernel_cmdline,
1052 machine->boot_order, machine->ram_size, kernel_size,
1053 graphic_width, graphic_height, graphic_depth,
1054 hwdef->nvram_machine_id, "Sun4m");
1055
1056 if (hwdef->ecc_base)
1057 ecc_init(hwdef->ecc_base, slavio_irq[28],
1058 hwdef->ecc_version);
1059
1060 dev = qdev_new(TYPE_FW_CFG_MEM);
1061 fw_cfg = FW_CFG(dev);
1062 qdev_prop_set_uint32(dev, "data_width", 1);
1063 qdev_prop_set_bit(dev, "dma_enabled", false);
1064 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
1065 OBJECT(fw_cfg));
1066 s = SYS_BUS_DEVICE(dev);
1067 sysbus_realize_and_unref(s, &error_fatal);
1068 sysbus_mmio_map(s, 0, CFG_ADDR);
1069 sysbus_mmio_map(s, 1, CFG_ADDR + 2);
1070
1071 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
1072 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
1073 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size);
1074 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1075 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1076 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width);
1077 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height);
1078 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1079 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1080 if (machine->kernel_cmdline) {
1081 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1082 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE,
1083 machine->kernel_cmdline);
1084 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
1085 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1086 strlen(machine->kernel_cmdline) + 1);
1087 } else {
1088 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1089 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
1090 }
1091 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1092 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
1093 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
1094 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1095 }
1096
1097 enum {
1098 ss5_id = 32,
1099 vger_id,
1100 lx_id,
1101 ss4_id,
1102 scls_id,
1103 sbook_id,
1104 ss10_id = 64,
1105 ss20_id,
1106 ss600mp_id,
1107 };
1108
1109 static void sun4m_machine_class_init(ObjectClass *oc, void *data)
1110 {
1111 MachineClass *mc = MACHINE_CLASS(oc);
1112
1113 mc->init = sun4m_hw_init;
1114 mc->block_default_type = IF_SCSI;
1115 mc->default_boot_order = "c";
1116 mc->default_display = "tcx";
1117 mc->default_ram_id = "sun4m.ram";
1118 }
1119
1120 static void ss5_class_init(ObjectClass *oc, void *data)
1121 {
1122 MachineClass *mc = MACHINE_CLASS(oc);
1123 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
1124 static const struct sun4m_hwdef ss5_hwdef = {
1125 .iommu_base = 0x10000000,
1126 .iommu_pad_base = 0x10004000,
1127 .iommu_pad_len = 0x0fffb000,
1128 .tcx_base = 0x50000000,
1129 .cs_base = 0x6c000000,
1130 .slavio_base = 0x70000000,
1131 .ms_kb_base = 0x71000000,
1132 .serial_base = 0x71100000,
1133 .nvram_base = 0x71200000,
1134 .fd_base = 0x71400000,
1135 .counter_base = 0x71d00000,
1136 .intctl_base = 0x71e00000,
1137 .idreg_base = 0x78000000,
1138 .dma_base = 0x78400000,
1139 .esp_base = 0x78800000,
1140 .le_base = 0x78c00000,
1141 .apc_base = 0x6a000000,
1142 .afx_base = 0x6e000000,
1143 .aux1_base = 0x71900000,
1144 .aux2_base = 0x71910000,
1145 .nvram_machine_id = 0x80,
1146 .machine_id = ss5_id,
1147 .iommu_version = 0x05000000,
1148 .max_mem = 0x10000000,
1149 };
1150
1151 mc->desc = "Sun4m platform, SPARCstation 5";
1152 mc->is_default = true;
1153 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1154 smc->hwdef = &ss5_hwdef;
1155 }
1156
1157 static void ss10_class_init(ObjectClass *oc, void *data)
1158 {
1159 MachineClass *mc = MACHINE_CLASS(oc);
1160 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
1161 static const struct sun4m_hwdef ss10_hwdef = {
1162 .iommu_base = 0xfe0000000ULL,
1163 .tcx_base = 0xe20000000ULL,
1164 .slavio_base = 0xff0000000ULL,
1165 .ms_kb_base = 0xff1000000ULL,
1166 .serial_base = 0xff1100000ULL,
1167 .nvram_base = 0xff1200000ULL,
1168 .fd_base = 0xff1700000ULL,
1169 .counter_base = 0xff1300000ULL,
1170 .intctl_base = 0xff1400000ULL,
1171 .idreg_base = 0xef0000000ULL,
1172 .dma_base = 0xef0400000ULL,
1173 .esp_base = 0xef0800000ULL,
1174 .le_base = 0xef0c00000ULL,
1175 .apc_base = 0xefa000000ULL, /* XXX should not exist */
1176 .aux1_base = 0xff1800000ULL,
1177 .aux2_base = 0xff1a01000ULL,
1178 .ecc_base = 0xf00000000ULL,
1179 .ecc_version = 0x10000000, /* version 0, implementation 1 */
1180 .nvram_machine_id = 0x72,
1181 .machine_id = ss10_id,
1182 .iommu_version = 0x03000000,
1183 .max_mem = 0xf00000000ULL,
1184 };
1185
1186 mc->desc = "Sun4m platform, SPARCstation 10";
1187 mc->max_cpus = 4;
1188 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1189 smc->hwdef = &ss10_hwdef;
1190 }
1191
1192 static void ss600mp_class_init(ObjectClass *oc, void *data)
1193 {
1194 MachineClass *mc = MACHINE_CLASS(oc);
1195 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
1196 static const struct sun4m_hwdef ss600mp_hwdef = {
1197 .iommu_base = 0xfe0000000ULL,
1198 .tcx_base = 0xe20000000ULL,
1199 .slavio_base = 0xff0000000ULL,
1200 .ms_kb_base = 0xff1000000ULL,
1201 .serial_base = 0xff1100000ULL,
1202 .nvram_base = 0xff1200000ULL,
1203 .counter_base = 0xff1300000ULL,
1204 .intctl_base = 0xff1400000ULL,
1205 .dma_base = 0xef0081000ULL,
1206 .esp_base = 0xef0080000ULL,
1207 .le_base = 0xef0060000ULL,
1208 .apc_base = 0xefa000000ULL, /* XXX should not exist */
1209 .aux1_base = 0xff1800000ULL,
1210 .aux2_base = 0xff1a01000ULL, /* XXX should not exist */
1211 .ecc_base = 0xf00000000ULL,
1212 .ecc_version = 0x00000000, /* version 0, implementation 0 */
1213 .nvram_machine_id = 0x71,
1214 .machine_id = ss600mp_id,
1215 .iommu_version = 0x01000000,
1216 .max_mem = 0xf00000000ULL,
1217 };
1218
1219 mc->desc = "Sun4m platform, SPARCserver 600MP";
1220 mc->max_cpus = 4;
1221 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1222 smc->hwdef = &ss600mp_hwdef;
1223 }
1224
1225 static void ss20_class_init(ObjectClass *oc, void *data)
1226 {
1227 MachineClass *mc = MACHINE_CLASS(oc);
1228 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
1229 static const struct sun4m_hwdef ss20_hwdef = {
1230 .iommu_base = 0xfe0000000ULL,
1231 .tcx_base = 0xe20000000ULL,
1232 .slavio_base = 0xff0000000ULL,
1233 .ms_kb_base = 0xff1000000ULL,
1234 .serial_base = 0xff1100000ULL,
1235 .nvram_base = 0xff1200000ULL,
1236 .fd_base = 0xff1700000ULL,
1237 .counter_base = 0xff1300000ULL,
1238 .intctl_base = 0xff1400000ULL,
1239 .idreg_base = 0xef0000000ULL,
1240 .dma_base = 0xef0400000ULL,
1241 .esp_base = 0xef0800000ULL,
1242 .le_base = 0xef0c00000ULL,
1243 .bpp_base = 0xef4800000ULL,
1244 .apc_base = 0xefa000000ULL, /* XXX should not exist */
1245 .aux1_base = 0xff1800000ULL,
1246 .aux2_base = 0xff1a01000ULL,
1247 .dbri_base = 0xee0000000ULL,
1248 .sx_base = 0xf80000000ULL,
1249 .vsimm = {
1250 {
1251 .reg_base = 0x9c000000ULL,
1252 .vram_base = 0xfc000000ULL
1253 }, {
1254 .reg_base = 0x90000000ULL,
1255 .vram_base = 0xf0000000ULL
1256 }, {
1257 .reg_base = 0x94000000ULL
1258 }, {
1259 .reg_base = 0x98000000ULL
1260 }
1261 },
1262 .ecc_base = 0xf00000000ULL,
1263 .ecc_version = 0x20000000, /* version 0, implementation 2 */
1264 .nvram_machine_id = 0x72,
1265 .machine_id = ss20_id,
1266 .iommu_version = 0x13000000,
1267 .max_mem = 0xf00000000ULL,
1268 };
1269
1270 mc->desc = "Sun4m platform, SPARCstation 20";
1271 mc->max_cpus = 4;
1272 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1273 smc->hwdef = &ss20_hwdef;
1274 }
1275
1276 static void voyager_class_init(ObjectClass *oc, void *data)
1277 {
1278 MachineClass *mc = MACHINE_CLASS(oc);
1279 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
1280 static const struct sun4m_hwdef voyager_hwdef = {
1281 .iommu_base = 0x10000000,
1282 .tcx_base = 0x50000000,
1283 .slavio_base = 0x70000000,
1284 .ms_kb_base = 0x71000000,
1285 .serial_base = 0x71100000,
1286 .nvram_base = 0x71200000,
1287 .fd_base = 0x71400000,
1288 .counter_base = 0x71d00000,
1289 .intctl_base = 0x71e00000,
1290 .idreg_base = 0x78000000,
1291 .dma_base = 0x78400000,
1292 .esp_base = 0x78800000,
1293 .le_base = 0x78c00000,
1294 .apc_base = 0x71300000, /* pmc */
1295 .aux1_base = 0x71900000,
1296 .aux2_base = 0x71910000,
1297 .nvram_machine_id = 0x80,
1298 .machine_id = vger_id,
1299 .iommu_version = 0x05000000,
1300 .max_mem = 0x10000000,
1301 };
1302
1303 mc->desc = "Sun4m platform, SPARCstation Voyager";
1304 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1305 smc->hwdef = &voyager_hwdef;
1306 }
1307
1308 static void ss_lx_class_init(ObjectClass *oc, void *data)
1309 {
1310 MachineClass *mc = MACHINE_CLASS(oc);
1311 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
1312 static const struct sun4m_hwdef ss_lx_hwdef = {
1313 .iommu_base = 0x10000000,
1314 .iommu_pad_base = 0x10004000,
1315 .iommu_pad_len = 0x0fffb000,
1316 .tcx_base = 0x50000000,
1317 .slavio_base = 0x70000000,
1318 .ms_kb_base = 0x71000000,
1319 .serial_base = 0x71100000,
1320 .nvram_base = 0x71200000,
1321 .fd_base = 0x71400000,
1322 .counter_base = 0x71d00000,
1323 .intctl_base = 0x71e00000,
1324 .idreg_base = 0x78000000,
1325 .dma_base = 0x78400000,
1326 .esp_base = 0x78800000,
1327 .le_base = 0x78c00000,
1328 .aux1_base = 0x71900000,
1329 .aux2_base = 0x71910000,
1330 .nvram_machine_id = 0x80,
1331 .machine_id = lx_id,
1332 .iommu_version = 0x04000000,
1333 .max_mem = 0x10000000,
1334 };
1335
1336 mc->desc = "Sun4m platform, SPARCstation LX";
1337 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1338 smc->hwdef = &ss_lx_hwdef;
1339 }
1340
1341 static void ss4_class_init(ObjectClass *oc, void *data)
1342 {
1343 MachineClass *mc = MACHINE_CLASS(oc);
1344 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
1345 static const struct sun4m_hwdef ss4_hwdef = {
1346 .iommu_base = 0x10000000,
1347 .tcx_base = 0x50000000,
1348 .cs_base = 0x6c000000,
1349 .slavio_base = 0x70000000,
1350 .ms_kb_base = 0x71000000,
1351 .serial_base = 0x71100000,
1352 .nvram_base = 0x71200000,
1353 .fd_base = 0x71400000,
1354 .counter_base = 0x71d00000,
1355 .intctl_base = 0x71e00000,
1356 .idreg_base = 0x78000000,
1357 .dma_base = 0x78400000,
1358 .esp_base = 0x78800000,
1359 .le_base = 0x78c00000,
1360 .apc_base = 0x6a000000,
1361 .aux1_base = 0x71900000,
1362 .aux2_base = 0x71910000,
1363 .nvram_machine_id = 0x80,
1364 .machine_id = ss4_id,
1365 .iommu_version = 0x05000000,
1366 .max_mem = 0x10000000,
1367 };
1368
1369 mc->desc = "Sun4m platform, SPARCstation 4";
1370 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1371 smc->hwdef = &ss4_hwdef;
1372 }
1373
1374 static void scls_class_init(ObjectClass *oc, void *data)
1375 {
1376 MachineClass *mc = MACHINE_CLASS(oc);
1377 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
1378 static const struct sun4m_hwdef scls_hwdef = {
1379 .iommu_base = 0x10000000,
1380 .tcx_base = 0x50000000,
1381 .slavio_base = 0x70000000,
1382 .ms_kb_base = 0x71000000,
1383 .serial_base = 0x71100000,
1384 .nvram_base = 0x71200000,
1385 .fd_base = 0x71400000,
1386 .counter_base = 0x71d00000,
1387 .intctl_base = 0x71e00000,
1388 .idreg_base = 0x78000000,
1389 .dma_base = 0x78400000,
1390 .esp_base = 0x78800000,
1391 .le_base = 0x78c00000,
1392 .apc_base = 0x6a000000,
1393 .aux1_base = 0x71900000,
1394 .aux2_base = 0x71910000,
1395 .nvram_machine_id = 0x80,
1396 .machine_id = scls_id,
1397 .iommu_version = 0x05000000,
1398 .max_mem = 0x10000000,
1399 };
1400
1401 mc->desc = "Sun4m platform, SPARCClassic";
1402 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1403 smc->hwdef = &scls_hwdef;
1404 }
1405
1406 static void sbook_class_init(ObjectClass *oc, void *data)
1407 {
1408 MachineClass *mc = MACHINE_CLASS(oc);
1409 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
1410 static const struct sun4m_hwdef sbook_hwdef = {
1411 .iommu_base = 0x10000000,
1412 .tcx_base = 0x50000000, /* XXX */
1413 .slavio_base = 0x70000000,
1414 .ms_kb_base = 0x71000000,
1415 .serial_base = 0x71100000,
1416 .nvram_base = 0x71200000,
1417 .fd_base = 0x71400000,
1418 .counter_base = 0x71d00000,
1419 .intctl_base = 0x71e00000,
1420 .idreg_base = 0x78000000,
1421 .dma_base = 0x78400000,
1422 .esp_base = 0x78800000,
1423 .le_base = 0x78c00000,
1424 .apc_base = 0x6a000000,
1425 .aux1_base = 0x71900000,
1426 .aux2_base = 0x71910000,
1427 .nvram_machine_id = 0x80,
1428 .machine_id = sbook_id,
1429 .iommu_version = 0x05000000,
1430 .max_mem = 0x10000000,
1431 };
1432
1433 mc->desc = "Sun4m platform, SPARCbook";
1434 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1435 smc->hwdef = &sbook_hwdef;
1436 }
1437
1438 static const TypeInfo sun4m_machine_types[] = {
1439 {
1440 .name = MACHINE_TYPE_NAME("SS-5"),
1441 .parent = TYPE_SUN4M_MACHINE,
1442 .class_init = ss5_class_init,
1443 }, {
1444 .name = MACHINE_TYPE_NAME("SS-10"),
1445 .parent = TYPE_SUN4M_MACHINE,
1446 .class_init = ss10_class_init,
1447 }, {
1448 .name = MACHINE_TYPE_NAME("SS-600MP"),
1449 .parent = TYPE_SUN4M_MACHINE,
1450 .class_init = ss600mp_class_init,
1451 }, {
1452 .name = MACHINE_TYPE_NAME("SS-20"),
1453 .parent = TYPE_SUN4M_MACHINE,
1454 .class_init = ss20_class_init,
1455 }, {
1456 .name = MACHINE_TYPE_NAME("Voyager"),
1457 .parent = TYPE_SUN4M_MACHINE,
1458 .class_init = voyager_class_init,
1459 }, {
1460 .name = MACHINE_TYPE_NAME("LX"),
1461 .parent = TYPE_SUN4M_MACHINE,
1462 .class_init = ss_lx_class_init,
1463 }, {
1464 .name = MACHINE_TYPE_NAME("SS-4"),
1465 .parent = TYPE_SUN4M_MACHINE,
1466 .class_init = ss4_class_init,
1467 }, {
1468 .name = MACHINE_TYPE_NAME("SPARCClassic"),
1469 .parent = TYPE_SUN4M_MACHINE,
1470 .class_init = scls_class_init,
1471 }, {
1472 .name = MACHINE_TYPE_NAME("SPARCbook"),
1473 .parent = TYPE_SUN4M_MACHINE,
1474 .class_init = sbook_class_init,
1475 }, {
1476 .name = TYPE_SUN4M_MACHINE,
1477 .parent = TYPE_MACHINE,
1478 .class_size = sizeof(Sun4mMachineClass),
1479 .class_init = sun4m_machine_class_init,
1480 .abstract = true,
1481 }
1482 };
1483
1484 DEFINE_TYPES(sun4m_machine_types)
1485
1486 static void sun4m_register_types(void)
1487 {
1488 type_register_static(&idreg_info);
1489 type_register_static(&afx_info);
1490 type_register_static(&prom_info);
1491 type_register_static(&ram_info);
1492 }
1493
1494 type_init(sun4m_register_types)