sun4u: add power_mem_read routine
[qemu.git] / hw / sparc64 / sun4u.c
1 /*
2 * QEMU Sun4u/Sun4v System Emulator
3 *
4 * Copyright (c) 2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "qemu/osdep.h"
25 #include "qemu/units.h"
26 #include "qemu/error-report.h"
27 #include "qapi/error.h"
28 #include "qemu-common.h"
29 #include "cpu.h"
30 #include "hw/hw.h"
31 #include "hw/pci/pci.h"
32 #include "hw/pci/pci_bridge.h"
33 #include "hw/pci/pci_bus.h"
34 #include "hw/pci/pci_host.h"
35 #include "hw/pci-host/sabre.h"
36 #include "hw/i386/pc.h"
37 #include "hw/char/serial.h"
38 #include "hw/char/parallel.h"
39 #include "hw/timer/m48t59.h"
40 #include "hw/input/i8042.h"
41 #include "hw/block/fdc.h"
42 #include "net/net.h"
43 #include "qemu/timer.h"
44 #include "sysemu/sysemu.h"
45 #include "hw/boards.h"
46 #include "hw/nvram/sun_nvram.h"
47 #include "hw/nvram/chrp_nvram.h"
48 #include "hw/sparc/sparc64.h"
49 #include "hw/nvram/fw_cfg.h"
50 #include "hw/sysbus.h"
51 #include "hw/ide.h"
52 #include "hw/ide/pci.h"
53 #include "hw/loader.h"
54 #include "hw/fw-path-provider.h"
55 #include "elf.h"
56 #include "trace.h"
57
58 #define KERNEL_LOAD_ADDR 0x00404000
59 #define CMDLINE_ADDR 0x003ff000
60 #define PROM_SIZE_MAX (4 * MiB)
61 #define PROM_VADDR 0x000ffd00000ULL
62 #define PBM_SPECIAL_BASE 0x1fe00000000ULL
63 #define PBM_MEM_BASE 0x1ff00000000ULL
64 #define PBM_PCI_IO_BASE (PBM_SPECIAL_BASE + 0x02000000ULL)
65 #define PROM_FILENAME "openbios-sparc64"
66 #define NVRAM_SIZE 0x2000
67 #define MAX_IDE_BUS 2
68 #define BIOS_CFG_IOPORT 0x510
69 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
70 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
71 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
72
73 #define IVEC_MAX 0x40
74
75 struct hwdef {
76 uint16_t machine_id;
77 uint64_t prom_addr;
78 uint64_t console_serial_base;
79 };
80
81 typedef struct EbusState {
82 /*< private >*/
83 PCIDevice parent_obj;
84
85 ISABus *isa_bus;
86 qemu_irq isa_bus_irqs[ISA_NUM_IRQS];
87 uint64_t console_serial_base;
88 MemoryRegion bar0;
89 MemoryRegion bar1;
90 } EbusState;
91
92 #define TYPE_EBUS "ebus"
93 #define EBUS(obj) OBJECT_CHECK(EbusState, (obj), TYPE_EBUS)
94
95 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
96 Error **errp)
97 {
98 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
99 }
100
101 static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size,
102 const char *arch, ram_addr_t RAM_size,
103 const char *boot_devices,
104 uint32_t kernel_image, uint32_t kernel_size,
105 const char *cmdline,
106 uint32_t initrd_image, uint32_t initrd_size,
107 uint32_t NVRAM_image,
108 int width, int height, int depth,
109 const uint8_t *macaddr)
110 {
111 unsigned int i;
112 int sysp_end;
113 uint8_t image[0x1ff0];
114 NvramClass *k = NVRAM_GET_CLASS(nvram);
115
116 memset(image, '\0', sizeof(image));
117
118 /* OpenBIOS nvram variables partition */
119 sysp_end = chrp_nvram_create_system_partition(image, 0);
120
121 /* Free space partition */
122 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end);
123
124 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
125
126 for (i = 0; i < sizeof(image); i++) {
127 (k->write)(nvram, i, image[i]);
128 }
129
130 return 0;
131 }
132
133 static uint64_t sun4u_load_kernel(const char *kernel_filename,
134 const char *initrd_filename,
135 ram_addr_t RAM_size, uint64_t *initrd_size,
136 uint64_t *initrd_addr, uint64_t *kernel_addr,
137 uint64_t *kernel_entry)
138 {
139 int linux_boot;
140 unsigned int i;
141 long kernel_size;
142 uint8_t *ptr;
143 uint64_t kernel_top = 0;
144
145 linux_boot = (kernel_filename != NULL);
146
147 kernel_size = 0;
148 if (linux_boot) {
149 int bswap_needed;
150
151 #ifdef BSWAP_NEEDED
152 bswap_needed = 1;
153 #else
154 bswap_needed = 0;
155 #endif
156 kernel_size = load_elf(kernel_filename, NULL, NULL, kernel_entry,
157 kernel_addr, &kernel_top, 1, EM_SPARCV9, 0, 0);
158 if (kernel_size < 0) {
159 *kernel_addr = KERNEL_LOAD_ADDR;
160 *kernel_entry = KERNEL_LOAD_ADDR;
161 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
162 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
163 TARGET_PAGE_SIZE);
164 }
165 if (kernel_size < 0) {
166 kernel_size = load_image_targphys(kernel_filename,
167 KERNEL_LOAD_ADDR,
168 RAM_size - KERNEL_LOAD_ADDR);
169 }
170 if (kernel_size < 0) {
171 error_report("could not load kernel '%s'", kernel_filename);
172 exit(1);
173 }
174 /* load initrd above kernel */
175 *initrd_size = 0;
176 if (initrd_filename && kernel_top) {
177 *initrd_addr = TARGET_PAGE_ALIGN(kernel_top);
178
179 *initrd_size = load_image_targphys(initrd_filename,
180 *initrd_addr,
181 RAM_size - *initrd_addr);
182 if ((int)*initrd_size < 0) {
183 error_report("could not load initial ram disk '%s'",
184 initrd_filename);
185 exit(1);
186 }
187 }
188 if (*initrd_size > 0) {
189 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
190 ptr = rom_ptr(*kernel_addr + i, 32);
191 if (ptr && ldl_p(ptr + 8) == 0x48647253) { /* HdrS */
192 stl_p(ptr + 24, *initrd_addr + *kernel_addr);
193 stl_p(ptr + 28, *initrd_size);
194 break;
195 }
196 }
197 }
198 }
199 return kernel_size;
200 }
201
202 typedef struct ResetData {
203 SPARCCPU *cpu;
204 uint64_t prom_addr;
205 } ResetData;
206
207 #define TYPE_SUN4U_POWER "power"
208 #define SUN4U_POWER(obj) OBJECT_CHECK(PowerDevice, (obj), TYPE_SUN4U_POWER)
209
210 typedef struct PowerDevice {
211 SysBusDevice parent_obj;
212
213 MemoryRegion power_mmio;
214 } PowerDevice;
215
216 /* Power */
217 static uint64_t power_mem_read(void *opaque, hwaddr addr, unsigned size)
218 {
219 return 0;
220 }
221
222 static void power_mem_write(void *opaque, hwaddr addr,
223 uint64_t val, unsigned size)
224 {
225 /* According to a real Ultra 5, bit 24 controls the power */
226 if (val & 0x1000000) {
227 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
228 }
229 }
230
231 static const MemoryRegionOps power_mem_ops = {
232 .read = power_mem_read,
233 .write = power_mem_write,
234 .endianness = DEVICE_NATIVE_ENDIAN,
235 .valid = {
236 .min_access_size = 4,
237 .max_access_size = 4,
238 },
239 };
240
241 static void power_realize(DeviceState *dev, Error **errp)
242 {
243 PowerDevice *d = SUN4U_POWER(dev);
244 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
245
246 memory_region_init_io(&d->power_mmio, OBJECT(dev), &power_mem_ops, d,
247 "power", sizeof(uint32_t));
248
249 sysbus_init_mmio(sbd, &d->power_mmio);
250 }
251
252 static void power_class_init(ObjectClass *klass, void *data)
253 {
254 DeviceClass *dc = DEVICE_CLASS(klass);
255
256 dc->realize = power_realize;
257 }
258
259 static const TypeInfo power_info = {
260 .name = TYPE_SUN4U_POWER,
261 .parent = TYPE_SYS_BUS_DEVICE,
262 .instance_size = sizeof(PowerDevice),
263 .class_init = power_class_init,
264 };
265
266 static void ebus_isa_irq_handler(void *opaque, int n, int level)
267 {
268 EbusState *s = EBUS(opaque);
269 qemu_irq irq = s->isa_bus_irqs[n];
270
271 /* Pass ISA bus IRQs onto their gpio equivalent */
272 trace_ebus_isa_irq_handler(n, level);
273 if (irq) {
274 qemu_set_irq(irq, level);
275 }
276 }
277
278 /* EBUS (Eight bit bus) bridge */
279 static void ebus_realize(PCIDevice *pci_dev, Error **errp)
280 {
281 EbusState *s = EBUS(pci_dev);
282 SysBusDevice *sbd;
283 DeviceState *dev;
284 qemu_irq *isa_irq;
285 DriveInfo *fd[MAX_FD];
286 int i;
287
288 s->isa_bus = isa_bus_new(DEVICE(pci_dev), get_system_memory(),
289 pci_address_space_io(pci_dev), errp);
290 if (!s->isa_bus) {
291 error_setg(errp, "unable to instantiate EBUS ISA bus");
292 return;
293 }
294
295 /* ISA bus */
296 isa_irq = qemu_allocate_irqs(ebus_isa_irq_handler, s, ISA_NUM_IRQS);
297 isa_bus_irqs(s->isa_bus, isa_irq);
298 qdev_init_gpio_out_named(DEVICE(s), s->isa_bus_irqs, "isa-irq",
299 ISA_NUM_IRQS);
300
301 /* Serial ports */
302 i = 0;
303 if (s->console_serial_base) {
304 serial_mm_init(pci_address_space(pci_dev), s->console_serial_base,
305 0, NULL, 115200, serial_hd(i), DEVICE_BIG_ENDIAN);
306 i++;
307 }
308 serial_hds_isa_init(s->isa_bus, i, MAX_ISA_SERIAL_PORTS);
309
310 /* Parallel ports */
311 parallel_hds_isa_init(s->isa_bus, MAX_PARALLEL_PORTS);
312
313 /* Keyboard */
314 isa_create_simple(s->isa_bus, "i8042");
315
316 /* Floppy */
317 for (i = 0; i < MAX_FD; i++) {
318 fd[i] = drive_get(IF_FLOPPY, 0, i);
319 }
320 dev = DEVICE(isa_create(s->isa_bus, TYPE_ISA_FDC));
321 if (fd[0]) {
322 qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fd[0]),
323 &error_abort);
324 }
325 if (fd[1]) {
326 qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fd[1]),
327 &error_abort);
328 }
329 qdev_prop_set_uint32(dev, "dma", -1);
330 qdev_init_nofail(dev);
331
332 /* Power */
333 dev = qdev_create(NULL, TYPE_SUN4U_POWER);
334 qdev_init_nofail(dev);
335 sbd = SYS_BUS_DEVICE(dev);
336 memory_region_add_subregion(pci_address_space_io(pci_dev), 0x7240,
337 sysbus_mmio_get_region(sbd, 0));
338
339 /* PCI */
340 pci_dev->config[0x04] = 0x06; // command = bus master, pci mem
341 pci_dev->config[0x05] = 0x00;
342 pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
343 pci_dev->config[0x07] = 0x03; // status = medium devsel
344 pci_dev->config[0x09] = 0x00; // programming i/f
345 pci_dev->config[0x0D] = 0x0a; // latency_timer
346
347 memory_region_init_alias(&s->bar0, OBJECT(s), "bar0", get_system_io(),
348 0, 0x1000000);
349 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
350 memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(),
351 0, 0x8000);
352 pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1);
353 }
354
355 static Property ebus_properties[] = {
356 DEFINE_PROP_UINT64("console-serial-base", EbusState,
357 console_serial_base, 0),
358 DEFINE_PROP_END_OF_LIST(),
359 };
360
361 static void ebus_class_init(ObjectClass *klass, void *data)
362 {
363 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
364 DeviceClass *dc = DEVICE_CLASS(klass);
365
366 k->realize = ebus_realize;
367 k->vendor_id = PCI_VENDOR_ID_SUN;
368 k->device_id = PCI_DEVICE_ID_SUN_EBUS;
369 k->revision = 0x01;
370 k->class_id = PCI_CLASS_BRIDGE_OTHER;
371 dc->props = ebus_properties;
372 }
373
374 static const TypeInfo ebus_info = {
375 .name = TYPE_EBUS,
376 .parent = TYPE_PCI_DEVICE,
377 .class_init = ebus_class_init,
378 .instance_size = sizeof(EbusState),
379 .interfaces = (InterfaceInfo[]) {
380 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
381 { },
382 },
383 };
384
385 #define TYPE_OPENPROM "openprom"
386 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM)
387
388 typedef struct PROMState {
389 SysBusDevice parent_obj;
390
391 MemoryRegion prom;
392 } PROMState;
393
394 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
395 {
396 hwaddr *base_addr = (hwaddr *)opaque;
397 return addr + *base_addr - PROM_VADDR;
398 }
399
400 /* Boot PROM (OpenBIOS) */
401 static void prom_init(hwaddr addr, const char *bios_name)
402 {
403 DeviceState *dev;
404 SysBusDevice *s;
405 char *filename;
406 int ret;
407
408 dev = qdev_create(NULL, TYPE_OPENPROM);
409 qdev_init_nofail(dev);
410 s = SYS_BUS_DEVICE(dev);
411
412 sysbus_mmio_map(s, 0, addr);
413
414 /* load boot prom */
415 if (bios_name == NULL) {
416 bios_name = PROM_FILENAME;
417 }
418 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
419 if (filename) {
420 ret = load_elf(filename, translate_prom_address, &addr,
421 NULL, NULL, NULL, 1, EM_SPARCV9, 0, 0);
422 if (ret < 0 || ret > PROM_SIZE_MAX) {
423 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
424 }
425 g_free(filename);
426 } else {
427 ret = -1;
428 }
429 if (ret < 0 || ret > PROM_SIZE_MAX) {
430 error_report("could not load prom '%s'", bios_name);
431 exit(1);
432 }
433 }
434
435 static void prom_realize(DeviceState *ds, Error **errp)
436 {
437 PROMState *s = OPENPROM(ds);
438 SysBusDevice *dev = SYS_BUS_DEVICE(ds);
439 Error *local_err = NULL;
440
441 memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4u.prom",
442 PROM_SIZE_MAX, &local_err);
443 if (local_err) {
444 error_propagate(errp, local_err);
445 return;
446 }
447
448 vmstate_register_ram_global(&s->prom);
449 memory_region_set_readonly(&s->prom, true);
450 sysbus_init_mmio(dev, &s->prom);
451 }
452
453 static Property prom_properties[] = {
454 {/* end of property list */},
455 };
456
457 static void prom_class_init(ObjectClass *klass, void *data)
458 {
459 DeviceClass *dc = DEVICE_CLASS(klass);
460
461 dc->props = prom_properties;
462 dc->realize = prom_realize;
463 }
464
465 static const TypeInfo prom_info = {
466 .name = TYPE_OPENPROM,
467 .parent = TYPE_SYS_BUS_DEVICE,
468 .instance_size = sizeof(PROMState),
469 .class_init = prom_class_init,
470 };
471
472
473 #define TYPE_SUN4U_MEMORY "memory"
474 #define SUN4U_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4U_MEMORY)
475
476 typedef struct RamDevice {
477 SysBusDevice parent_obj;
478
479 MemoryRegion ram;
480 uint64_t size;
481 } RamDevice;
482
483 /* System RAM */
484 static void ram_realize(DeviceState *dev, Error **errp)
485 {
486 RamDevice *d = SUN4U_RAM(dev);
487 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
488
489 memory_region_init_ram_nomigrate(&d->ram, OBJECT(d), "sun4u.ram", d->size,
490 &error_fatal);
491 vmstate_register_ram_global(&d->ram);
492 sysbus_init_mmio(sbd, &d->ram);
493 }
494
495 static void ram_init(hwaddr addr, ram_addr_t RAM_size)
496 {
497 DeviceState *dev;
498 SysBusDevice *s;
499 RamDevice *d;
500
501 /* allocate RAM */
502 dev = qdev_create(NULL, TYPE_SUN4U_MEMORY);
503 s = SYS_BUS_DEVICE(dev);
504
505 d = SUN4U_RAM(dev);
506 d->size = RAM_size;
507 qdev_init_nofail(dev);
508
509 sysbus_mmio_map(s, 0, addr);
510 }
511
512 static Property ram_properties[] = {
513 DEFINE_PROP_UINT64("size", RamDevice, size, 0),
514 DEFINE_PROP_END_OF_LIST(),
515 };
516
517 static void ram_class_init(ObjectClass *klass, void *data)
518 {
519 DeviceClass *dc = DEVICE_CLASS(klass);
520
521 dc->realize = ram_realize;
522 dc->props = ram_properties;
523 }
524
525 static const TypeInfo ram_info = {
526 .name = TYPE_SUN4U_MEMORY,
527 .parent = TYPE_SYS_BUS_DEVICE,
528 .instance_size = sizeof(RamDevice),
529 .class_init = ram_class_init,
530 };
531
532 static void sun4uv_init(MemoryRegion *address_space_mem,
533 MachineState *machine,
534 const struct hwdef *hwdef)
535 {
536 SPARCCPU *cpu;
537 Nvram *nvram;
538 unsigned int i;
539 uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry;
540 SabreState *sabre;
541 PCIBus *pci_bus, *pci_busA, *pci_busB;
542 PCIDevice *ebus, *pci_dev;
543 SysBusDevice *s;
544 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
545 DeviceState *iommu, *dev;
546 FWCfgState *fw_cfg;
547 NICInfo *nd;
548 MACAddr macaddr;
549 bool onboard_nic;
550
551 /* init CPUs */
552 cpu = sparc64_cpu_devinit(machine->cpu_type, hwdef->prom_addr);
553
554 /* IOMMU */
555 iommu = qdev_create(NULL, TYPE_SUN4U_IOMMU);
556 qdev_init_nofail(iommu);
557
558 /* set up devices */
559 ram_init(0, machine->ram_size);
560
561 prom_init(hwdef->prom_addr, bios_name);
562
563 /* Init sabre (PCI host bridge) */
564 sabre = SABRE_DEVICE(qdev_create(NULL, TYPE_SABRE));
565 qdev_prop_set_uint64(DEVICE(sabre), "special-base", PBM_SPECIAL_BASE);
566 qdev_prop_set_uint64(DEVICE(sabre), "mem-base", PBM_MEM_BASE);
567 object_property_set_link(OBJECT(sabre), OBJECT(iommu), "iommu",
568 &error_abort);
569 qdev_init_nofail(DEVICE(sabre));
570
571 /* Wire up PCI interrupts to CPU */
572 for (i = 0; i < IVEC_MAX; i++) {
573 qdev_connect_gpio_out_named(DEVICE(sabre), "ivec-irq", i,
574 qdev_get_gpio_in_named(DEVICE(cpu), "ivec-irq", i));
575 }
576
577 pci_bus = PCI_HOST_BRIDGE(sabre)->bus;
578 pci_busA = pci_bridge_get_sec_bus(sabre->bridgeA);
579 pci_busB = pci_bridge_get_sec_bus(sabre->bridgeB);
580
581 /* Only in-built Simba APBs can exist on the root bus, slot 0 on busA is
582 reserved (leaving no slots free after on-board devices) however slots
583 0-3 are free on busB */
584 pci_bus->slot_reserved_mask = 0xfffffffc;
585 pci_busA->slot_reserved_mask = 0xfffffff1;
586 pci_busB->slot_reserved_mask = 0xfffffff0;
587
588 ebus = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 0), true, TYPE_EBUS);
589 qdev_prop_set_uint64(DEVICE(ebus), "console-serial-base",
590 hwdef->console_serial_base);
591 qdev_init_nofail(DEVICE(ebus));
592
593 /* Wire up "well-known" ISA IRQs to PBM legacy obio IRQs */
594 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 7,
595 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_LPT_IRQ));
596 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 6,
597 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_FDD_IRQ));
598 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 1,
599 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_KBD_IRQ));
600 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 12,
601 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_MSE_IRQ));
602 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 4,
603 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_SER_IRQ));
604
605 switch (vga_interface_type) {
606 case VGA_STD:
607 pci_create_simple(pci_busA, PCI_DEVFN(2, 0), "VGA");
608 break;
609 case VGA_NONE:
610 break;
611 default:
612 abort(); /* Should not happen - types are checked in vl.c already */
613 }
614
615 memset(&macaddr, 0, sizeof(MACAddr));
616 onboard_nic = false;
617 for (i = 0; i < nb_nics; i++) {
618 nd = &nd_table[i];
619
620 if (!nd->model || strcmp(nd->model, "sunhme") == 0) {
621 if (!onboard_nic) {
622 pci_dev = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 1),
623 true, "sunhme");
624 memcpy(&macaddr, &nd->macaddr.a, sizeof(MACAddr));
625 onboard_nic = true;
626 } else {
627 pci_dev = pci_create(pci_busB, -1, "sunhme");
628 }
629 } else {
630 pci_dev = pci_create(pci_busB, -1, nd->model);
631 }
632
633 dev = &pci_dev->qdev;
634 qdev_set_nic_properties(dev, nd);
635 qdev_init_nofail(dev);
636 }
637
638 /* If we don't have an onboard NIC, grab a default MAC address so that
639 * we have a valid machine id */
640 if (!onboard_nic) {
641 qemu_macaddr_default_if_unset(&macaddr);
642 }
643
644 ide_drive_get(hd, ARRAY_SIZE(hd));
645
646 pci_dev = pci_create(pci_busA, PCI_DEVFN(3, 0), "cmd646-ide");
647 qdev_prop_set_uint32(&pci_dev->qdev, "secondary", 1);
648 qdev_init_nofail(&pci_dev->qdev);
649 pci_ide_create_devs(pci_dev, hd);
650
651 /* Map NVRAM into I/O (ebus) space */
652 nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59);
653 s = SYS_BUS_DEVICE(nvram);
654 memory_region_add_subregion(pci_address_space_io(ebus), 0x2000,
655 sysbus_mmio_get_region(s, 0));
656
657 initrd_size = 0;
658 initrd_addr = 0;
659 kernel_size = sun4u_load_kernel(machine->kernel_filename,
660 machine->initrd_filename,
661 ram_size, &initrd_size, &initrd_addr,
662 &kernel_addr, &kernel_entry);
663
664 sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size,
665 machine->boot_order,
666 kernel_addr, kernel_size,
667 machine->kernel_cmdline,
668 initrd_addr, initrd_size,
669 /* XXX: need an option to load a NVRAM image */
670 0,
671 graphic_width, graphic_height, graphic_depth,
672 (uint8_t *)&macaddr);
673
674 dev = qdev_create(NULL, TYPE_FW_CFG_IO);
675 qdev_prop_set_bit(dev, "dma_enabled", false);
676 object_property_add_child(OBJECT(ebus), TYPE_FW_CFG, OBJECT(dev), NULL);
677 qdev_init_nofail(dev);
678 memory_region_add_subregion(pci_address_space_io(ebus), BIOS_CFG_IOPORT,
679 &FW_CFG_IO(dev)->comb_iomem);
680
681 fw_cfg = FW_CFG(dev);
682 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
683 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
684 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
685 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
686 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry);
687 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
688 if (machine->kernel_cmdline) {
689 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
690 strlen(machine->kernel_cmdline) + 1);
691 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
692 } else {
693 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
694 }
695 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
696 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
697 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
698
699 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width);
700 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height);
701 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth);
702
703 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
704 }
705
706 enum {
707 sun4u_id = 0,
708 sun4v_id = 64,
709 };
710
711 /*
712 * Implementation of an interface to adjust firmware path
713 * for the bootindex property handling.
714 */
715 static char *sun4u_fw_dev_path(FWPathProvider *p, BusState *bus,
716 DeviceState *dev)
717 {
718 PCIDevice *pci;
719 IDEBus *ide_bus;
720 IDEState *ide_s;
721 int bus_id;
722
723 if (!strcmp(object_get_typename(OBJECT(dev)), "pbm-bridge")) {
724 pci = PCI_DEVICE(dev);
725
726 if (PCI_FUNC(pci->devfn)) {
727 return g_strdup_printf("pci@%x,%x", PCI_SLOT(pci->devfn),
728 PCI_FUNC(pci->devfn));
729 } else {
730 return g_strdup_printf("pci@%x", PCI_SLOT(pci->devfn));
731 }
732 }
733
734 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-drive")) {
735 ide_bus = IDE_BUS(qdev_get_parent_bus(dev));
736 ide_s = idebus_active_if(ide_bus);
737 bus_id = ide_bus->bus_id;
738
739 if (ide_s->drive_kind == IDE_CD) {
740 return g_strdup_printf("ide@%x/cdrom", bus_id);
741 }
742
743 return g_strdup_printf("ide@%x/disk", bus_id);
744 }
745
746 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) {
747 return g_strdup("disk");
748 }
749
750 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) {
751 return g_strdup("cdrom");
752 }
753
754 if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) {
755 return g_strdup("disk");
756 }
757
758 return NULL;
759 }
760
761 static const struct hwdef hwdefs[] = {
762 /* Sun4u generic PC-like machine */
763 {
764 .machine_id = sun4u_id,
765 .prom_addr = 0x1fff0000000ULL,
766 .console_serial_base = 0,
767 },
768 /* Sun4v generic PC-like machine */
769 {
770 .machine_id = sun4v_id,
771 .prom_addr = 0x1fff0000000ULL,
772 .console_serial_base = 0,
773 },
774 };
775
776 /* Sun4u hardware initialisation */
777 static void sun4u_init(MachineState *machine)
778 {
779 sun4uv_init(get_system_memory(), machine, &hwdefs[0]);
780 }
781
782 /* Sun4v hardware initialisation */
783 static void sun4v_init(MachineState *machine)
784 {
785 sun4uv_init(get_system_memory(), machine, &hwdefs[1]);
786 }
787
788 static void sun4u_class_init(ObjectClass *oc, void *data)
789 {
790 MachineClass *mc = MACHINE_CLASS(oc);
791 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
792
793 mc->desc = "Sun4u platform";
794 mc->init = sun4u_init;
795 mc->block_default_type = IF_IDE;
796 mc->max_cpus = 1; /* XXX for now */
797 mc->is_default = 1;
798 mc->default_boot_order = "c";
799 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-UltraSparc-IIi");
800 mc->ignore_boot_device_suffixes = true;
801 fwc->get_dev_path = sun4u_fw_dev_path;
802 }
803
804 static const TypeInfo sun4u_type = {
805 .name = MACHINE_TYPE_NAME("sun4u"),
806 .parent = TYPE_MACHINE,
807 .class_init = sun4u_class_init,
808 .interfaces = (InterfaceInfo[]) {
809 { TYPE_FW_PATH_PROVIDER },
810 { }
811 },
812 };
813
814 static void sun4v_class_init(ObjectClass *oc, void *data)
815 {
816 MachineClass *mc = MACHINE_CLASS(oc);
817
818 mc->desc = "Sun4v platform";
819 mc->init = sun4v_init;
820 mc->block_default_type = IF_IDE;
821 mc->max_cpus = 1; /* XXX for now */
822 mc->default_boot_order = "c";
823 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Sun-UltraSparc-T1");
824 }
825
826 static const TypeInfo sun4v_type = {
827 .name = MACHINE_TYPE_NAME("sun4v"),
828 .parent = TYPE_MACHINE,
829 .class_init = sun4v_class_init,
830 };
831
832 static void sun4u_register_types(void)
833 {
834 type_register_static(&power_info);
835 type_register_static(&ebus_info);
836 type_register_static(&prom_info);
837 type_register_static(&ram_info);
838
839 type_register_static(&sun4u_type);
840 type_register_static(&sun4v_type);
841 }
842
843 type_init(sun4u_register_types)