isa: Convert uses of isa_create() with Coccinelle
[qemu.git] / hw / sparc64 / sun4u.c
1 /*
2 * QEMU Sun4u/Sun4v System Emulator
3 *
4 * Copyright (c) 2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "qemu/error-report.h"
28 #include "qapi/error.h"
29 #include "qemu-common.h"
30 #include "cpu.h"
31 #include "hw/pci/pci.h"
32 #include "hw/pci/pci_bridge.h"
33 #include "hw/pci/pci_bus.h"
34 #include "hw/pci/pci_host.h"
35 #include "hw/qdev-properties.h"
36 #include "hw/pci-host/sabre.h"
37 #include "hw/char/serial.h"
38 #include "hw/char/parallel.h"
39 #include "hw/rtc/m48t59.h"
40 #include "migration/vmstate.h"
41 #include "hw/input/i8042.h"
42 #include "hw/block/fdc.h"
43 #include "net/net.h"
44 #include "qemu/timer.h"
45 #include "sysemu/runstate.h"
46 #include "sysemu/sysemu.h"
47 #include "hw/boards.h"
48 #include "hw/nvram/sun_nvram.h"
49 #include "hw/nvram/chrp_nvram.h"
50 #include "hw/sparc/sparc64.h"
51 #include "hw/nvram/fw_cfg.h"
52 #include "hw/sysbus.h"
53 #include "hw/ide/pci.h"
54 #include "hw/loader.h"
55 #include "hw/fw-path-provider.h"
56 #include "elf.h"
57 #include "trace.h"
58
59 #define KERNEL_LOAD_ADDR 0x00404000
60 #define CMDLINE_ADDR 0x003ff000
61 #define PROM_SIZE_MAX (4 * MiB)
62 #define PROM_VADDR 0x000ffd00000ULL
63 #define PBM_SPECIAL_BASE 0x1fe00000000ULL
64 #define PBM_MEM_BASE 0x1ff00000000ULL
65 #define PBM_PCI_IO_BASE (PBM_SPECIAL_BASE + 0x02000000ULL)
66 #define PROM_FILENAME "openbios-sparc64"
67 #define NVRAM_SIZE 0x2000
68 #define MAX_IDE_BUS 2
69 #define BIOS_CFG_IOPORT 0x510
70 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
71 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
72 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
73
74 #define IVEC_MAX 0x40
75
76 struct hwdef {
77 uint16_t machine_id;
78 uint64_t prom_addr;
79 uint64_t console_serial_base;
80 };
81
82 typedef struct EbusState {
83 /*< private >*/
84 PCIDevice parent_obj;
85
86 ISABus *isa_bus;
87 qemu_irq isa_bus_irqs[ISA_NUM_IRQS];
88 uint64_t console_serial_base;
89 MemoryRegion bar0;
90 MemoryRegion bar1;
91 } EbusState;
92
93 #define TYPE_EBUS "ebus"
94 #define EBUS(obj) OBJECT_CHECK(EbusState, (obj), TYPE_EBUS)
95
96 const char *fw_cfg_arch_key_name(uint16_t key)
97 {
98 static const struct {
99 uint16_t key;
100 const char *name;
101 } fw_cfg_arch_wellknown_keys[] = {
102 {FW_CFG_SPARC64_WIDTH, "width"},
103 {FW_CFG_SPARC64_HEIGHT, "height"},
104 {FW_CFG_SPARC64_DEPTH, "depth"},
105 };
106
107 for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) {
108 if (fw_cfg_arch_wellknown_keys[i].key == key) {
109 return fw_cfg_arch_wellknown_keys[i].name;
110 }
111 }
112 return NULL;
113 }
114
115 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
116 Error **errp)
117 {
118 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
119 }
120
121 static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size,
122 const char *arch, ram_addr_t RAM_size,
123 const char *boot_devices,
124 uint32_t kernel_image, uint32_t kernel_size,
125 const char *cmdline,
126 uint32_t initrd_image, uint32_t initrd_size,
127 uint32_t NVRAM_image,
128 int width, int height, int depth,
129 const uint8_t *macaddr)
130 {
131 unsigned int i;
132 int sysp_end;
133 uint8_t image[0x1ff0];
134 NvramClass *k = NVRAM_GET_CLASS(nvram);
135
136 memset(image, '\0', sizeof(image));
137
138 /* OpenBIOS nvram variables partition */
139 sysp_end = chrp_nvram_create_system_partition(image, 0);
140
141 /* Free space partition */
142 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end);
143
144 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
145
146 for (i = 0; i < sizeof(image); i++) {
147 (k->write)(nvram, i, image[i]);
148 }
149
150 return 0;
151 }
152
153 static uint64_t sun4u_load_kernel(const char *kernel_filename,
154 const char *initrd_filename,
155 ram_addr_t RAM_size, uint64_t *initrd_size,
156 uint64_t *initrd_addr, uint64_t *kernel_addr,
157 uint64_t *kernel_entry)
158 {
159 int linux_boot;
160 unsigned int i;
161 long kernel_size;
162 uint8_t *ptr;
163 uint64_t kernel_top = 0;
164
165 linux_boot = (kernel_filename != NULL);
166
167 kernel_size = 0;
168 if (linux_boot) {
169 int bswap_needed;
170
171 #ifdef BSWAP_NEEDED
172 bswap_needed = 1;
173 #else
174 bswap_needed = 0;
175 #endif
176 kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, kernel_entry,
177 kernel_addr, &kernel_top, NULL, 1, EM_SPARCV9, 0,
178 0);
179 if (kernel_size < 0) {
180 *kernel_addr = KERNEL_LOAD_ADDR;
181 *kernel_entry = KERNEL_LOAD_ADDR;
182 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
183 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
184 TARGET_PAGE_SIZE);
185 }
186 if (kernel_size < 0) {
187 kernel_size = load_image_targphys(kernel_filename,
188 KERNEL_LOAD_ADDR,
189 RAM_size - KERNEL_LOAD_ADDR);
190 }
191 if (kernel_size < 0) {
192 error_report("could not load kernel '%s'", kernel_filename);
193 exit(1);
194 }
195 /* load initrd above kernel */
196 *initrd_size = 0;
197 if (initrd_filename && kernel_top) {
198 *initrd_addr = TARGET_PAGE_ALIGN(kernel_top);
199
200 *initrd_size = load_image_targphys(initrd_filename,
201 *initrd_addr,
202 RAM_size - *initrd_addr);
203 if ((int)*initrd_size < 0) {
204 error_report("could not load initial ram disk '%s'",
205 initrd_filename);
206 exit(1);
207 }
208 }
209 if (*initrd_size > 0) {
210 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
211 ptr = rom_ptr(*kernel_addr + i, 32);
212 if (ptr && ldl_p(ptr + 8) == 0x48647253) { /* HdrS */
213 stl_p(ptr + 24, *initrd_addr + *kernel_addr);
214 stl_p(ptr + 28, *initrd_size);
215 break;
216 }
217 }
218 }
219 }
220 return kernel_size;
221 }
222
223 typedef struct ResetData {
224 SPARCCPU *cpu;
225 uint64_t prom_addr;
226 } ResetData;
227
228 #define TYPE_SUN4U_POWER "power"
229 #define SUN4U_POWER(obj) OBJECT_CHECK(PowerDevice, (obj), TYPE_SUN4U_POWER)
230
231 typedef struct PowerDevice {
232 SysBusDevice parent_obj;
233
234 MemoryRegion power_mmio;
235 } PowerDevice;
236
237 /* Power */
238 static uint64_t power_mem_read(void *opaque, hwaddr addr, unsigned size)
239 {
240 return 0;
241 }
242
243 static void power_mem_write(void *opaque, hwaddr addr,
244 uint64_t val, unsigned size)
245 {
246 /* According to a real Ultra 5, bit 24 controls the power */
247 if (val & 0x1000000) {
248 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
249 }
250 }
251
252 static const MemoryRegionOps power_mem_ops = {
253 .read = power_mem_read,
254 .write = power_mem_write,
255 .endianness = DEVICE_NATIVE_ENDIAN,
256 .valid = {
257 .min_access_size = 4,
258 .max_access_size = 4,
259 },
260 };
261
262 static void power_realize(DeviceState *dev, Error **errp)
263 {
264 PowerDevice *d = SUN4U_POWER(dev);
265 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
266
267 memory_region_init_io(&d->power_mmio, OBJECT(dev), &power_mem_ops, d,
268 "power", sizeof(uint32_t));
269
270 sysbus_init_mmio(sbd, &d->power_mmio);
271 }
272
273 static void power_class_init(ObjectClass *klass, void *data)
274 {
275 DeviceClass *dc = DEVICE_CLASS(klass);
276
277 dc->realize = power_realize;
278 }
279
280 static const TypeInfo power_info = {
281 .name = TYPE_SUN4U_POWER,
282 .parent = TYPE_SYS_BUS_DEVICE,
283 .instance_size = sizeof(PowerDevice),
284 .class_init = power_class_init,
285 };
286
287 static void ebus_isa_irq_handler(void *opaque, int n, int level)
288 {
289 EbusState *s = EBUS(opaque);
290 qemu_irq irq = s->isa_bus_irqs[n];
291
292 /* Pass ISA bus IRQs onto their gpio equivalent */
293 trace_ebus_isa_irq_handler(n, level);
294 if (irq) {
295 qemu_set_irq(irq, level);
296 }
297 }
298
299 /* EBUS (Eight bit bus) bridge */
300 static void ebus_realize(PCIDevice *pci_dev, Error **errp)
301 {
302 EbusState *s = EBUS(pci_dev);
303 ISADevice *isa_dev;
304 SysBusDevice *sbd;
305 DeviceState *dev;
306 qemu_irq *isa_irq;
307 DriveInfo *fd[MAX_FD];
308 int i;
309
310 s->isa_bus = isa_bus_new(DEVICE(pci_dev), get_system_memory(),
311 pci_address_space_io(pci_dev), errp);
312 if (!s->isa_bus) {
313 error_setg(errp, "unable to instantiate EBUS ISA bus");
314 return;
315 }
316
317 /* ISA bus */
318 isa_irq = qemu_allocate_irqs(ebus_isa_irq_handler, s, ISA_NUM_IRQS);
319 isa_bus_irqs(s->isa_bus, isa_irq);
320 qdev_init_gpio_out_named(DEVICE(s), s->isa_bus_irqs, "isa-irq",
321 ISA_NUM_IRQS);
322
323 /* Serial ports */
324 i = 0;
325 if (s->console_serial_base) {
326 serial_mm_init(pci_address_space(pci_dev), s->console_serial_base,
327 0, NULL, 115200, serial_hd(i), DEVICE_BIG_ENDIAN);
328 i++;
329 }
330 serial_hds_isa_init(s->isa_bus, i, MAX_ISA_SERIAL_PORTS);
331
332 /* Parallel ports */
333 parallel_hds_isa_init(s->isa_bus, MAX_PARALLEL_PORTS);
334
335 /* Keyboard */
336 isa_create_simple(s->isa_bus, "i8042");
337
338 /* Floppy */
339 for (i = 0; i < MAX_FD; i++) {
340 fd[i] = drive_get(IF_FLOPPY, 0, i);
341 }
342 isa_dev = isa_new(TYPE_ISA_FDC);
343 dev = DEVICE(isa_dev);
344 if (fd[0]) {
345 qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fd[0]),
346 &error_abort);
347 }
348 if (fd[1]) {
349 qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fd[1]),
350 &error_abort);
351 }
352 qdev_prop_set_uint32(dev, "dma", -1);
353 isa_realize_and_unref(isa_dev, s->isa_bus, &error_fatal);
354
355 /* Power */
356 dev = qdev_new(TYPE_SUN4U_POWER);
357 qdev_realize_and_unref(dev, NULL, &error_fatal);
358 sbd = SYS_BUS_DEVICE(dev);
359 memory_region_add_subregion(pci_address_space_io(pci_dev), 0x7240,
360 sysbus_mmio_get_region(sbd, 0));
361
362 /* PCI */
363 pci_dev->config[0x04] = 0x06; // command = bus master, pci mem
364 pci_dev->config[0x05] = 0x00;
365 pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
366 pci_dev->config[0x07] = 0x03; // status = medium devsel
367 pci_dev->config[0x09] = 0x00; // programming i/f
368 pci_dev->config[0x0D] = 0x0a; // latency_timer
369
370 memory_region_init_alias(&s->bar0, OBJECT(s), "bar0", get_system_io(),
371 0, 0x1000000);
372 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
373 memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(),
374 0, 0x8000);
375 pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1);
376 }
377
378 static Property ebus_properties[] = {
379 DEFINE_PROP_UINT64("console-serial-base", EbusState,
380 console_serial_base, 0),
381 DEFINE_PROP_END_OF_LIST(),
382 };
383
384 static void ebus_class_init(ObjectClass *klass, void *data)
385 {
386 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
387 DeviceClass *dc = DEVICE_CLASS(klass);
388
389 k->realize = ebus_realize;
390 k->vendor_id = PCI_VENDOR_ID_SUN;
391 k->device_id = PCI_DEVICE_ID_SUN_EBUS;
392 k->revision = 0x01;
393 k->class_id = PCI_CLASS_BRIDGE_OTHER;
394 device_class_set_props(dc, ebus_properties);
395 }
396
397 static const TypeInfo ebus_info = {
398 .name = TYPE_EBUS,
399 .parent = TYPE_PCI_DEVICE,
400 .class_init = ebus_class_init,
401 .instance_size = sizeof(EbusState),
402 .interfaces = (InterfaceInfo[]) {
403 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
404 { },
405 },
406 };
407
408 #define TYPE_OPENPROM "openprom"
409 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM)
410
411 typedef struct PROMState {
412 SysBusDevice parent_obj;
413
414 MemoryRegion prom;
415 } PROMState;
416
417 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
418 {
419 hwaddr *base_addr = (hwaddr *)opaque;
420 return addr + *base_addr - PROM_VADDR;
421 }
422
423 /* Boot PROM (OpenBIOS) */
424 static void prom_init(hwaddr addr, const char *bios_name)
425 {
426 DeviceState *dev;
427 SysBusDevice *s;
428 char *filename;
429 int ret;
430
431 dev = qdev_new(TYPE_OPENPROM);
432 qdev_realize_and_unref(dev, NULL, &error_fatal);
433 s = SYS_BUS_DEVICE(dev);
434
435 sysbus_mmio_map(s, 0, addr);
436
437 /* load boot prom */
438 if (bios_name == NULL) {
439 bios_name = PROM_FILENAME;
440 }
441 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
442 if (filename) {
443 ret = load_elf(filename, NULL, translate_prom_address, &addr,
444 NULL, NULL, NULL, NULL, 1, EM_SPARCV9, 0, 0);
445 if (ret < 0 || ret > PROM_SIZE_MAX) {
446 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
447 }
448 g_free(filename);
449 } else {
450 ret = -1;
451 }
452 if (ret < 0 || ret > PROM_SIZE_MAX) {
453 error_report("could not load prom '%s'", bios_name);
454 exit(1);
455 }
456 }
457
458 static void prom_realize(DeviceState *ds, Error **errp)
459 {
460 PROMState *s = OPENPROM(ds);
461 SysBusDevice *dev = SYS_BUS_DEVICE(ds);
462 Error *local_err = NULL;
463
464 memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4u.prom",
465 PROM_SIZE_MAX, &local_err);
466 if (local_err) {
467 error_propagate(errp, local_err);
468 return;
469 }
470
471 vmstate_register_ram_global(&s->prom);
472 memory_region_set_readonly(&s->prom, true);
473 sysbus_init_mmio(dev, &s->prom);
474 }
475
476 static Property prom_properties[] = {
477 {/* end of property list */},
478 };
479
480 static void prom_class_init(ObjectClass *klass, void *data)
481 {
482 DeviceClass *dc = DEVICE_CLASS(klass);
483
484 device_class_set_props(dc, prom_properties);
485 dc->realize = prom_realize;
486 }
487
488 static const TypeInfo prom_info = {
489 .name = TYPE_OPENPROM,
490 .parent = TYPE_SYS_BUS_DEVICE,
491 .instance_size = sizeof(PROMState),
492 .class_init = prom_class_init,
493 };
494
495
496 #define TYPE_SUN4U_MEMORY "memory"
497 #define SUN4U_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4U_MEMORY)
498
499 typedef struct RamDevice {
500 SysBusDevice parent_obj;
501
502 MemoryRegion ram;
503 uint64_t size;
504 } RamDevice;
505
506 /* System RAM */
507 static void ram_realize(DeviceState *dev, Error **errp)
508 {
509 RamDevice *d = SUN4U_RAM(dev);
510 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
511
512 memory_region_init_ram_nomigrate(&d->ram, OBJECT(d), "sun4u.ram", d->size,
513 &error_fatal);
514 vmstate_register_ram_global(&d->ram);
515 sysbus_init_mmio(sbd, &d->ram);
516 }
517
518 static void ram_init(hwaddr addr, ram_addr_t RAM_size)
519 {
520 DeviceState *dev;
521 SysBusDevice *s;
522 RamDevice *d;
523
524 /* allocate RAM */
525 dev = qdev_new(TYPE_SUN4U_MEMORY);
526 s = SYS_BUS_DEVICE(dev);
527
528 d = SUN4U_RAM(dev);
529 d->size = RAM_size;
530 qdev_realize_and_unref(dev, NULL, &error_fatal);
531
532 sysbus_mmio_map(s, 0, addr);
533 }
534
535 static Property ram_properties[] = {
536 DEFINE_PROP_UINT64("size", RamDevice, size, 0),
537 DEFINE_PROP_END_OF_LIST(),
538 };
539
540 static void ram_class_init(ObjectClass *klass, void *data)
541 {
542 DeviceClass *dc = DEVICE_CLASS(klass);
543
544 dc->realize = ram_realize;
545 device_class_set_props(dc, ram_properties);
546 }
547
548 static const TypeInfo ram_info = {
549 .name = TYPE_SUN4U_MEMORY,
550 .parent = TYPE_SYS_BUS_DEVICE,
551 .instance_size = sizeof(RamDevice),
552 .class_init = ram_class_init,
553 };
554
555 static void sun4uv_init(MemoryRegion *address_space_mem,
556 MachineState *machine,
557 const struct hwdef *hwdef)
558 {
559 SPARCCPU *cpu;
560 Nvram *nvram;
561 unsigned int i;
562 uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry;
563 SabreState *sabre;
564 PCIBus *pci_bus, *pci_busA, *pci_busB;
565 PCIDevice *ebus, *pci_dev;
566 SysBusDevice *s;
567 DeviceState *iommu, *dev;
568 FWCfgState *fw_cfg;
569 NICInfo *nd;
570 MACAddr macaddr;
571 bool onboard_nic;
572
573 /* init CPUs */
574 cpu = sparc64_cpu_devinit(machine->cpu_type, hwdef->prom_addr);
575
576 /* IOMMU */
577 iommu = qdev_new(TYPE_SUN4U_IOMMU);
578 qdev_realize_and_unref(iommu, NULL, &error_fatal);
579
580 /* set up devices */
581 ram_init(0, machine->ram_size);
582
583 prom_init(hwdef->prom_addr, bios_name);
584
585 /* Init sabre (PCI host bridge) */
586 sabre = SABRE_DEVICE(qdev_new(TYPE_SABRE));
587 qdev_prop_set_uint64(DEVICE(sabre), "special-base", PBM_SPECIAL_BASE);
588 qdev_prop_set_uint64(DEVICE(sabre), "mem-base", PBM_MEM_BASE);
589 object_property_set_link(OBJECT(sabre), OBJECT(iommu), "iommu",
590 &error_abort);
591 qdev_realize_and_unref(DEVICE(sabre), NULL, &error_fatal);
592
593 /* Wire up PCI interrupts to CPU */
594 for (i = 0; i < IVEC_MAX; i++) {
595 qdev_connect_gpio_out_named(DEVICE(sabre), "ivec-irq", i,
596 qdev_get_gpio_in_named(DEVICE(cpu), "ivec-irq", i));
597 }
598
599 pci_bus = PCI_HOST_BRIDGE(sabre)->bus;
600 pci_busA = pci_bridge_get_sec_bus(sabre->bridgeA);
601 pci_busB = pci_bridge_get_sec_bus(sabre->bridgeB);
602
603 /* Only in-built Simba APBs can exist on the root bus, slot 0 on busA is
604 reserved (leaving no slots free after on-board devices) however slots
605 0-3 are free on busB */
606 pci_bus->slot_reserved_mask = 0xfffffffc;
607 pci_busA->slot_reserved_mask = 0xfffffff1;
608 pci_busB->slot_reserved_mask = 0xfffffff0;
609
610 ebus = pci_new_multifunction(PCI_DEVFN(1, 0), true, TYPE_EBUS);
611 qdev_prop_set_uint64(DEVICE(ebus), "console-serial-base",
612 hwdef->console_serial_base);
613 pci_realize_and_unref(ebus, pci_busA, &error_fatal);
614
615 /* Wire up "well-known" ISA IRQs to PBM legacy obio IRQs */
616 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 7,
617 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_LPT_IRQ));
618 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 6,
619 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_FDD_IRQ));
620 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 1,
621 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_KBD_IRQ));
622 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 12,
623 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_MSE_IRQ));
624 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 4,
625 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_SER_IRQ));
626
627 switch (vga_interface_type) {
628 case VGA_STD:
629 pci_create_simple(pci_busA, PCI_DEVFN(2, 0), "VGA");
630 break;
631 case VGA_NONE:
632 break;
633 default:
634 abort(); /* Should not happen - types are checked in vl.c already */
635 }
636
637 memset(&macaddr, 0, sizeof(MACAddr));
638 onboard_nic = false;
639 for (i = 0; i < nb_nics; i++) {
640 PCIBus *bus;
641 nd = &nd_table[i];
642
643 if (!nd->model || strcmp(nd->model, "sunhme") == 0) {
644 if (!onboard_nic) {
645 pci_dev = pci_new_multifunction(PCI_DEVFN(1, 1),
646 true, "sunhme");
647 bus = pci_busA;
648 memcpy(&macaddr, &nd->macaddr.a, sizeof(MACAddr));
649 onboard_nic = true;
650 } else {
651 pci_dev = pci_new(-1, "sunhme");
652 bus = pci_busB;
653 }
654 } else {
655 pci_dev = pci_new(-1, nd->model);
656 bus = pci_busB;
657 }
658
659 dev = &pci_dev->qdev;
660 qdev_set_nic_properties(dev, nd);
661 pci_realize_and_unref(pci_dev, bus, &error_fatal);
662 }
663
664 /* If we don't have an onboard NIC, grab a default MAC address so that
665 * we have a valid machine id */
666 if (!onboard_nic) {
667 qemu_macaddr_default_if_unset(&macaddr);
668 }
669
670 pci_dev = pci_new(PCI_DEVFN(3, 0), "cmd646-ide");
671 qdev_prop_set_uint32(&pci_dev->qdev, "secondary", 1);
672 pci_realize_and_unref(pci_dev, pci_busA, &error_fatal);
673 pci_ide_create_devs(pci_dev);
674
675 /* Map NVRAM into I/O (ebus) space */
676 nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59);
677 s = SYS_BUS_DEVICE(nvram);
678 memory_region_add_subregion(pci_address_space_io(ebus), 0x2000,
679 sysbus_mmio_get_region(s, 0));
680
681 initrd_size = 0;
682 initrd_addr = 0;
683 kernel_size = sun4u_load_kernel(machine->kernel_filename,
684 machine->initrd_filename,
685 ram_size, &initrd_size, &initrd_addr,
686 &kernel_addr, &kernel_entry);
687
688 sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size,
689 machine->boot_order,
690 kernel_addr, kernel_size,
691 machine->kernel_cmdline,
692 initrd_addr, initrd_size,
693 /* XXX: need an option to load a NVRAM image */
694 0,
695 graphic_width, graphic_height, graphic_depth,
696 (uint8_t *)&macaddr);
697
698 dev = qdev_new(TYPE_FW_CFG_IO);
699 qdev_prop_set_bit(dev, "dma_enabled", false);
700 object_property_add_child(OBJECT(ebus), TYPE_FW_CFG, OBJECT(dev));
701 qdev_realize_and_unref(dev, NULL, &error_fatal);
702 memory_region_add_subregion(pci_address_space_io(ebus), BIOS_CFG_IOPORT,
703 &FW_CFG_IO(dev)->comb_iomem);
704
705 fw_cfg = FW_CFG(dev);
706 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)machine->smp.cpus);
707 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus);
708 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
709 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
710 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry);
711 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
712 if (machine->kernel_cmdline) {
713 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
714 strlen(machine->kernel_cmdline) + 1);
715 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
716 } else {
717 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
718 }
719 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
720 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
721 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
722
723 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width);
724 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height);
725 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth);
726
727 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
728 }
729
730 enum {
731 sun4u_id = 0,
732 sun4v_id = 64,
733 };
734
735 /*
736 * Implementation of an interface to adjust firmware path
737 * for the bootindex property handling.
738 */
739 static char *sun4u_fw_dev_path(FWPathProvider *p, BusState *bus,
740 DeviceState *dev)
741 {
742 PCIDevice *pci;
743 IDEBus *ide_bus;
744 IDEState *ide_s;
745 int bus_id;
746
747 if (!strcmp(object_get_typename(OBJECT(dev)), "pbm-bridge")) {
748 pci = PCI_DEVICE(dev);
749
750 if (PCI_FUNC(pci->devfn)) {
751 return g_strdup_printf("pci@%x,%x", PCI_SLOT(pci->devfn),
752 PCI_FUNC(pci->devfn));
753 } else {
754 return g_strdup_printf("pci@%x", PCI_SLOT(pci->devfn));
755 }
756 }
757
758 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-drive")) {
759 ide_bus = IDE_BUS(qdev_get_parent_bus(dev));
760 ide_s = idebus_active_if(ide_bus);
761 bus_id = ide_bus->bus_id;
762
763 if (ide_s->drive_kind == IDE_CD) {
764 return g_strdup_printf("ide@%x/cdrom", bus_id);
765 }
766
767 return g_strdup_printf("ide@%x/disk", bus_id);
768 }
769
770 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) {
771 return g_strdup("disk");
772 }
773
774 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) {
775 return g_strdup("cdrom");
776 }
777
778 if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) {
779 return g_strdup("disk");
780 }
781
782 return NULL;
783 }
784
785 static const struct hwdef hwdefs[] = {
786 /* Sun4u generic PC-like machine */
787 {
788 .machine_id = sun4u_id,
789 .prom_addr = 0x1fff0000000ULL,
790 .console_serial_base = 0,
791 },
792 /* Sun4v generic PC-like machine */
793 {
794 .machine_id = sun4v_id,
795 .prom_addr = 0x1fff0000000ULL,
796 .console_serial_base = 0,
797 },
798 };
799
800 /* Sun4u hardware initialisation */
801 static void sun4u_init(MachineState *machine)
802 {
803 sun4uv_init(get_system_memory(), machine, &hwdefs[0]);
804 }
805
806 /* Sun4v hardware initialisation */
807 static void sun4v_init(MachineState *machine)
808 {
809 sun4uv_init(get_system_memory(), machine, &hwdefs[1]);
810 }
811
812 static void sun4u_class_init(ObjectClass *oc, void *data)
813 {
814 MachineClass *mc = MACHINE_CLASS(oc);
815 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
816
817 mc->desc = "Sun4u platform";
818 mc->init = sun4u_init;
819 mc->block_default_type = IF_IDE;
820 mc->max_cpus = 1; /* XXX for now */
821 mc->is_default = true;
822 mc->default_boot_order = "c";
823 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-UltraSparc-IIi");
824 mc->ignore_boot_device_suffixes = true;
825 mc->default_display = "std";
826 fwc->get_dev_path = sun4u_fw_dev_path;
827 }
828
829 static const TypeInfo sun4u_type = {
830 .name = MACHINE_TYPE_NAME("sun4u"),
831 .parent = TYPE_MACHINE,
832 .class_init = sun4u_class_init,
833 .interfaces = (InterfaceInfo[]) {
834 { TYPE_FW_PATH_PROVIDER },
835 { }
836 },
837 };
838
839 static void sun4v_class_init(ObjectClass *oc, void *data)
840 {
841 MachineClass *mc = MACHINE_CLASS(oc);
842
843 mc->desc = "Sun4v platform";
844 mc->init = sun4v_init;
845 mc->block_default_type = IF_IDE;
846 mc->max_cpus = 1; /* XXX for now */
847 mc->default_boot_order = "c";
848 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Sun-UltraSparc-T1");
849 mc->default_display = "std";
850 }
851
852 static const TypeInfo sun4v_type = {
853 .name = MACHINE_TYPE_NAME("sun4v"),
854 .parent = TYPE_MACHINE,
855 .class_init = sun4v_class_init,
856 };
857
858 static void sun4u_register_types(void)
859 {
860 type_register_static(&power_info);
861 type_register_static(&ebus_info);
862 type_register_static(&prom_info);
863 type_register_static(&ram_info);
864
865 type_register_static(&sun4u_type);
866 type_register_static(&sun4v_type);
867 }
868
869 type_init(sun4u_register_types)