hw/arm/bcm2836: Only provide "enabled-cpus" property to multicore SoCs
[qemu.git] / hw / ssi / imx_spi.c
1 /*
2 * IMX SPI Controller
3 *
4 * Copyright (c) 2016 Jean-Christophe Dubois <jcd@tribudubois.net>
5 *
6 * This work is licensed under the terms of the GNU GPL, version 2 or later.
7 * See the COPYING file in the top-level directory.
8 *
9 */
10
11 #include "qemu/osdep.h"
12 #include "hw/irq.h"
13 #include "hw/ssi/imx_spi.h"
14 #include "migration/vmstate.h"
15 #include "qemu/log.h"
16 #include "qemu/module.h"
17
18 #ifndef DEBUG_IMX_SPI
19 #define DEBUG_IMX_SPI 0
20 #endif
21
22 #define DPRINTF(fmt, args...) \
23 do { \
24 if (DEBUG_IMX_SPI) { \
25 fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_SPI, \
26 __func__, ##args); \
27 } \
28 } while (0)
29
30 static const char *imx_spi_reg_name(uint32_t reg)
31 {
32 static char unknown[20];
33
34 switch (reg) {
35 case ECSPI_RXDATA:
36 return "ECSPI_RXDATA";
37 case ECSPI_TXDATA:
38 return "ECSPI_TXDATA";
39 case ECSPI_CONREG:
40 return "ECSPI_CONREG";
41 case ECSPI_CONFIGREG:
42 return "ECSPI_CONFIGREG";
43 case ECSPI_INTREG:
44 return "ECSPI_INTREG";
45 case ECSPI_DMAREG:
46 return "ECSPI_DMAREG";
47 case ECSPI_STATREG:
48 return "ECSPI_STATREG";
49 case ECSPI_PERIODREG:
50 return "ECSPI_PERIODREG";
51 case ECSPI_TESTREG:
52 return "ECSPI_TESTREG";
53 case ECSPI_MSGDATA:
54 return "ECSPI_MSGDATA";
55 default:
56 sprintf(unknown, "%d ?", reg);
57 return unknown;
58 }
59 }
60
61 static const VMStateDescription vmstate_imx_spi = {
62 .name = TYPE_IMX_SPI,
63 .version_id = 1,
64 .minimum_version_id = 1,
65 .fields = (VMStateField[]) {
66 VMSTATE_FIFO32(tx_fifo, IMXSPIState),
67 VMSTATE_FIFO32(rx_fifo, IMXSPIState),
68 VMSTATE_INT16(burst_length, IMXSPIState),
69 VMSTATE_UINT32_ARRAY(regs, IMXSPIState, ECSPI_MAX),
70 VMSTATE_END_OF_LIST()
71 },
72 };
73
74 static void imx_spi_txfifo_reset(IMXSPIState *s)
75 {
76 fifo32_reset(&s->tx_fifo);
77 s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TE;
78 s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_TF;
79 }
80
81 static void imx_spi_rxfifo_reset(IMXSPIState *s)
82 {
83 fifo32_reset(&s->rx_fifo);
84 s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RR;
85 s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RF;
86 s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RO;
87 }
88
89 static void imx_spi_update_irq(IMXSPIState *s)
90 {
91 int level;
92
93 if (fifo32_is_empty(&s->rx_fifo)) {
94 s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RR;
95 } else {
96 s->regs[ECSPI_STATREG] |= ECSPI_STATREG_RR;
97 }
98
99 if (fifo32_is_full(&s->rx_fifo)) {
100 s->regs[ECSPI_STATREG] |= ECSPI_STATREG_RF;
101 } else {
102 s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RF;
103 }
104
105 if (fifo32_is_empty(&s->tx_fifo)) {
106 s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TE;
107 } else {
108 s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_TE;
109 }
110
111 if (fifo32_is_full(&s->tx_fifo)) {
112 s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TF;
113 } else {
114 s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_TF;
115 }
116
117 level = s->regs[ECSPI_STATREG] & s->regs[ECSPI_INTREG] ? 1 : 0;
118
119 qemu_set_irq(s->irq, level);
120
121 DPRINTF("IRQ level is %d\n", level);
122 }
123
124 static uint8_t imx_spi_selected_channel(IMXSPIState *s)
125 {
126 return EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_CHANNEL_SELECT);
127 }
128
129 static uint32_t imx_spi_burst_length(IMXSPIState *s)
130 {
131 return EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_BURST_LENGTH) + 1;
132 }
133
134 static bool imx_spi_is_enabled(IMXSPIState *s)
135 {
136 return s->regs[ECSPI_CONREG] & ECSPI_CONREG_EN;
137 }
138
139 static bool imx_spi_channel_is_master(IMXSPIState *s)
140 {
141 uint8_t mode = EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_CHANNEL_MODE);
142
143 return (mode & (1 << imx_spi_selected_channel(s))) ? true : false;
144 }
145
146 static bool imx_spi_is_multiple_master_burst(IMXSPIState *s)
147 {
148 uint8_t wave = EXTRACT(s->regs[ECSPI_CONFIGREG], ECSPI_CONFIGREG_SS_CTL);
149
150 return imx_spi_channel_is_master(s) &&
151 !(s->regs[ECSPI_CONREG] & ECSPI_CONREG_SMC) &&
152 ((wave & (1 << imx_spi_selected_channel(s))) ? true : false);
153 }
154
155 static void imx_spi_flush_txfifo(IMXSPIState *s)
156 {
157 uint32_t tx;
158 uint32_t rx;
159
160 DPRINTF("Begin: TX Fifo Size = %d, RX Fifo Size = %d\n",
161 fifo32_num_used(&s->tx_fifo), fifo32_num_used(&s->rx_fifo));
162
163 while (!fifo32_is_empty(&s->tx_fifo)) {
164 int tx_burst = 0;
165 int index = 0;
166
167 if (s->burst_length <= 0) {
168 s->burst_length = imx_spi_burst_length(s);
169
170 DPRINTF("Burst length = %d\n", s->burst_length);
171
172 if (imx_spi_is_multiple_master_burst(s)) {
173 s->regs[ECSPI_CONREG] |= ECSPI_CONREG_XCH;
174 }
175 }
176
177 tx = fifo32_pop(&s->tx_fifo);
178
179 DPRINTF("data tx:0x%08x\n", tx);
180
181 tx_burst = MIN(s->burst_length, 32);
182
183 rx = 0;
184
185 while (tx_burst > 0) {
186 uint8_t byte = tx & 0xff;
187
188 DPRINTF("writing 0x%02x\n", (uint32_t)byte);
189
190 /* We need to write one byte at a time */
191 byte = ssi_transfer(s->bus, byte);
192
193 DPRINTF("0x%02x read\n", (uint32_t)byte);
194
195 tx = tx >> 8;
196 rx |= (byte << (index * 8));
197
198 /* Remove 8 bits from the actual burst */
199 tx_burst -= 8;
200 s->burst_length -= 8;
201 index++;
202 }
203
204 DPRINTF("data rx:0x%08x\n", rx);
205
206 if (fifo32_is_full(&s->rx_fifo)) {
207 s->regs[ECSPI_STATREG] |= ECSPI_STATREG_RO;
208 } else {
209 fifo32_push(&s->rx_fifo, rx);
210 }
211
212 if (s->burst_length <= 0) {
213 if (!imx_spi_is_multiple_master_burst(s)) {
214 s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TC;
215 break;
216 }
217 }
218 }
219
220 if (fifo32_is_empty(&s->tx_fifo)) {
221 s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TC;
222 s->regs[ECSPI_CONREG] &= ~ECSPI_CONREG_XCH;
223 }
224
225 /* TODO: We should also use TDR and RDR bits */
226
227 DPRINTF("End: TX Fifo Size = %d, RX Fifo Size = %d\n",
228 fifo32_num_used(&s->tx_fifo), fifo32_num_used(&s->rx_fifo));
229 }
230
231 static void imx_spi_reset(DeviceState *dev)
232 {
233 IMXSPIState *s = IMX_SPI(dev);
234
235 DPRINTF("\n");
236
237 memset(s->regs, 0, sizeof(s->regs));
238
239 s->regs[ECSPI_STATREG] = 0x00000003;
240
241 imx_spi_rxfifo_reset(s);
242 imx_spi_txfifo_reset(s);
243
244 imx_spi_update_irq(s);
245
246 s->burst_length = 0;
247 }
248
249 static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size)
250 {
251 uint32_t value = 0;
252 IMXSPIState *s = opaque;
253 uint32_t index = offset >> 2;
254
255 if (index >= ECSPI_MAX) {
256 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
257 HWADDR_PRIx "\n", TYPE_IMX_SPI, __func__, offset);
258 return 0;
259 }
260
261 switch (index) {
262 case ECSPI_RXDATA:
263 if (!imx_spi_is_enabled(s)) {
264 value = 0;
265 } else if (fifo32_is_empty(&s->rx_fifo)) {
266 /* value is undefined */
267 value = 0xdeadbeef;
268 } else {
269 /* read from the RX FIFO */
270 value = fifo32_pop(&s->rx_fifo);
271 }
272
273 break;
274 case ECSPI_TXDATA:
275 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read from TX FIFO\n",
276 TYPE_IMX_SPI, __func__);
277
278 /* Reading from TXDATA gives 0 */
279
280 break;
281 case ECSPI_MSGDATA:
282 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read from MSG FIFO\n",
283 TYPE_IMX_SPI, __func__);
284
285 /* Reading from MSGDATA gives 0 */
286
287 break;
288 default:
289 value = s->regs[index];
290 break;
291 }
292
293 DPRINTF("reg[%s] => 0x%" PRIx32 "\n", imx_spi_reg_name(index), value);
294
295 imx_spi_update_irq(s);
296
297 return (uint64_t)value;
298 }
299
300 static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value,
301 unsigned size)
302 {
303 IMXSPIState *s = opaque;
304 uint32_t index = offset >> 2;
305 uint32_t change_mask;
306
307 if (index >= ECSPI_MAX) {
308 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
309 HWADDR_PRIx "\n", TYPE_IMX_SPI, __func__, offset);
310 return;
311 }
312
313 DPRINTF("reg[%s] <= 0x%" PRIx32 "\n", imx_spi_reg_name(index),
314 (uint32_t)value);
315
316 change_mask = s->regs[index] ^ value;
317
318 switch (index) {
319 case ECSPI_RXDATA:
320 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to write to RX FIFO\n",
321 TYPE_IMX_SPI, __func__);
322 break;
323 case ECSPI_TXDATA:
324 if (!imx_spi_is_enabled(s)) {
325 /* Ignore writes if device is disabled */
326 break;
327 } else if (fifo32_is_full(&s->tx_fifo)) {
328 /* Ignore writes if queue is full */
329 break;
330 }
331
332 fifo32_push(&s->tx_fifo, (uint32_t)value);
333
334 if (imx_spi_channel_is_master(s) &&
335 (s->regs[ECSPI_CONREG] & ECSPI_CONREG_SMC)) {
336 /*
337 * Start emitting if current channel is master and SMC bit is
338 * set.
339 */
340 imx_spi_flush_txfifo(s);
341 }
342
343 break;
344 case ECSPI_STATREG:
345 /* the RO and TC bits are write-one-to-clear */
346 value &= ECSPI_STATREG_RO | ECSPI_STATREG_TC;
347 s->regs[ECSPI_STATREG] &= ~value;
348
349 break;
350 case ECSPI_CONREG:
351 s->regs[ECSPI_CONREG] = value;
352
353 if (!imx_spi_is_enabled(s)) {
354 /* device is disabled, so this is a reset */
355 imx_spi_reset(DEVICE(s));
356 return;
357 }
358
359 if (imx_spi_channel_is_master(s)) {
360 int i;
361
362 /* We are in master mode */
363
364 for (i = 0; i < 4; i++) {
365 qemu_set_irq(s->cs_lines[i],
366 i == imx_spi_selected_channel(s) ? 0 : 1);
367 }
368
369 if ((value & change_mask & ECSPI_CONREG_SMC) &&
370 !fifo32_is_empty(&s->tx_fifo)) {
371 /* SMC bit is set and TX FIFO has some slots filled in */
372 imx_spi_flush_txfifo(s);
373 } else if ((value & change_mask & ECSPI_CONREG_XCH) &&
374 !(value & ECSPI_CONREG_SMC)) {
375 /* This is a request to start emitting */
376 imx_spi_flush_txfifo(s);
377 }
378 }
379
380 break;
381 case ECSPI_MSGDATA:
382 /* it is not clear from the spec what MSGDATA is for */
383 /* Anyway it is not used by Linux driver */
384 /* So for now we just ignore it */
385 qemu_log_mask(LOG_UNIMP,
386 "[%s]%s: Trying to write to MSGDATA, ignoring\n",
387 TYPE_IMX_SPI, __func__);
388 break;
389 default:
390 s->regs[index] = value;
391
392 break;
393 }
394
395 imx_spi_update_irq(s);
396 }
397
398 static const struct MemoryRegionOps imx_spi_ops = {
399 .read = imx_spi_read,
400 .write = imx_spi_write,
401 .endianness = DEVICE_NATIVE_ENDIAN,
402 .valid = {
403 /*
404 * Our device would not work correctly if the guest was doing
405 * unaligned access. This might not be a limitation on the real
406 * device but in practice there is no reason for a guest to access
407 * this device unaligned.
408 */
409 .min_access_size = 4,
410 .max_access_size = 4,
411 .unaligned = false,
412 },
413 };
414
415 static void imx_spi_realize(DeviceState *dev, Error **errp)
416 {
417 IMXSPIState *s = IMX_SPI(dev);
418 int i;
419
420 s->bus = ssi_create_bus(dev, "spi");
421
422 memory_region_init_io(&s->iomem, OBJECT(dev), &imx_spi_ops, s,
423 TYPE_IMX_SPI, 0x1000);
424 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
425 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
426
427 for (i = 0; i < 4; ++i) {
428 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->cs_lines[i]);
429 }
430
431 s->burst_length = 0;
432
433 fifo32_create(&s->tx_fifo, ECSPI_FIFO_SIZE);
434 fifo32_create(&s->rx_fifo, ECSPI_FIFO_SIZE);
435 }
436
437 static void imx_spi_class_init(ObjectClass *klass, void *data)
438 {
439 DeviceClass *dc = DEVICE_CLASS(klass);
440
441 dc->realize = imx_spi_realize;
442 dc->vmsd = &vmstate_imx_spi;
443 dc->reset = imx_spi_reset;
444 dc->desc = "i.MX SPI Controller";
445 }
446
447 static const TypeInfo imx_spi_info = {
448 .name = TYPE_IMX_SPI,
449 .parent = TYPE_SYS_BUS_DEVICE,
450 .instance_size = sizeof(IMXSPIState),
451 .class_init = imx_spi_class_init,
452 };
453
454 static void imx_spi_register_types(void)
455 {
456 type_register_static(&imx_spi_info);
457 }
458
459 type_init(imx_spi_register_types)