hw/arm/raspi: fix CPRMAN base address
[qemu.git] / hw / ssi / ssi.c
1 /*
2 * QEMU Synchronous Serial Interface support
3 *
4 * Copyright (c) 2009 CodeSourcery.
5 * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com)
6 * Copyright (c) 2012 PetaLogix Pty Ltd.
7 * Written by Paul Brook
8 *
9 * This code is licensed under the GNU GPL v2.
10 *
11 * Contributions after 2012-01-13 are licensed under the terms of the
12 * GNU GPL, version 2 or (at your option) any later version.
13 */
14
15 #include "qemu/osdep.h"
16 #include "hw/ssi/ssi.h"
17 #include "migration/vmstate.h"
18 #include "qemu/module.h"
19 #include "qapi/error.h"
20 #include "qom/object.h"
21
22 struct SSIBus {
23 BusState parent_obj;
24 };
25
26 #define TYPE_SSI_BUS "SSI"
27 OBJECT_DECLARE_SIMPLE_TYPE(SSIBus, SSI_BUS)
28
29 static const TypeInfo ssi_bus_info = {
30 .name = TYPE_SSI_BUS,
31 .parent = TYPE_BUS,
32 .instance_size = sizeof(SSIBus),
33 };
34
35 static void ssi_cs_default(void *opaque, int n, int level)
36 {
37 SSISlave *s = SSI_SLAVE(opaque);
38 bool cs = !!level;
39 assert(n == 0);
40 if (s->cs != cs) {
41 SSISlaveClass *ssc = SSI_SLAVE_GET_CLASS(s);
42 if (ssc->set_cs) {
43 ssc->set_cs(s, cs);
44 }
45 }
46 s->cs = cs;
47 }
48
49 static uint32_t ssi_transfer_raw_default(SSISlave *dev, uint32_t val)
50 {
51 SSISlaveClass *ssc = SSI_SLAVE_GET_CLASS(dev);
52
53 if ((dev->cs && ssc->cs_polarity == SSI_CS_HIGH) ||
54 (!dev->cs && ssc->cs_polarity == SSI_CS_LOW) ||
55 ssc->cs_polarity == SSI_CS_NONE) {
56 return ssc->transfer(dev, val);
57 }
58 return 0;
59 }
60
61 static void ssi_slave_realize(DeviceState *dev, Error **errp)
62 {
63 SSISlave *s = SSI_SLAVE(dev);
64 SSISlaveClass *ssc = SSI_SLAVE_GET_CLASS(s);
65
66 if (ssc->transfer_raw == ssi_transfer_raw_default &&
67 ssc->cs_polarity != SSI_CS_NONE) {
68 qdev_init_gpio_in_named(dev, ssi_cs_default, SSI_GPIO_CS, 1);
69 }
70
71 ssc->realize(s, errp);
72 }
73
74 static void ssi_slave_class_init(ObjectClass *klass, void *data)
75 {
76 SSISlaveClass *ssc = SSI_SLAVE_CLASS(klass);
77 DeviceClass *dc = DEVICE_CLASS(klass);
78
79 dc->realize = ssi_slave_realize;
80 dc->bus_type = TYPE_SSI_BUS;
81 if (!ssc->transfer_raw) {
82 ssc->transfer_raw = ssi_transfer_raw_default;
83 }
84 }
85
86 static const TypeInfo ssi_slave_info = {
87 .name = TYPE_SSI_SLAVE,
88 .parent = TYPE_DEVICE,
89 .class_init = ssi_slave_class_init,
90 .class_size = sizeof(SSISlaveClass),
91 .abstract = true,
92 };
93
94 bool ssi_realize_and_unref(DeviceState *dev, SSIBus *bus, Error **errp)
95 {
96 return qdev_realize_and_unref(dev, &bus->parent_obj, errp);
97 }
98
99 DeviceState *ssi_create_slave(SSIBus *bus, const char *name)
100 {
101 DeviceState *dev = qdev_new(name);
102
103 ssi_realize_and_unref(dev, bus, &error_fatal);
104 return dev;
105 }
106
107 SSIBus *ssi_create_bus(DeviceState *parent, const char *name)
108 {
109 BusState *bus;
110 bus = qbus_create(TYPE_SSI_BUS, parent, name);
111 return SSI_BUS(bus);
112 }
113
114 uint32_t ssi_transfer(SSIBus *bus, uint32_t val)
115 {
116 BusState *b = BUS(bus);
117 BusChild *kid;
118 SSISlaveClass *ssc;
119 uint32_t r = 0;
120
121 QTAILQ_FOREACH(kid, &b->children, sibling) {
122 SSISlave *slave = SSI_SLAVE(kid->child);
123 ssc = SSI_SLAVE_GET_CLASS(slave);
124 r |= ssc->transfer_raw(slave, val);
125 }
126
127 return r;
128 }
129
130 const VMStateDescription vmstate_ssi_slave = {
131 .name = "SSISlave",
132 .version_id = 1,
133 .minimum_version_id = 1,
134 .fields = (VMStateField[]) {
135 VMSTATE_BOOL(cs, SSISlave),
136 VMSTATE_END_OF_LIST()
137 }
138 };
139
140 static void ssi_slave_register_types(void)
141 {
142 type_register_static(&ssi_bus_info);
143 type_register_static(&ssi_slave_info);
144 }
145
146 type_init(ssi_slave_register_types)