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[qemu.git] / hw / strongarm.c
1 /*
2 * StrongARM SA-1100/SA-1110 emulation
3 *
4 * Copyright (C) 2011 Dmitry Eremin-Solenikov
5 *
6 * Largely based on StrongARM emulation:
7 * Copyright (c) 2006 Openedhand Ltd.
8 * Written by Andrzej Zaborowski <balrog@zabor.org>
9 *
10 * UART code based on QEMU 16550A UART emulation
11 * Copyright (c) 2003-2004 Fabrice Bellard
12 * Copyright (c) 2008 Citrix Systems, Inc.
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, see <http://www.gnu.org/licenses/>.
25 *
26 * Contributions after 2012-01-13 are licensed under the terms of the
27 * GNU GPL, version 2 or (at your option) any later version.
28 */
29 #include "sysbus.h"
30 #include "strongarm.h"
31 #include "qemu-error.h"
32 #include "arm-misc.h"
33 #include "sysemu.h"
34 #include "ssi.h"
35
36 //#define DEBUG
37
38 /*
39 TODO
40 - Implement cp15, c14 ?
41 - Implement cp15, c15 !!! (idle used in L)
42 - Implement idle mode handling/DIM
43 - Implement sleep mode/Wake sources
44 - Implement reset control
45 - Implement memory control regs
46 - PCMCIA handling
47 - Maybe support MBGNT/MBREQ
48 - DMA channels
49 - GPCLK
50 - IrDA
51 - MCP
52 - Enhance UART with modem signals
53 */
54
55 #ifdef DEBUG
56 # define DPRINTF(format, ...) printf(format , ## __VA_ARGS__)
57 #else
58 # define DPRINTF(format, ...) do { } while (0)
59 #endif
60
61 static struct {
62 target_phys_addr_t io_base;
63 int irq;
64 } sa_serial[] = {
65 { 0x80010000, SA_PIC_UART1 },
66 { 0x80030000, SA_PIC_UART2 },
67 { 0x80050000, SA_PIC_UART3 },
68 { 0, 0 }
69 };
70
71 /* Interrupt Controller */
72 typedef struct {
73 SysBusDevice busdev;
74 MemoryRegion iomem;
75 qemu_irq irq;
76 qemu_irq fiq;
77
78 uint32_t pending;
79 uint32_t enabled;
80 uint32_t is_fiq;
81 uint32_t int_idle;
82 } StrongARMPICState;
83
84 #define ICIP 0x00
85 #define ICMR 0x04
86 #define ICLR 0x08
87 #define ICFP 0x10
88 #define ICPR 0x20
89 #define ICCR 0x0c
90
91 #define SA_PIC_SRCS 32
92
93
94 static void strongarm_pic_update(void *opaque)
95 {
96 StrongARMPICState *s = opaque;
97
98 /* FIXME: reflect DIM */
99 qemu_set_irq(s->fiq, s->pending & s->enabled & s->is_fiq);
100 qemu_set_irq(s->irq, s->pending & s->enabled & ~s->is_fiq);
101 }
102
103 static void strongarm_pic_set_irq(void *opaque, int irq, int level)
104 {
105 StrongARMPICState *s = opaque;
106
107 if (level) {
108 s->pending |= 1 << irq;
109 } else {
110 s->pending &= ~(1 << irq);
111 }
112
113 strongarm_pic_update(s);
114 }
115
116 static uint64_t strongarm_pic_mem_read(void *opaque, target_phys_addr_t offset,
117 unsigned size)
118 {
119 StrongARMPICState *s = opaque;
120
121 switch (offset) {
122 case ICIP:
123 return s->pending & ~s->is_fiq & s->enabled;
124 case ICMR:
125 return s->enabled;
126 case ICLR:
127 return s->is_fiq;
128 case ICCR:
129 return s->int_idle == 0;
130 case ICFP:
131 return s->pending & s->is_fiq & s->enabled;
132 case ICPR:
133 return s->pending;
134 default:
135 printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n",
136 __func__, offset);
137 return 0;
138 }
139 }
140
141 static void strongarm_pic_mem_write(void *opaque, target_phys_addr_t offset,
142 uint64_t value, unsigned size)
143 {
144 StrongARMPICState *s = opaque;
145
146 switch (offset) {
147 case ICMR:
148 s->enabled = value;
149 break;
150 case ICLR:
151 s->is_fiq = value;
152 break;
153 case ICCR:
154 s->int_idle = (value & 1) ? 0 : ~0;
155 break;
156 default:
157 printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n",
158 __func__, offset);
159 break;
160 }
161 strongarm_pic_update(s);
162 }
163
164 static const MemoryRegionOps strongarm_pic_ops = {
165 .read = strongarm_pic_mem_read,
166 .write = strongarm_pic_mem_write,
167 .endianness = DEVICE_NATIVE_ENDIAN,
168 };
169
170 static int strongarm_pic_initfn(SysBusDevice *dev)
171 {
172 StrongARMPICState *s = FROM_SYSBUS(StrongARMPICState, dev);
173
174 qdev_init_gpio_in(&dev->qdev, strongarm_pic_set_irq, SA_PIC_SRCS);
175 memory_region_init_io(&s->iomem, &strongarm_pic_ops, s, "pic", 0x1000);
176 sysbus_init_mmio(dev, &s->iomem);
177 sysbus_init_irq(dev, &s->irq);
178 sysbus_init_irq(dev, &s->fiq);
179
180 return 0;
181 }
182
183 static int strongarm_pic_post_load(void *opaque, int version_id)
184 {
185 strongarm_pic_update(opaque);
186 return 0;
187 }
188
189 static VMStateDescription vmstate_strongarm_pic_regs = {
190 .name = "strongarm_pic",
191 .version_id = 0,
192 .minimum_version_id = 0,
193 .minimum_version_id_old = 0,
194 .post_load = strongarm_pic_post_load,
195 .fields = (VMStateField[]) {
196 VMSTATE_UINT32(pending, StrongARMPICState),
197 VMSTATE_UINT32(enabled, StrongARMPICState),
198 VMSTATE_UINT32(is_fiq, StrongARMPICState),
199 VMSTATE_UINT32(int_idle, StrongARMPICState),
200 VMSTATE_END_OF_LIST(),
201 },
202 };
203
204 static SysBusDeviceInfo strongarm_pic_info = {
205 .init = strongarm_pic_initfn,
206 .qdev.name = "strongarm_pic",
207 .qdev.desc = "StrongARM PIC",
208 .qdev.size = sizeof(StrongARMPICState),
209 .qdev.vmsd = &vmstate_strongarm_pic_regs,
210 };
211
212 /* Real-Time Clock */
213 #define RTAR 0x00 /* RTC Alarm register */
214 #define RCNR 0x04 /* RTC Counter register */
215 #define RTTR 0x08 /* RTC Timer Trim register */
216 #define RTSR 0x10 /* RTC Status register */
217
218 #define RTSR_AL (1 << 0) /* RTC Alarm detected */
219 #define RTSR_HZ (1 << 1) /* RTC 1Hz detected */
220 #define RTSR_ALE (1 << 2) /* RTC Alarm enable */
221 #define RTSR_HZE (1 << 3) /* RTC 1Hz enable */
222
223 /* 16 LSB of RTTR are clockdiv for internal trim logic,
224 * trim delete isn't emulated, so
225 * f = 32 768 / (RTTR_trim + 1) */
226
227 typedef struct {
228 SysBusDevice busdev;
229 MemoryRegion iomem;
230 uint32_t rttr;
231 uint32_t rtsr;
232 uint32_t rtar;
233 uint32_t last_rcnr;
234 int64_t last_hz;
235 QEMUTimer *rtc_alarm;
236 QEMUTimer *rtc_hz;
237 qemu_irq rtc_irq;
238 qemu_irq rtc_hz_irq;
239 } StrongARMRTCState;
240
241 static inline void strongarm_rtc_int_update(StrongARMRTCState *s)
242 {
243 qemu_set_irq(s->rtc_irq, s->rtsr & RTSR_AL);
244 qemu_set_irq(s->rtc_hz_irq, s->rtsr & RTSR_HZ);
245 }
246
247 static void strongarm_rtc_hzupdate(StrongARMRTCState *s)
248 {
249 int64_t rt = qemu_get_clock_ms(rt_clock);
250 s->last_rcnr += ((rt - s->last_hz) << 15) /
251 (1000 * ((s->rttr & 0xffff) + 1));
252 s->last_hz = rt;
253 }
254
255 static inline void strongarm_rtc_timer_update(StrongARMRTCState *s)
256 {
257 if ((s->rtsr & RTSR_HZE) && !(s->rtsr & RTSR_HZ)) {
258 qemu_mod_timer(s->rtc_hz, s->last_hz + 1000);
259 } else {
260 qemu_del_timer(s->rtc_hz);
261 }
262
263 if ((s->rtsr & RTSR_ALE) && !(s->rtsr & RTSR_AL)) {
264 qemu_mod_timer(s->rtc_alarm, s->last_hz +
265 (((s->rtar - s->last_rcnr) * 1000 *
266 ((s->rttr & 0xffff) + 1)) >> 15));
267 } else {
268 qemu_del_timer(s->rtc_alarm);
269 }
270 }
271
272 static inline void strongarm_rtc_alarm_tick(void *opaque)
273 {
274 StrongARMRTCState *s = opaque;
275 s->rtsr |= RTSR_AL;
276 strongarm_rtc_timer_update(s);
277 strongarm_rtc_int_update(s);
278 }
279
280 static inline void strongarm_rtc_hz_tick(void *opaque)
281 {
282 StrongARMRTCState *s = opaque;
283 s->rtsr |= RTSR_HZ;
284 strongarm_rtc_timer_update(s);
285 strongarm_rtc_int_update(s);
286 }
287
288 static uint64_t strongarm_rtc_read(void *opaque, target_phys_addr_t addr,
289 unsigned size)
290 {
291 StrongARMRTCState *s = opaque;
292
293 switch (addr) {
294 case RTTR:
295 return s->rttr;
296 case RTSR:
297 return s->rtsr;
298 case RTAR:
299 return s->rtar;
300 case RCNR:
301 return s->last_rcnr +
302 ((qemu_get_clock_ms(rt_clock) - s->last_hz) << 15) /
303 (1000 * ((s->rttr & 0xffff) + 1));
304 default:
305 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
306 return 0;
307 }
308 }
309
310 static void strongarm_rtc_write(void *opaque, target_phys_addr_t addr,
311 uint64_t value, unsigned size)
312 {
313 StrongARMRTCState *s = opaque;
314 uint32_t old_rtsr;
315
316 switch (addr) {
317 case RTTR:
318 strongarm_rtc_hzupdate(s);
319 s->rttr = value;
320 strongarm_rtc_timer_update(s);
321 break;
322
323 case RTSR:
324 old_rtsr = s->rtsr;
325 s->rtsr = (value & (RTSR_ALE | RTSR_HZE)) |
326 (s->rtsr & ~(value & (RTSR_AL | RTSR_HZ)));
327
328 if (s->rtsr != old_rtsr) {
329 strongarm_rtc_timer_update(s);
330 }
331
332 strongarm_rtc_int_update(s);
333 break;
334
335 case RTAR:
336 s->rtar = value;
337 strongarm_rtc_timer_update(s);
338 break;
339
340 case RCNR:
341 strongarm_rtc_hzupdate(s);
342 s->last_rcnr = value;
343 strongarm_rtc_timer_update(s);
344 break;
345
346 default:
347 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
348 }
349 }
350
351 static const MemoryRegionOps strongarm_rtc_ops = {
352 .read = strongarm_rtc_read,
353 .write = strongarm_rtc_write,
354 .endianness = DEVICE_NATIVE_ENDIAN,
355 };
356
357 static int strongarm_rtc_init(SysBusDevice *dev)
358 {
359 StrongARMRTCState *s = FROM_SYSBUS(StrongARMRTCState, dev);
360 struct tm tm;
361
362 s->rttr = 0x0;
363 s->rtsr = 0;
364
365 qemu_get_timedate(&tm, 0);
366
367 s->last_rcnr = (uint32_t) mktimegm(&tm);
368 s->last_hz = qemu_get_clock_ms(rt_clock);
369
370 s->rtc_alarm = qemu_new_timer_ms(rt_clock, strongarm_rtc_alarm_tick, s);
371 s->rtc_hz = qemu_new_timer_ms(rt_clock, strongarm_rtc_hz_tick, s);
372
373 sysbus_init_irq(dev, &s->rtc_irq);
374 sysbus_init_irq(dev, &s->rtc_hz_irq);
375
376 memory_region_init_io(&s->iomem, &strongarm_rtc_ops, s, "rtc", 0x10000);
377 sysbus_init_mmio(dev, &s->iomem);
378
379 return 0;
380 }
381
382 static void strongarm_rtc_pre_save(void *opaque)
383 {
384 StrongARMRTCState *s = opaque;
385
386 strongarm_rtc_hzupdate(s);
387 }
388
389 static int strongarm_rtc_post_load(void *opaque, int version_id)
390 {
391 StrongARMRTCState *s = opaque;
392
393 strongarm_rtc_timer_update(s);
394 strongarm_rtc_int_update(s);
395
396 return 0;
397 }
398
399 static const VMStateDescription vmstate_strongarm_rtc_regs = {
400 .name = "strongarm-rtc",
401 .version_id = 0,
402 .minimum_version_id = 0,
403 .minimum_version_id_old = 0,
404 .pre_save = strongarm_rtc_pre_save,
405 .post_load = strongarm_rtc_post_load,
406 .fields = (VMStateField[]) {
407 VMSTATE_UINT32(rttr, StrongARMRTCState),
408 VMSTATE_UINT32(rtsr, StrongARMRTCState),
409 VMSTATE_UINT32(rtar, StrongARMRTCState),
410 VMSTATE_UINT32(last_rcnr, StrongARMRTCState),
411 VMSTATE_INT64(last_hz, StrongARMRTCState),
412 VMSTATE_END_OF_LIST(),
413 },
414 };
415
416 static SysBusDeviceInfo strongarm_rtc_sysbus_info = {
417 .init = strongarm_rtc_init,
418 .qdev.name = "strongarm-rtc",
419 .qdev.desc = "StrongARM RTC Controller",
420 .qdev.size = sizeof(StrongARMRTCState),
421 .qdev.vmsd = &vmstate_strongarm_rtc_regs,
422 };
423
424 /* GPIO */
425 #define GPLR 0x00
426 #define GPDR 0x04
427 #define GPSR 0x08
428 #define GPCR 0x0c
429 #define GRER 0x10
430 #define GFER 0x14
431 #define GEDR 0x18
432 #define GAFR 0x1c
433
434 typedef struct StrongARMGPIOInfo StrongARMGPIOInfo;
435 struct StrongARMGPIOInfo {
436 SysBusDevice busdev;
437 MemoryRegion iomem;
438 qemu_irq handler[28];
439 qemu_irq irqs[11];
440 qemu_irq irqX;
441
442 uint32_t ilevel;
443 uint32_t olevel;
444 uint32_t dir;
445 uint32_t rising;
446 uint32_t falling;
447 uint32_t status;
448 uint32_t gpsr;
449 uint32_t gafr;
450
451 uint32_t prev_level;
452 };
453
454
455 static void strongarm_gpio_irq_update(StrongARMGPIOInfo *s)
456 {
457 int i;
458 for (i = 0; i < 11; i++) {
459 qemu_set_irq(s->irqs[i], s->status & (1 << i));
460 }
461
462 qemu_set_irq(s->irqX, (s->status & ~0x7ff));
463 }
464
465 static void strongarm_gpio_set(void *opaque, int line, int level)
466 {
467 StrongARMGPIOInfo *s = opaque;
468 uint32_t mask;
469
470 mask = 1 << line;
471
472 if (level) {
473 s->status |= s->rising & mask &
474 ~s->ilevel & ~s->dir;
475 s->ilevel |= mask;
476 } else {
477 s->status |= s->falling & mask &
478 s->ilevel & ~s->dir;
479 s->ilevel &= ~mask;
480 }
481
482 if (s->status & mask) {
483 strongarm_gpio_irq_update(s);
484 }
485 }
486
487 static void strongarm_gpio_handler_update(StrongARMGPIOInfo *s)
488 {
489 uint32_t level, diff;
490 int bit;
491
492 level = s->olevel & s->dir;
493
494 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
495 bit = ffs(diff) - 1;
496 qemu_set_irq(s->handler[bit], (level >> bit) & 1);
497 }
498
499 s->prev_level = level;
500 }
501
502 static uint64_t strongarm_gpio_read(void *opaque, target_phys_addr_t offset,
503 unsigned size)
504 {
505 StrongARMGPIOInfo *s = opaque;
506
507 switch (offset) {
508 case GPDR: /* GPIO Pin-Direction registers */
509 return s->dir;
510
511 case GPSR: /* GPIO Pin-Output Set registers */
512 DPRINTF("%s: Read from a write-only register 0x" TARGET_FMT_plx "\n",
513 __func__, offset);
514 return s->gpsr; /* Return last written value. */
515
516 case GPCR: /* GPIO Pin-Output Clear registers */
517 DPRINTF("%s: Read from a write-only register 0x" TARGET_FMT_plx "\n",
518 __func__, offset);
519 return 31337; /* Specified as unpredictable in the docs. */
520
521 case GRER: /* GPIO Rising-Edge Detect Enable registers */
522 return s->rising;
523
524 case GFER: /* GPIO Falling-Edge Detect Enable registers */
525 return s->falling;
526
527 case GAFR: /* GPIO Alternate Function registers */
528 return s->gafr;
529
530 case GPLR: /* GPIO Pin-Level registers */
531 return (s->olevel & s->dir) |
532 (s->ilevel & ~s->dir);
533
534 case GEDR: /* GPIO Edge Detect Status registers */
535 return s->status;
536
537 default:
538 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
539 }
540
541 return 0;
542 }
543
544 static void strongarm_gpio_write(void *opaque, target_phys_addr_t offset,
545 uint64_t value, unsigned size)
546 {
547 StrongARMGPIOInfo *s = opaque;
548
549 switch (offset) {
550 case GPDR: /* GPIO Pin-Direction registers */
551 s->dir = value;
552 strongarm_gpio_handler_update(s);
553 break;
554
555 case GPSR: /* GPIO Pin-Output Set registers */
556 s->olevel |= value;
557 strongarm_gpio_handler_update(s);
558 s->gpsr = value;
559 break;
560
561 case GPCR: /* GPIO Pin-Output Clear registers */
562 s->olevel &= ~value;
563 strongarm_gpio_handler_update(s);
564 break;
565
566 case GRER: /* GPIO Rising-Edge Detect Enable registers */
567 s->rising = value;
568 break;
569
570 case GFER: /* GPIO Falling-Edge Detect Enable registers */
571 s->falling = value;
572 break;
573
574 case GAFR: /* GPIO Alternate Function registers */
575 s->gafr = value;
576 break;
577
578 case GEDR: /* GPIO Edge Detect Status registers */
579 s->status &= ~value;
580 strongarm_gpio_irq_update(s);
581 break;
582
583 default:
584 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
585 }
586 }
587
588 static const MemoryRegionOps strongarm_gpio_ops = {
589 .read = strongarm_gpio_read,
590 .write = strongarm_gpio_write,
591 .endianness = DEVICE_NATIVE_ENDIAN,
592 };
593
594 static DeviceState *strongarm_gpio_init(target_phys_addr_t base,
595 DeviceState *pic)
596 {
597 DeviceState *dev;
598 int i;
599
600 dev = qdev_create(NULL, "strongarm-gpio");
601 qdev_init_nofail(dev);
602
603 sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
604 for (i = 0; i < 12; i++)
605 sysbus_connect_irq(sysbus_from_qdev(dev), i,
606 qdev_get_gpio_in(pic, SA_PIC_GPIO0_EDGE + i));
607
608 return dev;
609 }
610
611 static int strongarm_gpio_initfn(SysBusDevice *dev)
612 {
613 StrongARMGPIOInfo *s;
614 int i;
615
616 s = FROM_SYSBUS(StrongARMGPIOInfo, dev);
617
618 qdev_init_gpio_in(&dev->qdev, strongarm_gpio_set, 28);
619 qdev_init_gpio_out(&dev->qdev, s->handler, 28);
620
621 memory_region_init_io(&s->iomem, &strongarm_gpio_ops, s, "gpio", 0x1000);
622
623 sysbus_init_mmio(dev, &s->iomem);
624 for (i = 0; i < 11; i++) {
625 sysbus_init_irq(dev, &s->irqs[i]);
626 }
627 sysbus_init_irq(dev, &s->irqX);
628
629 return 0;
630 }
631
632 static const VMStateDescription vmstate_strongarm_gpio_regs = {
633 .name = "strongarm-gpio",
634 .version_id = 0,
635 .minimum_version_id = 0,
636 .minimum_version_id_old = 0,
637 .fields = (VMStateField[]) {
638 VMSTATE_UINT32(ilevel, StrongARMGPIOInfo),
639 VMSTATE_UINT32(olevel, StrongARMGPIOInfo),
640 VMSTATE_UINT32(dir, StrongARMGPIOInfo),
641 VMSTATE_UINT32(rising, StrongARMGPIOInfo),
642 VMSTATE_UINT32(falling, StrongARMGPIOInfo),
643 VMSTATE_UINT32(status, StrongARMGPIOInfo),
644 VMSTATE_UINT32(gafr, StrongARMGPIOInfo),
645 VMSTATE_END_OF_LIST(),
646 },
647 };
648
649 static SysBusDeviceInfo strongarm_gpio_info = {
650 .init = strongarm_gpio_initfn,
651 .qdev.name = "strongarm-gpio",
652 .qdev.desc = "StrongARM GPIO controller",
653 .qdev.size = sizeof(StrongARMGPIOInfo),
654 };
655
656 /* Peripheral Pin Controller */
657 #define PPDR 0x00
658 #define PPSR 0x04
659 #define PPAR 0x08
660 #define PSDR 0x0c
661 #define PPFR 0x10
662
663 typedef struct StrongARMPPCInfo StrongARMPPCInfo;
664 struct StrongARMPPCInfo {
665 SysBusDevice busdev;
666 MemoryRegion iomem;
667 qemu_irq handler[28];
668
669 uint32_t ilevel;
670 uint32_t olevel;
671 uint32_t dir;
672 uint32_t ppar;
673 uint32_t psdr;
674 uint32_t ppfr;
675
676 uint32_t prev_level;
677 };
678
679 static void strongarm_ppc_set(void *opaque, int line, int level)
680 {
681 StrongARMPPCInfo *s = opaque;
682
683 if (level) {
684 s->ilevel |= 1 << line;
685 } else {
686 s->ilevel &= ~(1 << line);
687 }
688 }
689
690 static void strongarm_ppc_handler_update(StrongARMPPCInfo *s)
691 {
692 uint32_t level, diff;
693 int bit;
694
695 level = s->olevel & s->dir;
696
697 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
698 bit = ffs(diff) - 1;
699 qemu_set_irq(s->handler[bit], (level >> bit) & 1);
700 }
701
702 s->prev_level = level;
703 }
704
705 static uint64_t strongarm_ppc_read(void *opaque, target_phys_addr_t offset,
706 unsigned size)
707 {
708 StrongARMPPCInfo *s = opaque;
709
710 switch (offset) {
711 case PPDR: /* PPC Pin Direction registers */
712 return s->dir | ~0x3fffff;
713
714 case PPSR: /* PPC Pin State registers */
715 return (s->olevel & s->dir) |
716 (s->ilevel & ~s->dir) |
717 ~0x3fffff;
718
719 case PPAR:
720 return s->ppar | ~0x41000;
721
722 case PSDR:
723 return s->psdr;
724
725 case PPFR:
726 return s->ppfr | ~0x7f001;
727
728 default:
729 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
730 }
731
732 return 0;
733 }
734
735 static void strongarm_ppc_write(void *opaque, target_phys_addr_t offset,
736 uint64_t value, unsigned size)
737 {
738 StrongARMPPCInfo *s = opaque;
739
740 switch (offset) {
741 case PPDR: /* PPC Pin Direction registers */
742 s->dir = value & 0x3fffff;
743 strongarm_ppc_handler_update(s);
744 break;
745
746 case PPSR: /* PPC Pin State registers */
747 s->olevel = value & s->dir & 0x3fffff;
748 strongarm_ppc_handler_update(s);
749 break;
750
751 case PPAR:
752 s->ppar = value & 0x41000;
753 break;
754
755 case PSDR:
756 s->psdr = value & 0x3fffff;
757 break;
758
759 case PPFR:
760 s->ppfr = value & 0x7f001;
761 break;
762
763 default:
764 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
765 }
766 }
767
768 static const MemoryRegionOps strongarm_ppc_ops = {
769 .read = strongarm_ppc_read,
770 .write = strongarm_ppc_write,
771 .endianness = DEVICE_NATIVE_ENDIAN,
772 };
773
774 static int strongarm_ppc_init(SysBusDevice *dev)
775 {
776 StrongARMPPCInfo *s;
777
778 s = FROM_SYSBUS(StrongARMPPCInfo, dev);
779
780 qdev_init_gpio_in(&dev->qdev, strongarm_ppc_set, 22);
781 qdev_init_gpio_out(&dev->qdev, s->handler, 22);
782
783 memory_region_init_io(&s->iomem, &strongarm_ppc_ops, s, "ppc", 0x1000);
784
785 sysbus_init_mmio(dev, &s->iomem);
786
787 return 0;
788 }
789
790 static const VMStateDescription vmstate_strongarm_ppc_regs = {
791 .name = "strongarm-ppc",
792 .version_id = 0,
793 .minimum_version_id = 0,
794 .minimum_version_id_old = 0,
795 .fields = (VMStateField[]) {
796 VMSTATE_UINT32(ilevel, StrongARMPPCInfo),
797 VMSTATE_UINT32(olevel, StrongARMPPCInfo),
798 VMSTATE_UINT32(dir, StrongARMPPCInfo),
799 VMSTATE_UINT32(ppar, StrongARMPPCInfo),
800 VMSTATE_UINT32(psdr, StrongARMPPCInfo),
801 VMSTATE_UINT32(ppfr, StrongARMPPCInfo),
802 VMSTATE_END_OF_LIST(),
803 },
804 };
805
806 static SysBusDeviceInfo strongarm_ppc_info = {
807 .init = strongarm_ppc_init,
808 .qdev.name = "strongarm-ppc",
809 .qdev.desc = "StrongARM PPC controller",
810 .qdev.size = sizeof(StrongARMPPCInfo),
811 };
812
813 /* UART Ports */
814 #define UTCR0 0x00
815 #define UTCR1 0x04
816 #define UTCR2 0x08
817 #define UTCR3 0x0c
818 #define UTDR 0x14
819 #define UTSR0 0x1c
820 #define UTSR1 0x20
821
822 #define UTCR0_PE (1 << 0) /* Parity enable */
823 #define UTCR0_OES (1 << 1) /* Even parity */
824 #define UTCR0_SBS (1 << 2) /* 2 stop bits */
825 #define UTCR0_DSS (1 << 3) /* 8-bit data */
826
827 #define UTCR3_RXE (1 << 0) /* Rx enable */
828 #define UTCR3_TXE (1 << 1) /* Tx enable */
829 #define UTCR3_BRK (1 << 2) /* Force Break */
830 #define UTCR3_RIE (1 << 3) /* Rx int enable */
831 #define UTCR3_TIE (1 << 4) /* Tx int enable */
832 #define UTCR3_LBM (1 << 5) /* Loopback */
833
834 #define UTSR0_TFS (1 << 0) /* Tx FIFO nearly empty */
835 #define UTSR0_RFS (1 << 1) /* Rx FIFO nearly full */
836 #define UTSR0_RID (1 << 2) /* Receiver Idle */
837 #define UTSR0_RBB (1 << 3) /* Receiver begin break */
838 #define UTSR0_REB (1 << 4) /* Receiver end break */
839 #define UTSR0_EIF (1 << 5) /* Error in FIFO */
840
841 #define UTSR1_RNE (1 << 1) /* Receive FIFO not empty */
842 #define UTSR1_TNF (1 << 2) /* Transmit FIFO not full */
843 #define UTSR1_PRE (1 << 3) /* Parity error */
844 #define UTSR1_FRE (1 << 4) /* Frame error */
845 #define UTSR1_ROR (1 << 5) /* Receive Over Run */
846
847 #define RX_FIFO_PRE (1 << 8)
848 #define RX_FIFO_FRE (1 << 9)
849 #define RX_FIFO_ROR (1 << 10)
850
851 typedef struct {
852 SysBusDevice busdev;
853 MemoryRegion iomem;
854 CharDriverState *chr;
855 qemu_irq irq;
856
857 uint8_t utcr0;
858 uint16_t brd;
859 uint8_t utcr3;
860 uint8_t utsr0;
861 uint8_t utsr1;
862
863 uint8_t tx_fifo[8];
864 uint8_t tx_start;
865 uint8_t tx_len;
866 uint16_t rx_fifo[12]; /* value + error flags in high bits */
867 uint8_t rx_start;
868 uint8_t rx_len;
869
870 uint64_t char_transmit_time; /* time to transmit a char in ticks*/
871 bool wait_break_end;
872 QEMUTimer *rx_timeout_timer;
873 QEMUTimer *tx_timer;
874 } StrongARMUARTState;
875
876 static void strongarm_uart_update_status(StrongARMUARTState *s)
877 {
878 uint16_t utsr1 = 0;
879
880 if (s->tx_len != 8) {
881 utsr1 |= UTSR1_TNF;
882 }
883
884 if (s->rx_len != 0) {
885 uint16_t ent = s->rx_fifo[s->rx_start];
886
887 utsr1 |= UTSR1_RNE;
888 if (ent & RX_FIFO_PRE) {
889 s->utsr1 |= UTSR1_PRE;
890 }
891 if (ent & RX_FIFO_FRE) {
892 s->utsr1 |= UTSR1_FRE;
893 }
894 if (ent & RX_FIFO_ROR) {
895 s->utsr1 |= UTSR1_ROR;
896 }
897 }
898
899 s->utsr1 = utsr1;
900 }
901
902 static void strongarm_uart_update_int_status(StrongARMUARTState *s)
903 {
904 uint16_t utsr0 = s->utsr0 &
905 (UTSR0_REB | UTSR0_RBB | UTSR0_RID);
906 int i;
907
908 if ((s->utcr3 & UTCR3_TXE) &&
909 (s->utcr3 & UTCR3_TIE) &&
910 s->tx_len <= 4) {
911 utsr0 |= UTSR0_TFS;
912 }
913
914 if ((s->utcr3 & UTCR3_RXE) &&
915 (s->utcr3 & UTCR3_RIE) &&
916 s->rx_len > 4) {
917 utsr0 |= UTSR0_RFS;
918 }
919
920 for (i = 0; i < s->rx_len && i < 4; i++)
921 if (s->rx_fifo[(s->rx_start + i) % 12] & ~0xff) {
922 utsr0 |= UTSR0_EIF;
923 break;
924 }
925
926 s->utsr0 = utsr0;
927 qemu_set_irq(s->irq, utsr0);
928 }
929
930 static void strongarm_uart_update_parameters(StrongARMUARTState *s)
931 {
932 int speed, parity, data_bits, stop_bits, frame_size;
933 QEMUSerialSetParams ssp;
934
935 /* Start bit. */
936 frame_size = 1;
937 if (s->utcr0 & UTCR0_PE) {
938 /* Parity bit. */
939 frame_size++;
940 if (s->utcr0 & UTCR0_OES) {
941 parity = 'E';
942 } else {
943 parity = 'O';
944 }
945 } else {
946 parity = 'N';
947 }
948 if (s->utcr0 & UTCR0_SBS) {
949 stop_bits = 2;
950 } else {
951 stop_bits = 1;
952 }
953
954 data_bits = (s->utcr0 & UTCR0_DSS) ? 8 : 7;
955 frame_size += data_bits + stop_bits;
956 speed = 3686400 / 16 / (s->brd + 1);
957 ssp.speed = speed;
958 ssp.parity = parity;
959 ssp.data_bits = data_bits;
960 ssp.stop_bits = stop_bits;
961 s->char_transmit_time = (get_ticks_per_sec() / speed) * frame_size;
962 if (s->chr) {
963 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
964 }
965
966 DPRINTF(stderr, "%s speed=%d parity=%c data=%d stop=%d\n", s->chr->label,
967 speed, parity, data_bits, stop_bits);
968 }
969
970 static void strongarm_uart_rx_to(void *opaque)
971 {
972 StrongARMUARTState *s = opaque;
973
974 if (s->rx_len) {
975 s->utsr0 |= UTSR0_RID;
976 strongarm_uart_update_int_status(s);
977 }
978 }
979
980 static void strongarm_uart_rx_push(StrongARMUARTState *s, uint16_t c)
981 {
982 if ((s->utcr3 & UTCR3_RXE) == 0) {
983 /* rx disabled */
984 return;
985 }
986
987 if (s->wait_break_end) {
988 s->utsr0 |= UTSR0_REB;
989 s->wait_break_end = false;
990 }
991
992 if (s->rx_len < 12) {
993 s->rx_fifo[(s->rx_start + s->rx_len) % 12] = c;
994 s->rx_len++;
995 } else
996 s->rx_fifo[(s->rx_start + 11) % 12] |= RX_FIFO_ROR;
997 }
998
999 static int strongarm_uart_can_receive(void *opaque)
1000 {
1001 StrongARMUARTState *s = opaque;
1002
1003 if (s->rx_len == 12) {
1004 return 0;
1005 }
1006 /* It's best not to get more than 2/3 of RX FIFO, so advertise that much */
1007 if (s->rx_len < 8) {
1008 return 8 - s->rx_len;
1009 }
1010 return 1;
1011 }
1012
1013 static void strongarm_uart_receive(void *opaque, const uint8_t *buf, int size)
1014 {
1015 StrongARMUARTState *s = opaque;
1016 int i;
1017
1018 for (i = 0; i < size; i++) {
1019 strongarm_uart_rx_push(s, buf[i]);
1020 }
1021
1022 /* call the timeout receive callback in 3 char transmit time */
1023 qemu_mod_timer(s->rx_timeout_timer,
1024 qemu_get_clock_ns(vm_clock) + s->char_transmit_time * 3);
1025
1026 strongarm_uart_update_status(s);
1027 strongarm_uart_update_int_status(s);
1028 }
1029
1030 static void strongarm_uart_event(void *opaque, int event)
1031 {
1032 StrongARMUARTState *s = opaque;
1033 if (event == CHR_EVENT_BREAK) {
1034 s->utsr0 |= UTSR0_RBB;
1035 strongarm_uart_rx_push(s, RX_FIFO_FRE);
1036 s->wait_break_end = true;
1037 strongarm_uart_update_status(s);
1038 strongarm_uart_update_int_status(s);
1039 }
1040 }
1041
1042 static void strongarm_uart_tx(void *opaque)
1043 {
1044 StrongARMUARTState *s = opaque;
1045 uint64_t new_xmit_ts = qemu_get_clock_ns(vm_clock);
1046
1047 if (s->utcr3 & UTCR3_LBM) /* loopback */ {
1048 strongarm_uart_receive(s, &s->tx_fifo[s->tx_start], 1);
1049 } else if (s->chr) {
1050 qemu_chr_fe_write(s->chr, &s->tx_fifo[s->tx_start], 1);
1051 }
1052
1053 s->tx_start = (s->tx_start + 1) % 8;
1054 s->tx_len--;
1055 if (s->tx_len) {
1056 qemu_mod_timer(s->tx_timer, new_xmit_ts + s->char_transmit_time);
1057 }
1058 strongarm_uart_update_status(s);
1059 strongarm_uart_update_int_status(s);
1060 }
1061
1062 static uint64_t strongarm_uart_read(void *opaque, target_phys_addr_t addr,
1063 unsigned size)
1064 {
1065 StrongARMUARTState *s = opaque;
1066 uint16_t ret;
1067
1068 switch (addr) {
1069 case UTCR0:
1070 return s->utcr0;
1071
1072 case UTCR1:
1073 return s->brd >> 8;
1074
1075 case UTCR2:
1076 return s->brd & 0xff;
1077
1078 case UTCR3:
1079 return s->utcr3;
1080
1081 case UTDR:
1082 if (s->rx_len != 0) {
1083 ret = s->rx_fifo[s->rx_start];
1084 s->rx_start = (s->rx_start + 1) % 12;
1085 s->rx_len--;
1086 strongarm_uart_update_status(s);
1087 strongarm_uart_update_int_status(s);
1088 return ret;
1089 }
1090 return 0;
1091
1092 case UTSR0:
1093 return s->utsr0;
1094
1095 case UTSR1:
1096 return s->utsr1;
1097
1098 default:
1099 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1100 return 0;
1101 }
1102 }
1103
1104 static void strongarm_uart_write(void *opaque, target_phys_addr_t addr,
1105 uint64_t value, unsigned size)
1106 {
1107 StrongARMUARTState *s = opaque;
1108
1109 switch (addr) {
1110 case UTCR0:
1111 s->utcr0 = value & 0x7f;
1112 strongarm_uart_update_parameters(s);
1113 break;
1114
1115 case UTCR1:
1116 s->brd = (s->brd & 0xff) | ((value & 0xf) << 8);
1117 strongarm_uart_update_parameters(s);
1118 break;
1119
1120 case UTCR2:
1121 s->brd = (s->brd & 0xf00) | (value & 0xff);
1122 strongarm_uart_update_parameters(s);
1123 break;
1124
1125 case UTCR3:
1126 s->utcr3 = value & 0x3f;
1127 if ((s->utcr3 & UTCR3_RXE) == 0) {
1128 s->rx_len = 0;
1129 }
1130 if ((s->utcr3 & UTCR3_TXE) == 0) {
1131 s->tx_len = 0;
1132 }
1133 strongarm_uart_update_status(s);
1134 strongarm_uart_update_int_status(s);
1135 break;
1136
1137 case UTDR:
1138 if ((s->utcr3 & UTCR3_TXE) && s->tx_len != 8) {
1139 s->tx_fifo[(s->tx_start + s->tx_len) % 8] = value;
1140 s->tx_len++;
1141 strongarm_uart_update_status(s);
1142 strongarm_uart_update_int_status(s);
1143 if (s->tx_len == 1) {
1144 strongarm_uart_tx(s);
1145 }
1146 }
1147 break;
1148
1149 case UTSR0:
1150 s->utsr0 = s->utsr0 & ~(value &
1151 (UTSR0_REB | UTSR0_RBB | UTSR0_RID));
1152 strongarm_uart_update_int_status(s);
1153 break;
1154
1155 default:
1156 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1157 }
1158 }
1159
1160 static const MemoryRegionOps strongarm_uart_ops = {
1161 .read = strongarm_uart_read,
1162 .write = strongarm_uart_write,
1163 .endianness = DEVICE_NATIVE_ENDIAN,
1164 };
1165
1166 static int strongarm_uart_init(SysBusDevice *dev)
1167 {
1168 StrongARMUARTState *s = FROM_SYSBUS(StrongARMUARTState, dev);
1169
1170 memory_region_init_io(&s->iomem, &strongarm_uart_ops, s, "uart", 0x10000);
1171 sysbus_init_mmio(dev, &s->iomem);
1172 sysbus_init_irq(dev, &s->irq);
1173
1174 s->rx_timeout_timer = qemu_new_timer_ns(vm_clock, strongarm_uart_rx_to, s);
1175 s->tx_timer = qemu_new_timer_ns(vm_clock, strongarm_uart_tx, s);
1176
1177 if (s->chr) {
1178 qemu_chr_add_handlers(s->chr,
1179 strongarm_uart_can_receive,
1180 strongarm_uart_receive,
1181 strongarm_uart_event,
1182 s);
1183 }
1184
1185 return 0;
1186 }
1187
1188 static void strongarm_uart_reset(DeviceState *dev)
1189 {
1190 StrongARMUARTState *s = DO_UPCAST(StrongARMUARTState, busdev.qdev, dev);
1191
1192 s->utcr0 = UTCR0_DSS; /* 8 data, no parity */
1193 s->brd = 23; /* 9600 */
1194 /* enable send & recv - this actually violates spec */
1195 s->utcr3 = UTCR3_TXE | UTCR3_RXE;
1196
1197 s->rx_len = s->tx_len = 0;
1198
1199 strongarm_uart_update_parameters(s);
1200 strongarm_uart_update_status(s);
1201 strongarm_uart_update_int_status(s);
1202 }
1203
1204 static int strongarm_uart_post_load(void *opaque, int version_id)
1205 {
1206 StrongARMUARTState *s = opaque;
1207
1208 strongarm_uart_update_parameters(s);
1209 strongarm_uart_update_status(s);
1210 strongarm_uart_update_int_status(s);
1211
1212 /* tx and restart timer */
1213 if (s->tx_len) {
1214 strongarm_uart_tx(s);
1215 }
1216
1217 /* restart rx timeout timer */
1218 if (s->rx_len) {
1219 qemu_mod_timer(s->rx_timeout_timer,
1220 qemu_get_clock_ns(vm_clock) + s->char_transmit_time * 3);
1221 }
1222
1223 return 0;
1224 }
1225
1226 static const VMStateDescription vmstate_strongarm_uart_regs = {
1227 .name = "strongarm-uart",
1228 .version_id = 0,
1229 .minimum_version_id = 0,
1230 .minimum_version_id_old = 0,
1231 .post_load = strongarm_uart_post_load,
1232 .fields = (VMStateField[]) {
1233 VMSTATE_UINT8(utcr0, StrongARMUARTState),
1234 VMSTATE_UINT16(brd, StrongARMUARTState),
1235 VMSTATE_UINT8(utcr3, StrongARMUARTState),
1236 VMSTATE_UINT8(utsr0, StrongARMUARTState),
1237 VMSTATE_UINT8_ARRAY(tx_fifo, StrongARMUARTState, 8),
1238 VMSTATE_UINT8(tx_start, StrongARMUARTState),
1239 VMSTATE_UINT8(tx_len, StrongARMUARTState),
1240 VMSTATE_UINT16_ARRAY(rx_fifo, StrongARMUARTState, 12),
1241 VMSTATE_UINT8(rx_start, StrongARMUARTState),
1242 VMSTATE_UINT8(rx_len, StrongARMUARTState),
1243 VMSTATE_BOOL(wait_break_end, StrongARMUARTState),
1244 VMSTATE_END_OF_LIST(),
1245 },
1246 };
1247
1248 static SysBusDeviceInfo strongarm_uart_info = {
1249 .init = strongarm_uart_init,
1250 .qdev.name = "strongarm-uart",
1251 .qdev.desc = "StrongARM UART controller",
1252 .qdev.size = sizeof(StrongARMUARTState),
1253 .qdev.reset = strongarm_uart_reset,
1254 .qdev.vmsd = &vmstate_strongarm_uart_regs,
1255 .qdev.props = (Property[]) {
1256 DEFINE_PROP_CHR("chardev", StrongARMUARTState, chr),
1257 DEFINE_PROP_END_OF_LIST(),
1258 }
1259 };
1260
1261 /* Synchronous Serial Ports */
1262 typedef struct {
1263 SysBusDevice busdev;
1264 MemoryRegion iomem;
1265 qemu_irq irq;
1266 SSIBus *bus;
1267
1268 uint16_t sscr[2];
1269 uint16_t sssr;
1270
1271 uint16_t rx_fifo[8];
1272 uint8_t rx_level;
1273 uint8_t rx_start;
1274 } StrongARMSSPState;
1275
1276 #define SSCR0 0x60 /* SSP Control register 0 */
1277 #define SSCR1 0x64 /* SSP Control register 1 */
1278 #define SSDR 0x6c /* SSP Data register */
1279 #define SSSR 0x74 /* SSP Status register */
1280
1281 /* Bitfields for above registers */
1282 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00)
1283 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10)
1284 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20)
1285 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30)
1286 #define SSCR0_SSE (1 << 7)
1287 #define SSCR0_DSS(x) (((x) & 0xf) + 1)
1288 #define SSCR1_RIE (1 << 0)
1289 #define SSCR1_TIE (1 << 1)
1290 #define SSCR1_LBM (1 << 2)
1291 #define SSSR_TNF (1 << 2)
1292 #define SSSR_RNE (1 << 3)
1293 #define SSSR_TFS (1 << 5)
1294 #define SSSR_RFS (1 << 6)
1295 #define SSSR_ROR (1 << 7)
1296 #define SSSR_RW 0x0080
1297
1298 static void strongarm_ssp_int_update(StrongARMSSPState *s)
1299 {
1300 int level = 0;
1301
1302 level |= (s->sssr & SSSR_ROR);
1303 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE);
1304 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE);
1305 qemu_set_irq(s->irq, level);
1306 }
1307
1308 static void strongarm_ssp_fifo_update(StrongARMSSPState *s)
1309 {
1310 s->sssr &= ~SSSR_TFS;
1311 s->sssr &= ~SSSR_TNF;
1312 if (s->sscr[0] & SSCR0_SSE) {
1313 if (s->rx_level >= 4) {
1314 s->sssr |= SSSR_RFS;
1315 } else {
1316 s->sssr &= ~SSSR_RFS;
1317 }
1318 if (s->rx_level) {
1319 s->sssr |= SSSR_RNE;
1320 } else {
1321 s->sssr &= ~SSSR_RNE;
1322 }
1323 /* TX FIFO is never filled, so it is always in underrun
1324 condition if SSP is enabled */
1325 s->sssr |= SSSR_TFS;
1326 s->sssr |= SSSR_TNF;
1327 }
1328
1329 strongarm_ssp_int_update(s);
1330 }
1331
1332 static uint64_t strongarm_ssp_read(void *opaque, target_phys_addr_t addr,
1333 unsigned size)
1334 {
1335 StrongARMSSPState *s = opaque;
1336 uint32_t retval;
1337
1338 switch (addr) {
1339 case SSCR0:
1340 return s->sscr[0];
1341 case SSCR1:
1342 return s->sscr[1];
1343 case SSSR:
1344 return s->sssr;
1345 case SSDR:
1346 if (~s->sscr[0] & SSCR0_SSE) {
1347 return 0xffffffff;
1348 }
1349 if (s->rx_level < 1) {
1350 printf("%s: SSP Rx Underrun\n", __func__);
1351 return 0xffffffff;
1352 }
1353 s->rx_level--;
1354 retval = s->rx_fifo[s->rx_start++];
1355 s->rx_start &= 0x7;
1356 strongarm_ssp_fifo_update(s);
1357 return retval;
1358 default:
1359 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1360 break;
1361 }
1362 return 0;
1363 }
1364
1365 static void strongarm_ssp_write(void *opaque, target_phys_addr_t addr,
1366 uint64_t value, unsigned size)
1367 {
1368 StrongARMSSPState *s = opaque;
1369
1370 switch (addr) {
1371 case SSCR0:
1372 s->sscr[0] = value & 0xffbf;
1373 if ((s->sscr[0] & SSCR0_SSE) && SSCR0_DSS(value) < 4) {
1374 printf("%s: Wrong data size: %i bits\n", __func__,
1375 (int)SSCR0_DSS(value));
1376 }
1377 if (!(value & SSCR0_SSE)) {
1378 s->sssr = 0;
1379 s->rx_level = 0;
1380 }
1381 strongarm_ssp_fifo_update(s);
1382 break;
1383
1384 case SSCR1:
1385 s->sscr[1] = value & 0x2f;
1386 if (value & SSCR1_LBM) {
1387 printf("%s: Attempt to use SSP LBM mode\n", __func__);
1388 }
1389 strongarm_ssp_fifo_update(s);
1390 break;
1391
1392 case SSSR:
1393 s->sssr &= ~(value & SSSR_RW);
1394 strongarm_ssp_int_update(s);
1395 break;
1396
1397 case SSDR:
1398 if (SSCR0_UWIRE(s->sscr[0])) {
1399 value &= 0xff;
1400 } else
1401 /* Note how 32bits overflow does no harm here */
1402 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1;
1403
1404 /* Data goes from here to the Tx FIFO and is shifted out from
1405 * there directly to the slave, no need to buffer it.
1406 */
1407 if (s->sscr[0] & SSCR0_SSE) {
1408 uint32_t readval;
1409 if (s->sscr[1] & SSCR1_LBM) {
1410 readval = value;
1411 } else {
1412 readval = ssi_transfer(s->bus, value);
1413 }
1414
1415 if (s->rx_level < 0x08) {
1416 s->rx_fifo[(s->rx_start + s->rx_level++) & 0x7] = readval;
1417 } else {
1418 s->sssr |= SSSR_ROR;
1419 }
1420 }
1421 strongarm_ssp_fifo_update(s);
1422 break;
1423
1424 default:
1425 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1426 break;
1427 }
1428 }
1429
1430 static const MemoryRegionOps strongarm_ssp_ops = {
1431 .read = strongarm_ssp_read,
1432 .write = strongarm_ssp_write,
1433 .endianness = DEVICE_NATIVE_ENDIAN,
1434 };
1435
1436 static int strongarm_ssp_post_load(void *opaque, int version_id)
1437 {
1438 StrongARMSSPState *s = opaque;
1439
1440 strongarm_ssp_fifo_update(s);
1441
1442 return 0;
1443 }
1444
1445 static int strongarm_ssp_init(SysBusDevice *dev)
1446 {
1447 StrongARMSSPState *s = FROM_SYSBUS(StrongARMSSPState, dev);
1448
1449 sysbus_init_irq(dev, &s->irq);
1450
1451 memory_region_init_io(&s->iomem, &strongarm_ssp_ops, s, "ssp", 0x1000);
1452 sysbus_init_mmio(dev, &s->iomem);
1453
1454 s->bus = ssi_create_bus(&dev->qdev, "ssi");
1455 return 0;
1456 }
1457
1458 static void strongarm_ssp_reset(DeviceState *dev)
1459 {
1460 StrongARMSSPState *s = DO_UPCAST(StrongARMSSPState, busdev.qdev, dev);
1461 s->sssr = 0x03; /* 3 bit data, SPI, disabled */
1462 s->rx_start = 0;
1463 s->rx_level = 0;
1464 }
1465
1466 static const VMStateDescription vmstate_strongarm_ssp_regs = {
1467 .name = "strongarm-ssp",
1468 .version_id = 0,
1469 .minimum_version_id = 0,
1470 .minimum_version_id_old = 0,
1471 .post_load = strongarm_ssp_post_load,
1472 .fields = (VMStateField[]) {
1473 VMSTATE_UINT16_ARRAY(sscr, StrongARMSSPState, 2),
1474 VMSTATE_UINT16(sssr, StrongARMSSPState),
1475 VMSTATE_UINT16_ARRAY(rx_fifo, StrongARMSSPState, 8),
1476 VMSTATE_UINT8(rx_start, StrongARMSSPState),
1477 VMSTATE_UINT8(rx_level, StrongARMSSPState),
1478 VMSTATE_END_OF_LIST(),
1479 },
1480 };
1481
1482 static SysBusDeviceInfo strongarm_ssp_info = {
1483 .init = strongarm_ssp_init,
1484 .qdev.name = "strongarm-ssp",
1485 .qdev.desc = "StrongARM SSP controller",
1486 .qdev.size = sizeof(StrongARMSSPState),
1487 .qdev.reset = strongarm_ssp_reset,
1488 .qdev.vmsd = &vmstate_strongarm_ssp_regs,
1489 };
1490
1491 /* Main CPU functions */
1492 StrongARMState *sa1110_init(MemoryRegion *sysmem,
1493 unsigned int sdram_size, const char *rev)
1494 {
1495 StrongARMState *s;
1496 qemu_irq *pic;
1497 int i;
1498
1499 s = g_malloc0(sizeof(StrongARMState));
1500
1501 if (!rev) {
1502 rev = "sa1110-b5";
1503 }
1504
1505 if (strncmp(rev, "sa1110", 6)) {
1506 error_report("Machine requires a SA1110 processor.");
1507 exit(1);
1508 }
1509
1510 s->env = cpu_init(rev);
1511
1512 if (!s->env) {
1513 error_report("Unable to find CPU definition");
1514 exit(1);
1515 }
1516
1517 memory_region_init_ram(&s->sdram, "strongarm.sdram", sdram_size);
1518 vmstate_register_ram_global(&s->sdram);
1519 memory_region_add_subregion(sysmem, SA_SDCS0, &s->sdram);
1520
1521 pic = arm_pic_init_cpu(s->env);
1522 s->pic = sysbus_create_varargs("strongarm_pic", 0x90050000,
1523 pic[ARM_PIC_CPU_IRQ], pic[ARM_PIC_CPU_FIQ], NULL);
1524
1525 sysbus_create_varargs("pxa25x-timer", 0x90000000,
1526 qdev_get_gpio_in(s->pic, SA_PIC_OSTC0),
1527 qdev_get_gpio_in(s->pic, SA_PIC_OSTC1),
1528 qdev_get_gpio_in(s->pic, SA_PIC_OSTC2),
1529 qdev_get_gpio_in(s->pic, SA_PIC_OSTC3),
1530 NULL);
1531
1532 sysbus_create_simple("strongarm-rtc", 0x90010000,
1533 qdev_get_gpio_in(s->pic, SA_PIC_RTC_ALARM));
1534
1535 s->gpio = strongarm_gpio_init(0x90040000, s->pic);
1536
1537 s->ppc = sysbus_create_varargs("strongarm-ppc", 0x90060000, NULL);
1538
1539 for (i = 0; sa_serial[i].io_base; i++) {
1540 DeviceState *dev = qdev_create(NULL, "strongarm-uart");
1541 qdev_prop_set_chr(dev, "chardev", serial_hds[i]);
1542 qdev_init_nofail(dev);
1543 sysbus_mmio_map(sysbus_from_qdev(dev), 0,
1544 sa_serial[i].io_base);
1545 sysbus_connect_irq(sysbus_from_qdev(dev), 0,
1546 qdev_get_gpio_in(s->pic, sa_serial[i].irq));
1547 }
1548
1549 s->ssp = sysbus_create_varargs("strongarm-ssp", 0x80070000,
1550 qdev_get_gpio_in(s->pic, SA_PIC_SSP), NULL);
1551 s->ssp_bus = (SSIBus *)qdev_get_child_bus(s->ssp, "ssi");
1552
1553 return s;
1554 }
1555
1556 static void strongarm_register_devices(void)
1557 {
1558 sysbus_register_withprop(&strongarm_pic_info);
1559 sysbus_register_withprop(&strongarm_rtc_sysbus_info);
1560 sysbus_register_withprop(&strongarm_gpio_info);
1561 sysbus_register_withprop(&strongarm_ppc_info);
1562 sysbus_register_withprop(&strongarm_uart_info);
1563 sysbus_register_withprop(&strongarm_ssp_info);
1564 }
1565 device_init(strongarm_register_devices)