linux-user: stack_base is now mandatory on all targets
[qemu.git] / hw / strongarm.h
1 #ifndef _STRONGARM_H
2 #define _STRONGARM_H
3
4 #include "memory.h"
5
6 #define SA_CS0 0x00000000
7 #define SA_CS1 0x08000000
8 #define SA_CS2 0x10000000
9 #define SA_CS3 0x18000000
10 #define SA_PCMCIA_CS0 0x20000000
11 #define SA_PCMCIA_CS1 0x30000000
12 #define SA_CS4 0x40000000
13 #define SA_CS5 0x48000000
14 /* system registers here */
15 #define SA_SDCS0 0xc0000000
16 #define SA_SDCS1 0xc8000000
17 #define SA_SDCS2 0xd0000000
18 #define SA_SDCS3 0xd8000000
19
20 enum {
21 SA_PIC_GPIO0_EDGE = 0,
22 SA_PIC_GPIO1_EDGE,
23 SA_PIC_GPIO2_EDGE,
24 SA_PIC_GPIO3_EDGE,
25 SA_PIC_GPIO4_EDGE,
26 SA_PIC_GPIO5_EDGE,
27 SA_PIC_GPIO6_EDGE,
28 SA_PIC_GPIO7_EDGE,
29 SA_PIC_GPIO8_EDGE,
30 SA_PIC_GPIO9_EDGE,
31 SA_PIC_GPIO10_EDGE,
32 SA_PIC_GPIOX_EDGE,
33 SA_PIC_LCD,
34 SA_PIC_UDC,
35 SA_PIC_RSVD1,
36 SA_PIC_UART1,
37 SA_PIC_UART2,
38 SA_PIC_UART3,
39 SA_PIC_MCP,
40 SA_PIC_SSP,
41 SA_PIC_DMA_CH0,
42 SA_PIC_DMA_CH1,
43 SA_PIC_DMA_CH2,
44 SA_PIC_DMA_CH3,
45 SA_PIC_DMA_CH4,
46 SA_PIC_DMA_CH5,
47 SA_PIC_OSTC0,
48 SA_PIC_OSTC1,
49 SA_PIC_OSTC2,
50 SA_PIC_OSTC3,
51 SA_PIC_RTC_HZ,
52 SA_PIC_RTC_ALARM,
53 };
54
55 typedef struct {
56 CPUState *env;
57 MemoryRegion sdram;
58 DeviceState *pic;
59 DeviceState *gpio;
60 DeviceState *ppc;
61 DeviceState *ssp;
62 SSIBus *ssp_bus;
63 } StrongARMState;
64
65 StrongARMState *sa1110_init(MemoryRegion *sysmem,
66 unsigned int sdram_size, const char *rev);
67
68 #endif