qdev: integrate with QEMU Object Model (v2)
[qemu.git] / hw / sun4u.c
1 /*
2 * QEMU Sun4u/Sun4v System Emulator
3 *
4 * Copyright (c) 2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "pci.h"
26 #include "apb_pci.h"
27 #include "pc.h"
28 #include "nvram.h"
29 #include "fdc.h"
30 #include "net.h"
31 #include "qemu-timer.h"
32 #include "sysemu.h"
33 #include "boards.h"
34 #include "firmware_abi.h"
35 #include "fw_cfg.h"
36 #include "sysbus.h"
37 #include "ide.h"
38 #include "loader.h"
39 #include "elf.h"
40 #include "blockdev.h"
41 #include "exec-memory.h"
42
43 //#define DEBUG_IRQ
44 //#define DEBUG_EBUS
45 //#define DEBUG_TIMER
46
47 #ifdef DEBUG_IRQ
48 #define CPUIRQ_DPRINTF(fmt, ...) \
49 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
50 #else
51 #define CPUIRQ_DPRINTF(fmt, ...)
52 #endif
53
54 #ifdef DEBUG_EBUS
55 #define EBUS_DPRINTF(fmt, ...) \
56 do { printf("EBUS: " fmt , ## __VA_ARGS__); } while (0)
57 #else
58 #define EBUS_DPRINTF(fmt, ...)
59 #endif
60
61 #ifdef DEBUG_TIMER
62 #define TIMER_DPRINTF(fmt, ...) \
63 do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0)
64 #else
65 #define TIMER_DPRINTF(fmt, ...)
66 #endif
67
68 #define KERNEL_LOAD_ADDR 0x00404000
69 #define CMDLINE_ADDR 0x003ff000
70 #define INITRD_LOAD_ADDR 0x00300000
71 #define PROM_SIZE_MAX (4 * 1024 * 1024)
72 #define PROM_VADDR 0x000ffd00000ULL
73 #define APB_SPECIAL_BASE 0x1fe00000000ULL
74 #define APB_MEM_BASE 0x1ff00000000ULL
75 #define APB_PCI_IO_BASE (APB_SPECIAL_BASE + 0x02000000ULL)
76 #define PROM_FILENAME "openbios-sparc64"
77 #define NVRAM_SIZE 0x2000
78 #define MAX_IDE_BUS 2
79 #define BIOS_CFG_IOPORT 0x510
80 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
81 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
82 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
83
84 #define MAX_PILS 16
85
86 #define TICK_MAX 0x7fffffffffffffffULL
87
88 struct hwdef {
89 const char * const default_cpu_model;
90 uint16_t machine_id;
91 uint64_t prom_addr;
92 uint64_t console_serial_base;
93 };
94
95 typedef struct EbusState {
96 PCIDevice pci_dev;
97 MemoryRegion bar0;
98 MemoryRegion bar1;
99 } EbusState;
100
101 int DMA_get_channel_mode (int nchan)
102 {
103 return 0;
104 }
105 int DMA_read_memory (int nchan, void *buf, int pos, int size)
106 {
107 return 0;
108 }
109 int DMA_write_memory (int nchan, void *buf, int pos, int size)
110 {
111 return 0;
112 }
113 void DMA_hold_DREQ (int nchan) {}
114 void DMA_release_DREQ (int nchan) {}
115 void DMA_schedule(int nchan) {}
116
117 void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit)
118 {
119 }
120
121 void DMA_register_channel (int nchan,
122 DMA_transfer_handler transfer_handler,
123 void *opaque)
124 {
125 }
126
127 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
128 {
129 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
130 return 0;
131 }
132
133 static int sun4u_NVRAM_set_params(M48t59State *nvram, uint16_t NVRAM_size,
134 const char *arch, ram_addr_t RAM_size,
135 const char *boot_devices,
136 uint32_t kernel_image, uint32_t kernel_size,
137 const char *cmdline,
138 uint32_t initrd_image, uint32_t initrd_size,
139 uint32_t NVRAM_image,
140 int width, int height, int depth,
141 const uint8_t *macaddr)
142 {
143 unsigned int i;
144 uint32_t start, end;
145 uint8_t image[0x1ff0];
146 struct OpenBIOS_nvpart_v1 *part_header;
147
148 memset(image, '\0', sizeof(image));
149
150 start = 0;
151
152 // OpenBIOS nvram variables
153 // Variable partition
154 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
155 part_header->signature = OPENBIOS_PART_SYSTEM;
156 pstrcpy(part_header->name, sizeof(part_header->name), "system");
157
158 end = start + sizeof(struct OpenBIOS_nvpart_v1);
159 for (i = 0; i < nb_prom_envs; i++)
160 end = OpenBIOS_set_var(image, end, prom_envs[i]);
161
162 // End marker
163 image[end++] = '\0';
164
165 end = start + ((end - start + 15) & ~15);
166 OpenBIOS_finish_partition(part_header, end - start);
167
168 // free partition
169 start = end;
170 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
171 part_header->signature = OPENBIOS_PART_FREE;
172 pstrcpy(part_header->name, sizeof(part_header->name), "free");
173
174 end = 0x1fd0;
175 OpenBIOS_finish_partition(part_header, end - start);
176
177 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
178
179 for (i = 0; i < sizeof(image); i++)
180 m48t59_write(nvram, i, image[i]);
181
182 return 0;
183 }
184 static unsigned long sun4u_load_kernel(const char *kernel_filename,
185 const char *initrd_filename,
186 ram_addr_t RAM_size, long *initrd_size)
187 {
188 int linux_boot;
189 unsigned int i;
190 long kernel_size;
191 uint8_t *ptr;
192
193 linux_boot = (kernel_filename != NULL);
194
195 kernel_size = 0;
196 if (linux_boot) {
197 int bswap_needed;
198
199 #ifdef BSWAP_NEEDED
200 bswap_needed = 1;
201 #else
202 bswap_needed = 0;
203 #endif
204 kernel_size = load_elf(kernel_filename, NULL, NULL, NULL,
205 NULL, NULL, 1, ELF_MACHINE, 0);
206 if (kernel_size < 0)
207 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
208 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
209 TARGET_PAGE_SIZE);
210 if (kernel_size < 0)
211 kernel_size = load_image_targphys(kernel_filename,
212 KERNEL_LOAD_ADDR,
213 RAM_size - KERNEL_LOAD_ADDR);
214 if (kernel_size < 0) {
215 fprintf(stderr, "qemu: could not load kernel '%s'\n",
216 kernel_filename);
217 exit(1);
218 }
219
220 /* load initrd */
221 *initrd_size = 0;
222 if (initrd_filename) {
223 *initrd_size = load_image_targphys(initrd_filename,
224 INITRD_LOAD_ADDR,
225 RAM_size - INITRD_LOAD_ADDR);
226 if (*initrd_size < 0) {
227 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
228 initrd_filename);
229 exit(1);
230 }
231 }
232 if (*initrd_size > 0) {
233 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
234 ptr = rom_ptr(KERNEL_LOAD_ADDR + i);
235 if (ldl_p(ptr + 8) == 0x48647253) { /* HdrS */
236 stl_p(ptr + 24, INITRD_LOAD_ADDR + KERNEL_LOAD_ADDR - 0x4000);
237 stl_p(ptr + 28, *initrd_size);
238 break;
239 }
240 }
241 }
242 }
243 return kernel_size;
244 }
245
246 void cpu_check_irqs(CPUState *env)
247 {
248 uint32_t pil = env->pil_in |
249 (env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER));
250
251 /* check if TM or SM in SOFTINT are set
252 setting these also causes interrupt 14 */
253 if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) {
254 pil |= 1 << 14;
255 }
256
257 /* The bit corresponding to psrpil is (1<< psrpil), the next bit
258 is (2 << psrpil). */
259 if (pil < (2 << env->psrpil)){
260 if (env->interrupt_request & CPU_INTERRUPT_HARD) {
261 CPUIRQ_DPRINTF("Reset CPU IRQ (current interrupt %x)\n",
262 env->interrupt_index);
263 env->interrupt_index = 0;
264 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
265 }
266 return;
267 }
268
269 if (cpu_interrupts_enabled(env)) {
270
271 unsigned int i;
272
273 for (i = 15; i > env->psrpil; i--) {
274 if (pil & (1 << i)) {
275 int old_interrupt = env->interrupt_index;
276 int new_interrupt = TT_EXTINT | i;
277
278 if (env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt) {
279 CPUIRQ_DPRINTF("Not setting CPU IRQ: TL=%d "
280 "current %x >= pending %x\n",
281 env->tl, cpu_tsptr(env)->tt, new_interrupt);
282 } else if (old_interrupt != new_interrupt) {
283 env->interrupt_index = new_interrupt;
284 CPUIRQ_DPRINTF("Set CPU IRQ %d old=%x new=%x\n", i,
285 old_interrupt, new_interrupt);
286 cpu_interrupt(env, CPU_INTERRUPT_HARD);
287 }
288 break;
289 }
290 }
291 } else if (env->interrupt_request & CPU_INTERRUPT_HARD) {
292 CPUIRQ_DPRINTF("Interrupts disabled, pil=%08x pil_in=%08x softint=%08x "
293 "current interrupt %x\n",
294 pil, env->pil_in, env->softint, env->interrupt_index);
295 env->interrupt_index = 0;
296 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
297 }
298 }
299
300 static void cpu_kick_irq(CPUState *env)
301 {
302 env->halted = 0;
303 cpu_check_irqs(env);
304 qemu_cpu_kick(env);
305 }
306
307 static void cpu_set_irq(void *opaque, int irq, int level)
308 {
309 CPUState *env = opaque;
310
311 if (level) {
312 CPUIRQ_DPRINTF("Raise CPU IRQ %d\n", irq);
313 env->pil_in |= 1 << irq;
314 cpu_kick_irq(env);
315 } else {
316 CPUIRQ_DPRINTF("Lower CPU IRQ %d\n", irq);
317 env->pil_in &= ~(1 << irq);
318 cpu_check_irqs(env);
319 }
320 }
321
322 typedef struct ResetData {
323 CPUState *env;
324 uint64_t prom_addr;
325 } ResetData;
326
327 void cpu_put_timer(QEMUFile *f, CPUTimer *s)
328 {
329 qemu_put_be32s(f, &s->frequency);
330 qemu_put_be32s(f, &s->disabled);
331 qemu_put_be64s(f, &s->disabled_mask);
332 qemu_put_sbe64s(f, &s->clock_offset);
333
334 qemu_put_timer(f, s->qtimer);
335 }
336
337 void cpu_get_timer(QEMUFile *f, CPUTimer *s)
338 {
339 qemu_get_be32s(f, &s->frequency);
340 qemu_get_be32s(f, &s->disabled);
341 qemu_get_be64s(f, &s->disabled_mask);
342 qemu_get_sbe64s(f, &s->clock_offset);
343
344 qemu_get_timer(f, s->qtimer);
345 }
346
347 static CPUTimer* cpu_timer_create(const char* name, CPUState *env,
348 QEMUBHFunc *cb, uint32_t frequency,
349 uint64_t disabled_mask)
350 {
351 CPUTimer *timer = g_malloc0(sizeof (CPUTimer));
352
353 timer->name = name;
354 timer->frequency = frequency;
355 timer->disabled_mask = disabled_mask;
356
357 timer->disabled = 1;
358 timer->clock_offset = qemu_get_clock_ns(vm_clock);
359
360 timer->qtimer = qemu_new_timer_ns(vm_clock, cb, env);
361
362 return timer;
363 }
364
365 static void cpu_timer_reset(CPUTimer *timer)
366 {
367 timer->disabled = 1;
368 timer->clock_offset = qemu_get_clock_ns(vm_clock);
369
370 qemu_del_timer(timer->qtimer);
371 }
372
373 static void main_cpu_reset(void *opaque)
374 {
375 ResetData *s = (ResetData *)opaque;
376 CPUState *env = s->env;
377 static unsigned int nr_resets;
378
379 cpu_reset(env);
380
381 cpu_timer_reset(env->tick);
382 cpu_timer_reset(env->stick);
383 cpu_timer_reset(env->hstick);
384
385 env->gregs[1] = 0; // Memory start
386 env->gregs[2] = ram_size; // Memory size
387 env->gregs[3] = 0; // Machine description XXX
388 if (nr_resets++ == 0) {
389 /* Power on reset */
390 env->pc = s->prom_addr + 0x20ULL;
391 } else {
392 env->pc = s->prom_addr + 0x40ULL;
393 }
394 env->npc = env->pc + 4;
395 }
396
397 static void tick_irq(void *opaque)
398 {
399 CPUState *env = opaque;
400
401 CPUTimer* timer = env->tick;
402
403 if (timer->disabled) {
404 CPUIRQ_DPRINTF("tick_irq: softint disabled\n");
405 return;
406 } else {
407 CPUIRQ_DPRINTF("tick: fire\n");
408 }
409
410 env->softint |= SOFTINT_TIMER;
411 cpu_kick_irq(env);
412 }
413
414 static void stick_irq(void *opaque)
415 {
416 CPUState *env = opaque;
417
418 CPUTimer* timer = env->stick;
419
420 if (timer->disabled) {
421 CPUIRQ_DPRINTF("stick_irq: softint disabled\n");
422 return;
423 } else {
424 CPUIRQ_DPRINTF("stick: fire\n");
425 }
426
427 env->softint |= SOFTINT_STIMER;
428 cpu_kick_irq(env);
429 }
430
431 static void hstick_irq(void *opaque)
432 {
433 CPUState *env = opaque;
434
435 CPUTimer* timer = env->hstick;
436
437 if (timer->disabled) {
438 CPUIRQ_DPRINTF("hstick_irq: softint disabled\n");
439 return;
440 } else {
441 CPUIRQ_DPRINTF("hstick: fire\n");
442 }
443
444 env->softint |= SOFTINT_STIMER;
445 cpu_kick_irq(env);
446 }
447
448 static int64_t cpu_to_timer_ticks(int64_t cpu_ticks, uint32_t frequency)
449 {
450 return muldiv64(cpu_ticks, get_ticks_per_sec(), frequency);
451 }
452
453 static uint64_t timer_to_cpu_ticks(int64_t timer_ticks, uint32_t frequency)
454 {
455 return muldiv64(timer_ticks, frequency, get_ticks_per_sec());
456 }
457
458 void cpu_tick_set_count(CPUTimer *timer, uint64_t count)
459 {
460 uint64_t real_count = count & ~timer->disabled_mask;
461 uint64_t disabled_bit = count & timer->disabled_mask;
462
463 int64_t vm_clock_offset = qemu_get_clock_ns(vm_clock) -
464 cpu_to_timer_ticks(real_count, timer->frequency);
465
466 TIMER_DPRINTF("%s set_count count=0x%016lx (%s) p=%p\n",
467 timer->name, real_count,
468 timer->disabled?"disabled":"enabled", timer);
469
470 timer->disabled = disabled_bit ? 1 : 0;
471 timer->clock_offset = vm_clock_offset;
472 }
473
474 uint64_t cpu_tick_get_count(CPUTimer *timer)
475 {
476 uint64_t real_count = timer_to_cpu_ticks(
477 qemu_get_clock_ns(vm_clock) - timer->clock_offset,
478 timer->frequency);
479
480 TIMER_DPRINTF("%s get_count count=0x%016lx (%s) p=%p\n",
481 timer->name, real_count,
482 timer->disabled?"disabled":"enabled", timer);
483
484 if (timer->disabled)
485 real_count |= timer->disabled_mask;
486
487 return real_count;
488 }
489
490 void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit)
491 {
492 int64_t now = qemu_get_clock_ns(vm_clock);
493
494 uint64_t real_limit = limit & ~timer->disabled_mask;
495 timer->disabled = (limit & timer->disabled_mask) ? 1 : 0;
496
497 int64_t expires = cpu_to_timer_ticks(real_limit, timer->frequency) +
498 timer->clock_offset;
499
500 if (expires < now) {
501 expires = now + 1;
502 }
503
504 TIMER_DPRINTF("%s set_limit limit=0x%016lx (%s) p=%p "
505 "called with limit=0x%016lx at 0x%016lx (delta=0x%016lx)\n",
506 timer->name, real_limit,
507 timer->disabled?"disabled":"enabled",
508 timer, limit,
509 timer_to_cpu_ticks(now - timer->clock_offset,
510 timer->frequency),
511 timer_to_cpu_ticks(expires - now, timer->frequency));
512
513 if (!real_limit) {
514 TIMER_DPRINTF("%s set_limit limit=ZERO - not starting timer\n",
515 timer->name);
516 qemu_del_timer(timer->qtimer);
517 } else if (timer->disabled) {
518 qemu_del_timer(timer->qtimer);
519 } else {
520 qemu_mod_timer(timer->qtimer, expires);
521 }
522 }
523
524 static void dummy_isa_irq_handler(void *opaque, int n, int level)
525 {
526 }
527
528 /* EBUS (Eight bit bus) bridge */
529 static ISABus *
530 pci_ebus_init(PCIBus *bus, int devfn)
531 {
532 qemu_irq *isa_irq;
533 PCIDevice *pci_dev;
534 ISABus *isa_bus;
535
536 pci_dev = pci_create_simple(bus, devfn, "ebus");
537 isa_bus = DO_UPCAST(ISABus, qbus,
538 qdev_get_child_bus(&pci_dev->qdev, "isa.0"));
539 isa_irq = qemu_allocate_irqs(dummy_isa_irq_handler, NULL, 16);
540 isa_bus_irqs(isa_bus, isa_irq);
541 return isa_bus;
542 }
543
544 static int
545 pci_ebus_init1(PCIDevice *pci_dev)
546 {
547 EbusState *s = DO_UPCAST(EbusState, pci_dev, pci_dev);
548
549 isa_bus_new(&pci_dev->qdev, pci_address_space_io(pci_dev));
550
551 pci_dev->config[0x04] = 0x06; // command = bus master, pci mem
552 pci_dev->config[0x05] = 0x00;
553 pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
554 pci_dev->config[0x07] = 0x03; // status = medium devsel
555 pci_dev->config[0x09] = 0x00; // programming i/f
556 pci_dev->config[0x0D] = 0x0a; // latency_timer
557
558 isa_mmio_setup(&s->bar0, 0x1000000);
559 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
560 isa_mmio_setup(&s->bar1, 0x800000);
561 pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar1);
562 return 0;
563 }
564
565 static PCIDeviceInfo ebus_info = {
566 .qdev.name = "ebus",
567 .qdev.size = sizeof(EbusState),
568 .init = pci_ebus_init1,
569 .vendor_id = PCI_VENDOR_ID_SUN,
570 .device_id = PCI_DEVICE_ID_SUN_EBUS,
571 .revision = 0x01,
572 .class_id = PCI_CLASS_BRIDGE_OTHER,
573 };
574
575 static void pci_ebus_register(void)
576 {
577 pci_qdev_register(&ebus_info);
578 }
579
580 device_init(pci_ebus_register);
581
582 typedef struct PROMState {
583 SysBusDevice busdev;
584 MemoryRegion prom;
585 } PROMState;
586
587 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
588 {
589 target_phys_addr_t *base_addr = (target_phys_addr_t *)opaque;
590 return addr + *base_addr - PROM_VADDR;
591 }
592
593 /* Boot PROM (OpenBIOS) */
594 static void prom_init(target_phys_addr_t addr, const char *bios_name)
595 {
596 DeviceState *dev;
597 SysBusDevice *s;
598 char *filename;
599 int ret;
600
601 dev = qdev_create(NULL, "openprom");
602 qdev_init_nofail(dev);
603 s = sysbus_from_qdev(dev);
604
605 sysbus_mmio_map(s, 0, addr);
606
607 /* load boot prom */
608 if (bios_name == NULL) {
609 bios_name = PROM_FILENAME;
610 }
611 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
612 if (filename) {
613 ret = load_elf(filename, translate_prom_address, &addr,
614 NULL, NULL, NULL, 1, ELF_MACHINE, 0);
615 if (ret < 0 || ret > PROM_SIZE_MAX) {
616 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
617 }
618 g_free(filename);
619 } else {
620 ret = -1;
621 }
622 if (ret < 0 || ret > PROM_SIZE_MAX) {
623 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
624 exit(1);
625 }
626 }
627
628 static int prom_init1(SysBusDevice *dev)
629 {
630 PROMState *s = FROM_SYSBUS(PROMState, dev);
631
632 memory_region_init_ram(&s->prom, "sun4u.prom", PROM_SIZE_MAX);
633 vmstate_register_ram_global(&s->prom);
634 memory_region_set_readonly(&s->prom, true);
635 sysbus_init_mmio(dev, &s->prom);
636 return 0;
637 }
638
639 static SysBusDeviceInfo prom_info = {
640 .init = prom_init1,
641 .qdev.name = "openprom",
642 .qdev.size = sizeof(PROMState),
643 .qdev.props = (Property[]) {
644 {/* end of property list */}
645 }
646 };
647
648 static void prom_register_devices(void)
649 {
650 sysbus_register_withprop(&prom_info);
651 }
652
653 device_init(prom_register_devices);
654
655
656 typedef struct RamDevice
657 {
658 SysBusDevice busdev;
659 MemoryRegion ram;
660 uint64_t size;
661 } RamDevice;
662
663 /* System RAM */
664 static int ram_init1(SysBusDevice *dev)
665 {
666 RamDevice *d = FROM_SYSBUS(RamDevice, dev);
667
668 memory_region_init_ram(&d->ram, "sun4u.ram", d->size);
669 vmstate_register_ram_global(&d->ram);
670 sysbus_init_mmio(dev, &d->ram);
671 return 0;
672 }
673
674 static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size)
675 {
676 DeviceState *dev;
677 SysBusDevice *s;
678 RamDevice *d;
679
680 /* allocate RAM */
681 dev = qdev_create(NULL, "memory");
682 s = sysbus_from_qdev(dev);
683
684 d = FROM_SYSBUS(RamDevice, s);
685 d->size = RAM_size;
686 qdev_init_nofail(dev);
687
688 sysbus_mmio_map(s, 0, addr);
689 }
690
691 static SysBusDeviceInfo ram_info = {
692 .init = ram_init1,
693 .qdev.name = "memory",
694 .qdev.size = sizeof(RamDevice),
695 .qdev.props = (Property[]) {
696 DEFINE_PROP_UINT64("size", RamDevice, size, 0),
697 DEFINE_PROP_END_OF_LIST(),
698 }
699 };
700
701 static void ram_register_devices(void)
702 {
703 sysbus_register_withprop(&ram_info);
704 }
705
706 device_init(ram_register_devices);
707
708 static CPUState *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef)
709 {
710 CPUState *env;
711 ResetData *reset_info;
712
713 uint32_t tick_frequency = 100*1000000;
714 uint32_t stick_frequency = 100*1000000;
715 uint32_t hstick_frequency = 100*1000000;
716
717 if (!cpu_model)
718 cpu_model = hwdef->default_cpu_model;
719 env = cpu_init(cpu_model);
720 if (!env) {
721 fprintf(stderr, "Unable to find Sparc CPU definition\n");
722 exit(1);
723 }
724
725 env->tick = cpu_timer_create("tick", env, tick_irq,
726 tick_frequency, TICK_NPT_MASK);
727
728 env->stick = cpu_timer_create("stick", env, stick_irq,
729 stick_frequency, TICK_INT_DIS);
730
731 env->hstick = cpu_timer_create("hstick", env, hstick_irq,
732 hstick_frequency, TICK_INT_DIS);
733
734 reset_info = g_malloc0(sizeof(ResetData));
735 reset_info->env = env;
736 reset_info->prom_addr = hwdef->prom_addr;
737 qemu_register_reset(main_cpu_reset, reset_info);
738
739 return env;
740 }
741
742 static void sun4uv_init(MemoryRegion *address_space_mem,
743 ram_addr_t RAM_size,
744 const char *boot_devices,
745 const char *kernel_filename, const char *kernel_cmdline,
746 const char *initrd_filename, const char *cpu_model,
747 const struct hwdef *hwdef)
748 {
749 CPUState *env;
750 M48t59State *nvram;
751 unsigned int i;
752 long initrd_size, kernel_size;
753 PCIBus *pci_bus, *pci_bus2, *pci_bus3;
754 ISABus *isa_bus;
755 qemu_irq *irq;
756 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
757 DriveInfo *fd[MAX_FD];
758 void *fw_cfg;
759
760 /* init CPUs */
761 env = cpu_devinit(cpu_model, hwdef);
762
763 /* set up devices */
764 ram_init(0, RAM_size);
765
766 prom_init(hwdef->prom_addr, bios_name);
767
768
769 irq = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
770 pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, irq, &pci_bus2,
771 &pci_bus3);
772 pci_vga_init(pci_bus);
773
774 // XXX Should be pci_bus3
775 isa_bus = pci_ebus_init(pci_bus, -1);
776
777 i = 0;
778 if (hwdef->console_serial_base) {
779 serial_mm_init(address_space_mem, hwdef->console_serial_base, 0,
780 NULL, 115200, serial_hds[i], DEVICE_BIG_ENDIAN);
781 i++;
782 }
783 for(; i < MAX_SERIAL_PORTS; i++) {
784 if (serial_hds[i]) {
785 serial_isa_init(isa_bus, i, serial_hds[i]);
786 }
787 }
788
789 for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
790 if (parallel_hds[i]) {
791 parallel_init(isa_bus, i, parallel_hds[i]);
792 }
793 }
794
795 for(i = 0; i < nb_nics; i++)
796 pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL);
797
798 ide_drive_get(hd, MAX_IDE_BUS);
799
800 pci_cmd646_ide_init(pci_bus, hd, 1);
801
802 isa_create_simple(isa_bus, "i8042");
803 for(i = 0; i < MAX_FD; i++) {
804 fd[i] = drive_get(IF_FLOPPY, 0, i);
805 }
806 fdctrl_init_isa(isa_bus, fd);
807 nvram = m48t59_init_isa(isa_bus, 0x0074, NVRAM_SIZE, 59);
808
809 initrd_size = 0;
810 kernel_size = sun4u_load_kernel(kernel_filename, initrd_filename,
811 ram_size, &initrd_size);
812
813 sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices,
814 KERNEL_LOAD_ADDR, kernel_size,
815 kernel_cmdline,
816 INITRD_LOAD_ADDR, initrd_size,
817 /* XXX: need an option to load a NVRAM image */
818 0,
819 graphic_width, graphic_height, graphic_depth,
820 (uint8_t *)&nd_table[0].macaddr);
821
822 fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
823 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
824 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
825 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
826 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
827 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
828 if (kernel_cmdline) {
829 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
830 strlen(kernel_cmdline) + 1);
831 fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
832 (uint8_t*)strdup(kernel_cmdline),
833 strlen(kernel_cmdline) + 1);
834 } else {
835 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
836 }
837 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
838 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
839 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_devices[0]);
840
841 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width);
842 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height);
843 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth);
844
845 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
846 }
847
848 enum {
849 sun4u_id = 0,
850 sun4v_id = 64,
851 niagara_id,
852 };
853
854 static const struct hwdef hwdefs[] = {
855 /* Sun4u generic PC-like machine */
856 {
857 .default_cpu_model = "TI UltraSparc IIi",
858 .machine_id = sun4u_id,
859 .prom_addr = 0x1fff0000000ULL,
860 .console_serial_base = 0,
861 },
862 /* Sun4v generic PC-like machine */
863 {
864 .default_cpu_model = "Sun UltraSparc T1",
865 .machine_id = sun4v_id,
866 .prom_addr = 0x1fff0000000ULL,
867 .console_serial_base = 0,
868 },
869 /* Sun4v generic Niagara machine */
870 {
871 .default_cpu_model = "Sun UltraSparc T1",
872 .machine_id = niagara_id,
873 .prom_addr = 0xfff0000000ULL,
874 .console_serial_base = 0xfff0c2c000ULL,
875 },
876 };
877
878 /* Sun4u hardware initialisation */
879 static void sun4u_init(ram_addr_t RAM_size,
880 const char *boot_devices,
881 const char *kernel_filename, const char *kernel_cmdline,
882 const char *initrd_filename, const char *cpu_model)
883 {
884 sun4uv_init(get_system_memory(), RAM_size, boot_devices, kernel_filename,
885 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[0]);
886 }
887
888 /* Sun4v hardware initialisation */
889 static void sun4v_init(ram_addr_t RAM_size,
890 const char *boot_devices,
891 const char *kernel_filename, const char *kernel_cmdline,
892 const char *initrd_filename, const char *cpu_model)
893 {
894 sun4uv_init(get_system_memory(), RAM_size, boot_devices, kernel_filename,
895 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[1]);
896 }
897
898 /* Niagara hardware initialisation */
899 static void niagara_init(ram_addr_t RAM_size,
900 const char *boot_devices,
901 const char *kernel_filename, const char *kernel_cmdline,
902 const char *initrd_filename, const char *cpu_model)
903 {
904 sun4uv_init(get_system_memory(), RAM_size, boot_devices, kernel_filename,
905 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[2]);
906 }
907
908 static QEMUMachine sun4u_machine = {
909 .name = "sun4u",
910 .desc = "Sun4u platform",
911 .init = sun4u_init,
912 .max_cpus = 1, // XXX for now
913 .is_default = 1,
914 };
915
916 static QEMUMachine sun4v_machine = {
917 .name = "sun4v",
918 .desc = "Sun4v platform",
919 .init = sun4v_init,
920 .max_cpus = 1, // XXX for now
921 };
922
923 static QEMUMachine niagara_machine = {
924 .name = "Niagara",
925 .desc = "Sun4v platform, Niagara",
926 .init = niagara_init,
927 .max_cpus = 1, // XXX for now
928 };
929
930 static void sun4u_machine_init(void)
931 {
932 qemu_register_machine(&sun4u_machine);
933 qemu_register_machine(&sun4v_machine);
934 qemu_register_machine(&niagara_machine);
935 }
936
937 machine_init(sun4u_machine_init);